Google Git
Sign in
opensecura / hw / kelvin / HEAD
  1. 7ca5eba VCS-based CoreMiniAxi simulator by Alex Van Damme · 9 days ago master
  2. 1813320 1. Add VRF struct in rvv.svh 2. Add some define in rvv_define.svh by Mingzhe Chen · 2 days ago
  3. 021600d Update assertion. by Tianyu Li · 2 days ago
  4. e6060aa add lint flow for RVV by Zhidong Liang · 2 days ago
  5. 5d616da Complete some mask logic instructions in ALU unit (vmandn,vmand,vmor,vmxor.xmorn.vmnand,vmnor.vmxnor). by Tianyu Li · 2 days ago
  6. a27e17d Add common assertion by Tianyu Li · 2 days ago
  7. bcfbc2b change its module name. by Tianyu Li · 2 days ago
  8. 7e8caea Rename/move file(s) by zsp_hw_cd_dev · 2 days ago
  9. 27a4637 Rename/move file(s) by zsp_hw_cd_dev · 2 days ago
  10. d99a309 Add common DFFT and EDFFR. by Tianyu Li · 2 days ago
  11. 963bc1b 1. Complete a mask instruction(vmandn) in alu. 2. Add ignore_vta_vma signal and some signals into ALU_RS_t and ROB_t by Tianyu Li · 2 days ago
  12. bece15c add rvv_vrf_reg module by Zhidong Liang · 2 days ago
  13. 6d388fe Rename/move file(s) by zsp_hw_cd_dev · 2 days ago
  14. 32791d8 add files for rvv module. by Tianyu Li · 2 days ago
  15. 4a81562 add rvv_vrf_reg module and edff common module. by Zhidong Liang · 2 days ago
  16. f4f5197 Fix AWSIZE/ARSIZE default value by Alex Van Damme · 14 hours ago
  17. cffc150 Enable disallowLocalVariables for Core HDL export by Alex Van Damme · 3 days ago
  18. 4be4890 Remove rounding/saturating/doubling scalar mul by Alex Van Damme · 8 days ago
  19. 5c2f175 Swapping out library clockgate to the 6T version. by Srikanth Muroor · 7 days ago
  20. 1f231dd Adjust behavior of Mlu stages by Alex Van Damme · 8 days ago
  21. 24214f9 Add MakeWireBundle by David Gao · 13 days ago
  22. 44bfe32 Remove unnecessary shifting in Axi by Alex Van Damme · 13 days ago
  23. e9d9e1f Lint cleaning RTL fix. by Srikanth Muroor · 2 weeks ago
  24. 9a7d442 Conditionally include FPGA clock gate implementation. by Derek Chow · 2 weeks ago
  25. 773d9ed Define USE_GENERIC in kelvin.core.in by Alex Van Damme · 2 weeks ago
  26. c4958bd Block internal writes to external CSRs by Alex Van Damme · 2 weeks ago
  27. df2fba1 Add TE signal to CoreAxi by Alex Van Damme · 2 weeks ago
  28. 8ab6938 Add optional delays on AXI read addr/data for TCM & CSR by Derek Chow · 3 weeks ago
  29. e9b3905 Import and use SV reset synchronizer by Alex Van Damme · 2 weeks ago
  30. a8773f6 Use Informer in test output by David Gao · 2 weeks ago
  31. 527b8a3 Add entry points to decode compressed RVV inst. by David Gao · 3 weeks ago
  32. 8fbcdcf Apply new test helpers on rvv test by David Gao · 2 weeks ago
  33. eabe45e Create testing helper target by David Gao · 2 weeks ago
  34. 5f28748 Move Reg to RegInit. by Derek Chow · 2 weeks ago
  35. 6f87b50 Add support for building VCS Testbenches. by Derek Chow · 3 weeks ago
  36. d6df5bd Flip CoreAxi IRQ polarity by Alex Van Damme · 3 weeks ago
  37. f1fef4b Add support for ELF to core_mini_axi_sim by Alex Van Damme · 3 weeks ago
  38. 7b58d6a Force Core to use AsyncReset by Alex Van Damme · 3 weeks ago
  39. 812383f Refactor AluTest by David Gao · 7 weeks ago
  40. 72b6508 Implement XNOR, ORN and ANDN. by David Gao · 9 weeks ago
  41. 7b62421 Add denser SRAM macros by Alex Van Damme · 3 weeks ago
  42. b873bcc Plumb enable signal in TCM128 by Alex Van Damme · 3 weeks ago
  43. 61749a8 Embed Git revision as RO CSRs by Alex Van Damme · 3 weeks ago
  44. 25c4bba [lint] Fix undriven input in Slice by Alex Van Damme · 4 weeks ago
  45. 28510db Add a chapter on booting to the integration guide by Alex Van Damme · 4 weeks ago
  46. 5927fbe Add One Cycle Pipeline to io.rd in Lsu.scala by Stefan Hall · 5 weeks ago
  47. 0051302 Set CMAKE_INSTALL_LIBDIR in systemc build by Derek Chow · 4 weeks ago
  48. 0674a80 [CoreAxi] Move DTCM in the memory map, remove io_intr by Alex Van Damme · 4 weeks ago
  49. 9f5c02c Propagate error response back to AXI by Alex Van Damme · 5 weeks ago
  50. 6bb2c83 Update memory map by Alex Van Damme · 5 weeks ago
  51. aa4c418 Make WFI actually stall the core until an interrupt by Alex Van Damme · 6 weeks ago
  52. 593a132 Allow Kelvin to talk to internal peripherals by Alex Van Damme · 7 weeks ago
  53. 7f807ea Add Aligner. by Derek Chow · 7 weeks ago
  54. ba94ee0 Remove the uncached concept and related blocks by Alex Van Damme · 7 weeks ago
  55. f9784f1 Refactoring of AXI by Alex Van Damme · 7 weeks ago
  56. c77811e Add support for AXI WRAP and FIXED bursts. by Alex Van Damme · 7 weeks ago
  57. a9b727e Handle multi-beat AXI bursts to memory by Alex Van Damme · 8 weeks ago
  58. 578d7d0 Create core_mini_axi_sim by Alex Van Damme · 9 weeks ago
  59. f37ddd3 Modify chisel_cc_library to emit SystemC and vanilla by Alex Van Damme · 8 weeks ago
  60. 585de3c Add script to generate airgap tarball by Alex Van Damme · 8 weeks ago
  61. 7d188dd Better defaults for lowRISC prim choice by Alex Van Damme · 8 weeks ago
  62. 7bba666 Guard clock gates via ifdef by Alex Van Damme · 8 weeks ago
  63. 4c6c1be Example of Verilated chiseltest by Alex Van Damme · 9 weeks ago
  64. c47ae96 Move ClockGate to use HasBlackBoxResource. by Derek Chow · 9 weeks ago
  65. 0a4e285 Remove AXI WID signal by Alex Van Damme · 9 weeks ago
  66. bc5cc89 Remove manual tag from rv_core test by Alex Van Damme · 9 weeks ago
  67. 3208be0 Add notes on reset to integration guide by Alex Van Damme · 9 weeks ago
  68. 0194b75 Allow LSU to choose where to read based on addr by Alex Van Damme · 3 months ago
  69. 1c788bd Add Sign and Zero extension to ALU by Stefan Hall · 2 months ago
  70. 22feac5 Change CoreAxi + renode to active-low reset by Alex Van Damme · 9 weeks ago
  71. 5247b3f Actually write to CSRs based on writeAddr by Alex Van Damme · 9 weeks ago
  72. c79770f Add Decode support for WFI by Alex Van Damme · 10 weeks ago
  73. e442823 Generate split verilog. by Derek Chow · 2 months ago
  74. 9d24666 Improve SRAM practices a bit. by Derek Chow · 2 months ago
  75. 1255d62 Add TSMC12FFCP 128x128 SRAM as TCM SRAM for kelvin sim by Stefan Hall · 3 months ago
  76. c4d1366 Remove glibc-2.37 from Kelvin by Alex Van Damme · 4 months ago
  77. cbb320a Implement RVV Instruction Stage 1 Decoder (1) by David Gao · 3 months ago
  78. e706af6 Add verilog_zip_bundle to package all verilog sources for release. by Derek Chow · 3 months ago
  79. 17ed624 Run a Verilated CoreMiniAxi in Renode by Alex Van Damme · 3 months ago
  80. 94d1e41 Mux AXI to multiple ports in CoreAxi by Alex Van Damme · 3 months ago
  81. 87d20c7 Start integration guide for Kelvin. by Derek Chow · 3 months ago
  82. 9e2d034 Add utility for building AXI peripherals. by Derek Chow · 3 months ago
  83. 7853614 Set interrupts as inputs. by Derek Chow · 3 months ago
  84. dcb0af3 [CoreAxi] Fix sizes of ITCM, DTCM by Alex Van Damme · 3 months ago
  85. 048fb75 Adjust top-level interface for CoreAxi by Alex Van Damme · 3 months ago
  86. d82518d [CoreMiniAxi] ITCM, DTCM by Alex Van Damme · 3 months ago
  87. f4d983d Generate FST instead of VCD by Alex Van Damme · 3 months ago
  88. a04ed7b Flesh out AXI signal definitions by Alex Van Damme · 3 months ago
  89. d313b73 Create AXI wrapper around Core by Alex Van Damme · 3 months ago
  90. 28abdce CoreMini / KelvinMini with 128-bit memory config by Alex Van Damme · 4 months ago
  91. 17fc093 Set X extension based on enableVector by Alex Van Damme · 4 months ago
  92. f2f7391 Flag to enable/disable vector by Alex Van Damme · 4 months ago
  93. 59e47ce Add a cache-free fetch unit by Alex Van Damme · 4 months ago
  94. a952486 Refactor Kelvin's BUILD targets by Alex Van Damme · 4 months ago
  95. 5662e4a Fix --trace for Kelvin sims/testbenches by Alex Van Damme · 4 months ago
  96. b912a80 Add flush to InstructionBuffer. by Derek Chow · 4 months ago
  97. 543e589 Merge "Convert FetchInstruction to use Decoupled." by Derek Chow · 4 months ago
  98. 6134e85 Merge "Fix broken bazel build target in README.md" by Derek Chow · 4 months ago
  99. 99cd4a0 Convert FetchInstruction to use Decoupled. by Derek Chow · 4 months ago
  100. 605d937 Merge "Add InstructionBuffer." by Derek Chow · 4 months ago