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opensecura
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hw
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kelvin
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fe660cf
fix problem
by Tianyu Li
· 9 days ago
master
43d08d6
adjust assertion
by Tianyu Li
· 9 days ago
e7ac0dd
1. ignore_vma and ignore_vta changes; 2. Fix dispatch byte_type problem
by Tianyu Li
· 9 days ago
c8d39bd
Remove ignore_vta/vma in mulmac ex and retire
by Mingzhe Chen
· 9 days ago
735e92d
fix typo of previous submit
by Pu Wang
· 10 days ago
b457ab8
1. adjust assertion; 2. Add ignore_vma and ignore_vta in decoder; 3. fix problem for read ports assignment in dispatch.
by Tianyu Li
· 10 days ago
d80371f
1.Update check info display. 2.Fix DUT vrf retire value sample problem
by Pu Wang
· 10 days ago
fe7f8bd
Fix rob hit logic of vrf bypass
by Zhidong Liang
· 10 days ago
77d497f
1. dispatch should use evl to distinguish TAIL and BODY; 2. diviver should record dividend and divisor even if divisor equals to 0.
by Tianyu Li
· 10 days ago
8ce327a
Update testbench: 1. Update retire monitor & checker of vrf/xrf/vxsat. 2. Update retire transactions. Now it support full issue dispatch. 3. Fix check scripts ignore UVM_FATAL problem.
by Pu Wang
· 10 days ago
8da8e6b
update support signals which only used in tb
by Pu Wang
· 10 days ago
e7f7d59
Fix the problem of read ports of VRF assignment.
by Tianyu Li
· 11 days ago
213d4d8
update illegal inst check in mdl
by Pu Wang
· 11 days ago
1ba7c50
Fix some typo in comments
by Mingzhe Chen
· 13 days ago
fc8588e
fix overlap check problem for vwmaccus instruction
by Tianyu Li
· 13 days ago
3514e3c
1. fix problem for shift instruction; 2. fix problem for divider; 3. fix byte_type logic in dispatch
by Tianyu Li
· 13 days ago
a821fec
fix illegal instruction check for narrow shift
by Pu Wang
· 14 days ago
a08fce5
Emit verilog files for alu, mlu and dvu modules
by Yenkai Wang
· 6 days ago
93963ad
Add @com_github_grpc_grpc//:all to airgap for lint
by Matthew Wilson
· 6 days ago
5cfb408
Fix vwmacc logic
by Pu Wang
· 2 weeks ago
5f52f0e
Fix vrf index decoder for VV && vd_valid conditon
by Zhidong Liang
· 2 weeks ago
af610eb
Fix widen mac bug
by Mingzhe Chen
· 2 weeks ago
2475443
Bug fix
by Mingzhe Chen
· 2 weeks ago
9f62adb
ignore opivi for vmin/vmax
by Pu Wang
· 2 weeks ago
556c76d
update mdl 1. Fix emul of mask instructions 2. fix div logic
by Pu Wang
· 2 weeks ago
b4b4d2d
fix divider problem
by Tianyu Li
· 2 weeks ago
05405be
1. update the logic for vadc/vdiv instruction
by Tianyu Li
· 2 weeks ago
53922c5
add last_seq in each test to clean inst_queue in mdl
by Pu Wang
· 2 weeks ago
ca06d34
Fix assertion of vadc/vsbc
by Pu Wang
· 2 weeks ago
f79906c
fix result_valid problem in divider, because divider is not 1 cycle latency.
by Tianyu Li
· 2 weeks ago
68236c9
fix vs3_valid for vmadc and vmsbc instructions
by Tianyu Li
· 2 weeks ago
070e950
fix timing problem for viota
by Tianyu Li
· 2 weeks ago
268fb2e
fix vadcsbc sequence
by Pu Wang
· 2 weeks ago
b965c4b
add final check to mdl
by Pu Wang
· 2 weeks ago
f2ccddf
fix mask inst logic&test
by Pu Wang
· 2 weeks ago
9714b6a
Fix signed*unsigned issue
by Mingzhe Chen
· 2 weeks ago
f17a1dd
fix viota problem
by Tianyu Li
· 2 weeks ago
cb2e7e6
Fix mask generation issue when ignore_vta/vma
by Mingzhe Chen
· 2 weeks ago
d70ad09
Update error check
by Pu Wang
· 2 weeks ago
3947ecb
delete unused assertion
by Tianyu Li
· 2 weeks ago
58fb76c
RTL make the opposite f_and and f_andn.
by Tianyu Li
· 2 weeks ago
29b8cf0
update mul functions
by Pu Wang
· 2 weeks ago
583ccde
open div/bitlogic/shift test
by Pu Wang
· 2 weeks ago
b8a5864
fix shift amount
by Pu Wang
· 2 weeks ago
48ea2f3
fix typo
by Mingzhe Chen
· 2 weeks ago
15413ff
dispatch miss to send 'vl' to ALU_RS
by Tianyu Li
· 2 weeks ago
47d09fb
fix typo of vmul opmvx decoder
by Pu Wang
· 2 weeks ago
9c808e2
Fix mul8 index issue
by Mingzhe Chen
· 2 weeks ago
22f2455
don't point to head of log after grep
by Pu Wang
· 2 weeks ago
d20c902
Add assert fail number print
by Pu Wang
· 2 weeks ago
24fd1ea
modify the RTL to use $signed to complete sign-extend and simplify the code
by Tianyu Li
· 2 weeks ago
c9db3d4
optimize timing for addsub
by Tianyu Li
· 2 weeks ago
d35aad1
Open vadcsbc & vmul test. Add them to smoke test.
by Pu Wang
· 2 weeks ago
3cd304d
update vrf display format
by Pu Wang
· 2 weeks ago
dddff35
updated VXUNARY0 related sequence reference model. Fix illegal check of ref model.
by Pu Wang
· 2 weeks ago
0525f45
delete unused code
by Tianyu Li
· 2 weeks ago
1d24e5b
Update vext sew related assertions. Fix vext decode typo.
by Pu Wang
· 2 weeks ago
7fb768c
optimize timing for viota instruction
by Tianyu Li
· 2 weeks ago
2b6a902
change PMTRDT to PMT and RDT
by Tianyu Li
· 2 weeks ago
aff61d8
split PMTRDT to PMT and RDT marker.
by Tianyu Li
· 2 weeks ago
9891658
fix sign-extend problem for widening add instruction.
by Tianyu Li
· 2 weeks ago
2d42f19
Add illegal check for vsub.vi
by Pu Wang
· 3 weeks ago
82614c7
1. Fix assertion, rollback to 1066434; 2. rvv_backend.sv top has ready generation issue to LSU RS, fixed
by Mingzhe Chen
· 3 weeks ago
6378556
Fix typo in comment
by Mingzhe Chen
· 3 weeks ago
5f011e3
Fix assertion issue, a test cl#
by Mingzhe Chen
· 3 weeks ago
878ff6c
Emit actual request address on AXI-M txns
by Alex Van Damme
· 9 days ago
3378dff
Fix assertion issue
by Mingzhe Chen
· 3 weeks ago
27fc86a
Add assertion to illegal behavior in fifos
by Mingzhe Chen
· 3 weeks ago
3b9fe8e
fix sign-entend problem for widening instructions
by Tianyu Li
· 3 weeks ago
f3a80a0
add assertion info
by Tianyu Li
· 3 weeks ago
9aa1d12
fix assertion problem
by Tianyu Li
· 3 weeks ago
c594547
Add a feature: If both the quotient and remainder are required from the same division, divider can get the result of quotient and remainder together in one computing process instead of performing two separate divides operation.
by Tianyu Li
· 3 weeks ago
f2b767d
update rvs_driver for single inst mode.
by Pu Wang
· 3 weeks ago
ec67cc3
fix behavior model of vwadd/sub functions. Add a alu_smoke test as qualify test.
by Pu Wang
· 3 weeks ago
0b964a2
fix assertion problem
by Tianyu Li
· 3 weeks ago
ba4f84a
Add assertion for the situation when an instruction is decoded to 0 uop.
by Tianyu Li
· 3 weeks ago
af32a47
fix subtract and vxsat problem
by Tianyu Li
· 3 weeks ago
7b363e8
Add smoke test to run each inst once. Fix rt_event judgment for tb.
by Pu Wang
· 3 weeks ago
eff6beb
Fix bug where WAW01 not check addr
by Mingzhe Chen
· 3 weeks ago
4fcd3fb
Add debug logic under TB_SUPPORT define
by Mingzhe Chen
· 3 weeks ago
776d7c5
fix rvs_driver: pop inst_queue first
by Pu Wang
· 3 weeks ago
c076791
Add div unit TOP file
by Tianyu Li
· 3 weeks ago
ae9d9ed
fix a wrong signal name
by Tianyu Li
· 3 weeks ago
f4e94fc
Add DIV unit in TOP module
by Tianyu Li
· 3 weeks ago
fd587fc
remove macro for tb
by Tianyu Li
· 3 weeks ago
1081e96
fix the code for wrong subtract
by Tianyu Li
· 3 weeks ago
3065f07
fix the code for pop signal to Command Queue
by Tianyu Li
· 3 weeks ago
1621112
fix the code for wrong body-active and body-inactive judment.
by Tianyu Li
· 3 weeks ago
3019139
update behavior model print message control
by Pu Wang
· 3 weeks ago
49946de
Fix tb_log gen
by Pu Wang
· 3 weeks ago
41b7ae2
Add MUL/MAC to rvv_backend top
by Mingzhe Chen
· 3 weeks ago
b420701
Change signal names
by Mingzhe Chen
· 3 weeks ago
c3ab915
update test log generate
by Pu Wang
· 3 weeks ago
14ce83b
Initial version of MUL/MAC top wrapper
by Mingzhe Chen
· 3 weeks ago
fb596aa
fix ^M problem
by Tianyu Li
· 3 weeks ago
9aebc90
update illegal inst check in behavior model.
by Pu Wang
· 3 weeks ago
880e0ff
fix pointer overflow
by Pu Wang
· 3 weeks ago
3ff6190
change overlap v0 assert to warning
by Pu Wang
· 3 weeks ago
90de860
fix v0_data_in_use signal.
by Tianyu Li
· 3 weeks ago
49e7415
fix a bug that pop signal should be valid when the number of decoded uops is 0.
by Tianyu Li
· 3 weeks ago
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