Google Git
Sign in
opensecura / hw / kelvin / HEAD
  1. cd84f01 Add load16/32_index8 tests by David Gao · 18 hours ago master
  2. f906d35 Fix wrong results for mixed prec indexed loads by David Gao · 2 days ago
  3. 38e3297 [rvvi] Handle vd conflicts for vector tracing by Alex Van Damme · 8 days ago
  4. c2c02f7 Add vsseg*e16/32 tests by David Gao · 2 days ago
  5. 4aa97a9 feat(dv): Add Python-based SPI loader for Verilator by Alex Van Damme · 3 weeks ago
  6. 5fad6ba feat(fpga): Integrate Chisel Subsystem into FPGA build by Alex Van Damme · 3 weeks ago
  7. 5a16231 feat(fpga): Add SPI DPI Master for Verilator simulation by Alex Van Damme · 3 weeks ago
  8. bd14438 refactor(soc): Introduce unified KelvinChiselSubsystem by Alex Van Damme · 3 weeks ago
  9. 813d03e feat(spi): Increase Spi2TLUL bulk transfer size to 16-bit by Alex Van Damme · 3 days ago
  10. 7759a66 Consolidate load8/16/32 segmented test cases by David Gao · 3 days ago
  11. 6178d5d Fix segmented load-store register layout by David Gao · 4 days ago
  12. acf084c Adjust vector register order in Decoder for segment load/store. Update rvv_backend_tb for lsu changes. by tianyu.li · 3 days ago
  13. 19eeec6 Add segmented store8 tests by David Gao · 5 days ago
  14. 5ae9689 Fix load segment2 m2 test cases by David Gao · 3 days ago
  15. d28bde0 feat(spi2tlul): Implement efficient bulk data transfers by Alex Van Damme · 11 days ago
  16. 707495c [dv, flow] Add ELF loader feature by Yenkai Wang · 12 days ago
  17. 725eb3b Add VLM/VSM tests by David Gao · 5 days ago
  18. 10dea54 Handle masked loads and stores. by Derek Chow · 8 days ago
  19. 56decb0 Switch from VLM to VLE in VCPOP tests by David Gao · 8 days ago
  20. c775ee3 Refactoring core parts of toolchain_kelvin_v2 by Naveen Dodda · 10 days ago
  21. a1149e1 Confirm no more rvv instructions write rd by David Gao · 11 days ago
  22. 6506d56 Update ClockGate.sv to support GF22 by Stefan Hall · 2 weeks ago
  23. 7fc2fcc Add vill bit to config state and trap on bad state. by Derek Chow · 11 days ago
  24. 2133ce9 feat(spi): Add packed write transaction support by Alex Van Damme · 11 days ago
  25. d79c4a7 Minor BUILD fixups for vcs_sim by Alex Van Damme · 11 days ago
  26. 63cdfa9 [dv] Implement tohost termination mechanism by Yenkai Wang · 12 days ago
  27. faeb564 Add vstart check for additional instructions by David Gao · 2 weeks ago
  28. 88b0bbd feat(soc): Add Spi2TLUL bridge and tests by Alex Van Damme · 3 weeks ago
  29. a9ce01c Add vtype CSR. by Derek Chow · 2 weeks ago
  30. 8f96ae7 Update rvv_idle signal to include frontend and fix mpause dispatch. by Derek Chow · 2 weeks ago
  31. 7e33217 fix(cocotb): Correct decorator syntax in debug test by Alex Van Damme · 3 weeks ago
  32. 4278579 Mask LsuV2 regfile writes based on faults. by Derek Chow · 2 weeks ago
  33. dfae871 Apply masks to all write ports. by Derek Chow · 2 weeks ago
  34. 2affd50 CircularBufferMulti replace when with Mux by Stefan Hall · 3 weeks ago
  35. f66f498 Fault for reduction instructions when vstart != 0. by Derek Chow · 3 weeks ago
  36. 7eb4dec Add SvGenerationUtils. by Derek Chow · 3 weeks ago
  37. 296d738 fix(cocotb): Improve test discovery for tests with arguments by Alex Van Damme · 5 weeks ago
  38. 6edcd4e refactor(fpga): Replace tlgen xbar with Chisel-based KelvinXbar by Alex Van Damme · 5 weeks ago
  39. 0004fc3 feat(soc): Add data-driven TileLink-UL crossbar by Alex Van Damme · 5 weeks ago
  40. be106f1 feat(bus): Add TileLink-UL primitives by Alex Van Damme · 5 weeks ago
  41. 148e450 refactor(bus): Clean up AXI/TL-UL bridges and tests by Alex Van Damme · 5 weeks ago
  42. b9b0d55 feat(bus): Add SECDED integrity for TileLink-UL by Alex Van Damme · 5 weeks ago
  43. 131a9c5 feat(hdl): Add rocket-chip AsyncQueue and smoke test by Alex Van Damme · 5 weeks ago
  44. 9eaf5f1 Remove extra vd from RvvCompressedInstruction by Alex Van Damme · 5 weeks ago
  45. d0b475a Matmul rvv intrinsics in cpp by Naveen Dodda · 6 weeks ago
  46. 129b346 Generic test bench for loads/stores. by Derek Chow · 6 weeks ago
  47. 98e88c4 Add RVV to tracing by Alex Van Damme · 2 months ago
  48. 1aee13e Add support for RVV for kelvin simulator by Lun Dong · 6 weeks ago
  49. 814bc6c Update debug docs to reflect new addresses. by Derek Chow · 6 weeks ago
  50. e4d283f Move debug CSR addresses by Alex Van Damme · 6 weeks ago
  51. c16307d feat(fpga): Add Kelvin SoC top-level and build infrastructure by Alex Van Damme · 7 weeks ago
  52. 59bb2dd feat(fpga): Add supporting IPs for Kelvin SoC by Alex Van Damme · 7 weeks ago
  53. a9d0294 feat(fpga): Add Ibex core IP and generation docs by Alex Van Damme · 7 weeks ago
  54. 502e0d9 feat(build): Add FPGA toolchain support and enhance binary rules by Alex Van Damme · 7 weeks ago
  55. 3a18e1d refactor(hdl): Make CoreAxiCSR bus-width agnostic by Alex Van Damme · 7 weeks ago
  56. 4782b76 feat(hdl): Add Chisel TL-UL <-> AXI bridges and CoreTlul by Alex Van Damme · 7 weeks ago
  57. 97b73bf Clean lint warning: W416b,W362,W486... by zsp_hw_cd_dev · 7 weeks ago
  58. 088a577 update monitor in rvv backend tb by pu.wang · 8 weeks ago
  59. 8dc9126 Update rvv_backend exclusion file by pu.wang · 9 weeks ago
  60. 7f34b17 update waiver file for decoder by Tianyu · 10 weeks ago
  61. c0600ce update backend exclusion files by pu.wang · 10 weeks ago
  62. 150b1ae Fix constraint reserve inst by pu.wang · 2 months ago
  63. 9bb0dd9 Fill in unreachable state in cvfpu. by Derek Chow · 7 weeks ago
  64. ee09cb6 Expose VL through Csr. by Derek Chow · 7 weeks ago
  65. 6681f8f Connect xsat to CSR. by Derek Chow · 7 weeks ago
  66. c1c61ea Generate kelvin_simulator library and clean-ups by Lun Dong · 8 weeks ago
  67. 8977fc3 Fix scoreboarding issue in vsetvli. by Derek Chow · 7 weeks ago
  68. cd4c5d1 Matmul with Rvv intrinsics by Naveen Dodda · 2 months ago
  69. 4779c1d [dv, cosim] Enable lock-step PC and GPR verification with MPACT-Sim by Yenkai Wang · 8 weeks ago
  70. a48057d Fix some lint errors in RvvFrontEnd. by Derek Chow · 8 weeks ago
  71. 1561552 Allow LSU to accept multiple instructions in one cycle. by Derek Chow · 8 weeks ago
  72. 8cd3a3a Add CSR tracing to RVVI by Alex Van Damme · 2 months ago
  73. ab6d5df Widen math ops rvv intrinsics test. by Naveen Dodda · 9 weeks ago
  74. 72f32eb Reorder declaration of queue_capacity_internal. by Derek Chow · 8 weeks ago
  75. 94d7eb5 Respect queue counts in Lsu and Rvv. by Derek Chow · 9 weeks ago
  76. ce92821 Update tutorial documentation to reflect using cocotb_test_suite. by Derek Chow · 8 weeks ago
  77. bad4bf4 feat(debug): Transition debug module to CSR-based interface by Alex Van Damme · 8 weeks ago
  78. 21d428a Improve cocotb Bazel rules by Alex Van Damme · 10 weeks ago
  79. d0fe663 Parameterize RvvCore.scala based on VL. by Derek Chow · 9 weeks ago
  80. 3cf9083 rules: Query C++ toolchain for cocotb builds by Alex Van Damme · 9 weeks ago
  81. 4570a53 Fix(dispatch): Prevent FPU/LSU hazard in DispatchV1 by Alex Van Damme · 9 weeks ago
  82. ea45a72 [rvv] Fix enum assignment warnings by Alex Van Damme · 9 weeks ago
  83. c7d94b7 Debug readability improvement by Alex Van Damme · 10 weeks ago
  84. 0ecdd4b Enable tracing in verilator_cocotb_model by Alex Van Damme · 10 weeks ago
  85. 95ee0df Update assertions in RvvFrontEnd. by Derek Chow · 9 weeks ago
  86. 1250c67 Fix: Prevent X-propagation in debug module by Alex Van Damme · 9 weeks ago
  87. 1cfc86d Unset and forward user's LD_LIBRARY_PATH in cocotb by Alex Van Damme · 10 weeks ago
  88. 2c785ad Create filgroup targets for test binaries. by Derek Chow · 10 weeks ago
  89. 57b3918 Add tests for RVV reduction operations by Alex Van Damme · 2 months ago
  90. ed78b70 Separate cocotb build from test for Verilator by Alex Van Damme · 2 months ago
  91. d1a684d Adjust coding style to assign sub-fields of the same struct signal in a single always-block for tool-friendly. by Tianyu Li · 10 weeks ago v2-RC02
  92. aa3f712 Add debug version of core. by Derek Chow · 10 weeks ago
  93. e42e486 Add queue to AXI master output write. by Derek Chow · 10 weeks ago
  94. b8e7e6d Support for segmented loads. by Derek Chow · 2 months ago v2-RC01
  95. 546429b Relax size in AXI transactions. by Derek Chow · 2 months ago
  96. b6b2707 Add indexed load/store support. by Derek Chow · 2 months ago
  97. 0372375 Add vstart and vxrm to Csr. by Derek Chow · 2 months ago
  98. 350a35d Plumb rvv_idle output RvvCore. by Derek Chow · 2 months ago
  99. 653a908 merge derek change in vrf and update tb by pu.wang · 2 months ago
  100. 5a69943 Update exclusiton files by pu.wang · 3 months ago