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opensecura/hw/kelvin/HEAD
  1. fb6ba01 Finish intrinsic coverage for indexed stores by David Gao · 11 months ago master
  2. 57e3ee8 Remaining segmented load tests by Naveen Dodda · 11 months ago
  3. d1b0689 Increase sizes for tests that are timing out by Matthew Wilson · 11 months ago
  4. b4920b0 Add GF22 Compiled Memories to Design by Stefan Hall · 11 months ago
  5. 506654c Buildify cocotb, verilator-sim and chisel/common by Matthew Wilson · 11 months ago
  6. ca75d61 Add whole register into Lsu. by Derek Chow · 11 months ago
  7. 6957184 Fix rvv load/store non-indexed decoding by David Gao · 11 months ago
  8. 6d60671 Add tests for strided/strided-segmented loads/stores. by Derek Chow · 11 months ago
  9. 7c440a9 Add tests for unit/unit-segmented loads/stores. by Derek Chow · 11 months ago
  10. e494a11 Saturate vl in RvvFrontEnd.sv by Derek Chow · 11 months ago
  11. 46c5a0e Fix for loads > 8 steps by David Gao · 11 months ago
  12. ad3a1d1 Segmented load test for load16_index32 by Naveen Dodda · 11 months ago
  13. 51e5726 Increase size of kelvin_scalar_tests to prevent timeouts by Matthew Wilson · 11 months ago
  14. 8a10a6e Run buildifier on hdl/chisel/src/kelvin/BUILD by Matthew Wilson · 11 months ago
  15. 1ca123c Address STARC05-1.3.1.3 lint issues. by Derek Chow · 11 months ago
  16. a6c5d7f Test segmented store8 index8 by David Gao · 11 months ago
  17. 5dd68fa Test load8 index32 segmented by David Gao · 11 months ago
  18. c38bef0 Simplify indexed load testing by David Gao · 11 months ago
  19. a715d40 Test load16 index8 segmented by David Gao · 11 months ago
  20. 6fc717d Simplify compiler bug workaround by David Gao · 11 months ago
  21. 2ba772e [dv, cosim] Refactor co-sim DPI to use an unified 'mpact_get_register' API by Yenkai Wang · 11 months ago
  22. a0ccb58 [dv, cosim] Enable ELF loading in MPACT co-simulation model by Yenkai Wang · 11 months ago
  23. 42fc549 Mark vl and vtype as clobbered in inline asm by David Gao · 11 months ago
  24. 2b17092 Add tests for unit masked loads/stores. by Derek Chow · 11 months ago
  25. 791179d Update RVVI url to point to commit instead of branch. by Derek Chow · 11 months ago
  26. 783e3e3 Fix element length for segmented indexed loads by David Gao · 11 months ago
  27. 1a79d06 TFMicro integration into KelvinV2 ecosystem. by Naveen Dodda · 1 year ago
  28. 3b119f8 Extend segmented indexed load test coverage by David Gao · 11 months ago
  29. 03fa31a Set Clock Frequency for cocotb Sims to 800MHz by Stefan Hall · 11 months ago
  30. bfe7c24 Fix segmented indexed loads by David Gao · 11 months ago
  31. e0cdcd6 Improve coverage for indexed stores ddtype > idtype. by Derek Chow · 11 months ago
  32. 651c585 Fix index>data indexed load >m1 by David Gao · 11 months ago
  33. 1579478 LSU state machine for vector loops by David Gao · 11 months ago
  34. 9596c40 Set vill based on sew and lmul. by Derek Chow · 11 months ago
  35. a326cd5 Expand tests for indexed store of same ddtype and idtype. by Derek Chow · 11 months ago
  36. e7c87ff Apply inline asm only to vle in indexed load tests by David Gao · 11 months ago
  37. 6e984db Improve support for mixed dtype indexed loads/stores. by Derek Chow · 11 months ago
  38. cd84f01 Add load16/32_index8 tests by David Gao · 11 months ago
  39. f906d35 Fix wrong results for mixed prec indexed loads by David Gao · 11 months ago
  40. 38e3297 [rvvi] Handle vd conflicts for vector tracing by Alex Van Damme · 12 months ago
  41. c2c02f7 Add vsseg*e16/32 tests by David Gao · 11 months ago
  42. 4aa97a9 feat(dv): Add Python-based SPI loader for Verilator by Alex Van Damme · 12 months ago
  43. 5fad6ba feat(fpga): Integrate Chisel Subsystem into FPGA build by Alex Van Damme · 12 months ago
  44. 5a16231 feat(fpga): Add SPI DPI Master for Verilator simulation by Alex Van Damme · 12 months ago
  45. bd14438 refactor(soc): Introduce unified KelvinChiselSubsystem by Alex Van Damme · 12 months ago
  46. 813d03e feat(spi): Increase Spi2TLUL bulk transfer size to 16-bit by Alex Van Damme · 11 months ago
  47. 7759a66 Consolidate load8/16/32 segmented test cases by David Gao · 11 months ago
  48. 6178d5d Fix segmented load-store register layout by David Gao · 11 months ago
  49. acf084c Adjust vector register order in Decoder for segment load/store. Update rvv_backend_tb for lsu changes. by tianyu.li · 11 months ago
  50. 19eeec6 Add segmented store8 tests by David Gao · 11 months ago
  51. 5ae9689 Fix load segment2 m2 test cases by David Gao · 11 months ago
  52. d28bde0 feat(spi2tlul): Implement efficient bulk data transfers by Alex Van Damme · 12 months ago
  53. 707495c [dv, flow] Add ELF loader feature by Yenkai Wang · 12 months ago
  54. 725eb3b Add VLM/VSM tests by David Gao · 11 months ago
  55. 10dea54 Handle masked loads and stores. by Derek Chow · 12 months ago
  56. 56decb0 Switch from VLM to VLE in VCPOP tests by David Gao · 12 months ago
  57. c775ee3 Refactoring core parts of toolchain_kelvin_v2 by Naveen Dodda · 12 months ago
  58. a1149e1 Confirm no more rvv instructions write rd by David Gao · 12 months ago
  59. 6506d56 Update ClockGate.sv to support GF22 by Stefan Hall · 12 months ago
  60. 7fc2fcc Add vill bit to config state and trap on bad state. by Derek Chow · 12 months ago
  61. 2133ce9 feat(spi): Add packed write transaction support by Alex Van Damme · 12 months ago
  62. d79c4a7 Minor BUILD fixups for vcs_sim by Alex Van Damme · 12 months ago
  63. 63cdfa9 [dv] Implement tohost termination mechanism by Yenkai Wang · 12 months ago
  64. faeb564 Add vstart check for additional instructions by David Gao · 12 months ago
  65. 88b0bbd feat(soc): Add Spi2TLUL bridge and tests by Alex Van Damme · 12 months ago
  66. a9ce01c Add vtype CSR. by Derek Chow · 12 months ago
  67. 8f96ae7 Update rvv_idle signal to include frontend and fix mpause dispatch. by Derek Chow · 12 months ago
  68. 7e33217 fix(cocotb): Correct decorator syntax in debug test by Alex Van Damme · 12 months ago
  69. 4278579 Mask LsuV2 regfile writes based on faults. by Derek Chow · 12 months ago
  70. dfae871 Apply masks to all write ports. by Derek Chow · 12 months ago
  71. 2affd50 CircularBufferMulti replace when with Mux by Stefan Hall · 12 months ago
  72. f66f498 Fault for reduction instructions when vstart != 0. by Derek Chow · 12 months ago
  73. 7eb4dec Add SvGenerationUtils. by Derek Chow · 12 months ago
  74. 296d738 fix(cocotb): Improve test discovery for tests with arguments by Alex Van Damme · 1 year ago
  75. 6edcd4e refactor(fpga): Replace tlgen xbar with Chisel-based KelvinXbar by Alex Van Damme · 1 year ago
  76. 0004fc3 feat(soc): Add data-driven TileLink-UL crossbar by Alex Van Damme · 1 year ago
  77. be106f1 feat(bus): Add TileLink-UL primitives by Alex Van Damme · 1 year ago
  78. 148e450 refactor(bus): Clean up AXI/TL-UL bridges and tests by Alex Van Damme · 1 year ago
  79. b9b0d55 feat(bus): Add SECDED integrity for TileLink-UL by Alex Van Damme · 1 year ago
  80. 131a9c5 feat(hdl): Add rocket-chip AsyncQueue and smoke test by Alex Van Damme · 1 year ago
  81. 9eaf5f1 Remove extra vd from RvvCompressedInstruction by Alex Van Damme · 1 year ago
  82. d0b475a Matmul rvv intrinsics in cpp by Naveen Dodda · 1 year ago
  83. 129b346 Generic test bench for loads/stores. by Derek Chow · 1 year ago
  84. 98e88c4 Add RVV to tracing by Alex Van Damme · 1 year, 2 months ago
  85. 1aee13e Add support for RVV for kelvin simulator by Lun Dong · 1 year, 1 month ago
  86. 814bc6c Update debug docs to reflect new addresses. by Derek Chow · 1 year, 1 month ago
  87. e4d283f Move debug CSR addresses by Alex Van Damme · 1 year, 1 month ago
  88. c16307d feat(fpga): Add Kelvin SoC top-level and build infrastructure by Alex Van Damme · 1 year, 1 month ago
  89. 59bb2dd feat(fpga): Add supporting IPs for Kelvin SoC by Alex Van Damme · 1 year, 1 month ago
  90. a9d0294 feat(fpga): Add Ibex core IP and generation docs by Alex Van Damme · 1 year, 1 month ago
  91. 502e0d9 feat(build): Add FPGA toolchain support and enhance binary rules by Alex Van Damme · 1 year, 1 month ago
  92. 3a18e1d refactor(hdl): Make CoreAxiCSR bus-width agnostic by Alex Van Damme · 1 year, 1 month ago
  93. 4782b76 feat(hdl): Add Chisel TL-UL <-> AXI bridges and CoreTlul by Alex Van Damme · 1 year, 1 month ago
  94. 97b73bf Clean lint warning: W416b,W362,W486... by zsp_hw_cd_dev · 1 year, 1 month ago
  95. 088a577 update monitor in rvv backend tb by pu.wang · 1 year, 1 month ago
  96. 8dc9126 Update rvv_backend exclusion file by pu.wang · 1 year, 1 month ago
  97. 7f34b17 update waiver file for decoder by Tianyu · 1 year, 1 month ago
  98. c0600ce update backend exclusion files by pu.wang · 1 year, 1 month ago
  99. 150b1ae Fix constraint reserve inst by pu.wang · 1 year, 2 months ago
  100. 9bb0dd9 Fill in unreachable state in cvfpu. by Derek Chow · 1 year, 1 month ago