| commit | 8ab6938bdf437c1938af6d7fd8653e177a18a8f6 | [log] [tgz] |
|---|---|---|
| author | Derek Chow <derekjchow@google.com> | Thu Oct 31 13:56:50 2024 -0700 |
| committer | Alex Van Damme <atv@google.com> | Tue Nov 05 23:41:33 2024 +0000 |
| tree | 6b27c471758665f46a8ea58aa3055303e57884a4 | |
| parent | e9b390515dfd8f02b9f01c10660bed9fa27db369 [diff] |
Add optional delays on AXI read addr/data for TCM & CSR This helps with timing. Change-Id: I74a3246b226005c9d21b4d1313aab008aec75899
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog