)]}' { "log": [ { "commit": "fb6ba01ff3808df699da1403c15ba2b5219c068a", "tree": "ef24e9423867ba3b19ea4356c919807a2ccd33a5", "parents": [ "57e3ee84ac53ebdb5f2013e015e9c2d8aa6ea071" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 30 20:58:21 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Oct 06 17:40:39 2025 +0000" }, "message": "Finish intrinsic coverage for indexed stores\n\nChange-Id: I2b655b4f7a0588eaf6a6b553b9a43818a16382f1\n" }, { "commit": "57e3ee84ac53ebdb5f2013e015e9c2d8aa6ea071", "tree": "f6db34d2aa8230543bc69e2973b3e05cdd9c9010", "parents": [ "d1b068938f0abd949a248d9b50779aed1a11527f" ], "author": { "name": "Naveen Dodda", "email": "ndodda@google.com", "time": "Thu Oct 02 01:31:07 2025 +0000" }, "committer": { "name": "Naveen Dodda", "email": "ndodda@google.com", "time": "Fri Oct 03 15:48:31 2025 -0700" }, "message": "Remaining segmented load tests\n\n* This test uses workaround for compiler bug\n* Adds indexed segmented loads for SEW 32 for index width 16, 8\n* Test : bazel run //tests/cocotb:rvv_load_store_test_load32_index16_seg\n bazel run //tests/cocotb:rvv_load_store_test_load32_index8_seg\n\nChange-Id: I1462a3143db9228a3e42315fcf14179e51f51044\n" }, { "commit": "d1b068938f0abd949a248d9b50779aed1a11527f", "tree": "8c550871b133077bed729f4aa6fac12ee2b79845", "parents": [ "b4920b0f490206ba7cb4b584f04c6cf48ddfa3ad" ], "author": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Fri Oct 03 12:03:10 2025 -0700" }, "committer": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Fri Oct 03 14:59:12 2025 -0700" }, "message": "Increase sizes for tests that are timing out\n\nchisel_test was erasing test sizes causing all tests to be size medium\n\nChange-Id: I4338fab02f89d3b09ee3d36376b86ee135374a1b\n" }, { "commit": "b4920b0f490206ba7cb4b584f04c6cf48ddfa3ad", "tree": "77be339bf45f1a772cc91c9c6478d881540d2197", "parents": [ "506654c0f5193f55acee2262b8b9da2e52251429" ], "author": { "name": "Stefan Hall", "email": "stefanhall@google.com", "time": "Wed Sep 24 15:47:52 2025 -0700" }, "committer": { "name": "Stefan Hall", "email": "stefanhall@google.com", "time": "Fri Oct 03 14:28:33 2025 -0700" }, "message": "Add GF22 Compiled Memories to Design\n\nAdd GF22 compiled memories. Make Sram .v files more generic to\naccomodate different technologies.\n\nChange-Id: Ibf994fc361247494d62e88f0c331fb13e69f846e\n" }, { "commit": "506654c0f5193f55acee2262b8b9da2e52251429", "tree": "b4ce9ff469af7f51d381c04ac6c75a97150f3885", "parents": [ "ca75d613f9f2bfe0d0e002c50a2be471cd0b07da" ], "author": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Thu Oct 02 11:56:52 2025 -0700" }, "committer": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Fri Oct 03 14:14:12 2025 -0700" }, "message": "Buildify cocotb, verilator-sim and chisel/common\n\nChange-Id: If145679b87c8f6748d87920da250c7d884de0820\n" }, { "commit": "ca75d613f9f2bfe0d0e002c50a2be471cd0b07da", "tree": "dc2287f4afaa7e180704bd83488d6d050376e330", "parents": [ "6957184c893946874ae61713df1ec2020156f817" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Oct 03 11:33:00 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Oct 03 11:44:46 2025 -0700" }, "message": "Add whole register into Lsu.\n\nChange-Id: Iee07259b7c63aca7748a231ccc89a6f77bbfb4a3\n" }, { "commit": "6957184c893946874ae61713df1ec2020156f817", "tree": "f655f22e6c639edb757173bf53c77014b932a92c", "parents": [ "6d60671f9f087dc622d55692d342eb2b9abe635c" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Oct 03 08:44:28 2025 +0000" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Oct 03 10:29:50 2025 -0700" }, "message": "Fix rvv load/store non-indexed decoding\n\nShould only look at the ew in the instruction.\nDon\u0027t look at the one in vtype.\n\nAffected tests are now enabled.\n\nChange-Id: I5c3aa1181e9c0c5bc44542e2d892e4cb4548a35e\n" }, { "commit": "6d60671f9f087dc622d55692d342eb2b9abe635c", "tree": "c00010a319c9e821bacd586799423e35de9d38cb", "parents": [ "7c440a9049c61a21c57892e37678316a85b1b5cd" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Oct 02 21:32:53 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Oct 03 01:20:22 2025 -0700" }, "message": "Add tests for strided/strided-segmented loads/stores.\n\nCheck combinations of SEW and EEW.\n\nChange-Id: I733ca6b95c3abd8b1200ba9f003eb59b333aa353\n" }, { "commit": "7c440a9049c61a21c57892e37678316a85b1b5cd", "tree": "3a729aebfebe9a482b94929fbbd783fcc8598a62", "parents": [ "e494a11bb9734c51d8e11d6b3a61720eaf856b70" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Oct 02 18:02:40 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Oct 03 01:20:22 2025 -0700" }, "message": "Add tests for unit/unit-segmented loads/stores.\n\nCheck combinations of SEW and EEW.\n\nChange-Id: I7de787fb11ce4d554c338e069ed8c0f068bb0612\n" }, { "commit": "e494a11bb9734c51d8e11d6b3a61720eaf856b70", "tree": "ab951defeab4388f50604aaf165bea2fa06039d0", "parents": [ "46c5a0e513f22e1789a92548af6db5fa983edce0" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Oct 01 15:27:29 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Oct 03 00:40:20 2025 -0700" }, "message": "Saturate vl in RvvFrontEnd.sv\n\nChange-Id: Ia5215d18eec10b52aaf83c6a48985971e0e5602f\n" }, { "commit": "46c5a0e513f22e1789a92548af6db5fa983edce0", "tree": "9dcca84d9bdc2245998760b4fe7dfe84e9c26a94", "parents": [ "ad3a1d1afaa7015022984968adbb7fe51f95640d" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Oct 01 21:59:01 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Oct 03 05:00:50 2025 +0000" }, "message": "Fix for loads \u003e 8 steps\n\nIn the backend:\n- Allow up to 32 uops\n- Decode affected instructions\n- Set vd offset for them\n- Set vs2 offset for them\n- Set segment_index for them\n\nAll existing load-store tests now pass\n\nChange-Id: I2c77efd78d71dc418032b3d16f8c9297505dce37\n" }, { "commit": "ad3a1d1afaa7015022984968adbb7fe51f95640d", "tree": "5c6e2e9a5655fb48d5948e71f91cd20465d34ee0", "parents": [ "51e5726e057dd4086a19577c28e745a1f351da66" ], "author": { "name": "Naveen Dodda", "email": "ndodda@google.com", "time": "Thu Oct 02 01:31:07 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Thu Oct 02 22:34:19 2025 +0000" }, "message": "Segmented load test for load16_index32\n\n* This test currently included a work around for compiler bug\n* To test bazel run //tests/cocotb:rvv_load_store_test_load16_index32_seg\n\nChange-Id: Ie5fb2b0bc63c396c18be6d77f44aeb5a32497442\n" }, { "commit": "51e5726e057dd4086a19577c28e745a1f351da66", "tree": "24b9afd5ad1ccac7590bd3ebdcc9169dee83fea3", "parents": [ "8a10a6ed8e9621d11cb221c3fce66586fb8ae3e2" ], "author": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Thu Oct 02 11:41:58 2025 -0700" }, "committer": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Thu Oct 02 11:41:58 2025 -0700" }, "message": "Increase size of kelvin_scalar_tests to prevent timeouts\n\nChange-Id: I250a34a0dee6f4dd1e0e80df8ab02b45d409fd07\n" }, { "commit": "8a10a6ed8e9621d11cb221c3fce66586fb8ae3e2", "tree": "124185d030f40678ca1e4fee82e763311087fa33", "parents": [ "1ca123c7e4a99154882f0e389c2e661b91fe4369" ], "author": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Thu Oct 02 11:41:42 2025 -0700" }, "committer": { "name": "Matthew Wilson", "email": "mwilson@google.com", "time": "Thu Oct 02 11:41:42 2025 -0700" }, "message": "Run buildifier on hdl/chisel/src/kelvin/BUILD\n\nChange-Id: I2020786f26f87bcb90f17525742fd3a4cac80fc1\n" }, { "commit": "1ca123c7e4a99154882f0e389c2e661b91fe4369", "tree": "7a1932a6c2ddc46cf347e18474281e32266cf511", "parents": [ "a6c5d7fad5ef95bfbaeee72d69d2eed6c7297fed" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Oct 01 10:58:44 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Oct 01 14:13:22 2025 -0700" }, "message": "Address STARC05-1.3.1.3 lint issues.\n\nSeparate resettable and non-resettable registers into different\nalways_ff blocks.\n\nChange-Id: I5f1835b0274809d5a96a1f9931b945d13e18934b\n" }, { "commit": "a6c5d7fad5ef95bfbaeee72d69d2eed6c7297fed", "tree": "0da9daaa06195e86c53071a053af1a04fb362d6e", "parents": [ "5dd68faf6bb6adfb28eaf5e506a8b9acb17c4464" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 29 07:59:25 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 30 21:00:12 2025 +0000" }, "message": "Test segmented store8 index8\n\nSegment support is added to the control path, non-segmented cases are\nnow handled as 1-segment.\n\nAdding additional logic to avoid overlapping scatters - they make the\ntests flaky.\n\nChange-Id: Ie78eb663d7c3772902c47000eb70d8380868be52\n" }, { "commit": "5dd68faf6bb6adfb28eaf5e506a8b9acb17c4464", "tree": "20fd7b3a2c6b11caf9b3904ef993476ca7df8905", "parents": [ "c38bef0d55a4daea3127e8f0b7e482779ac035be" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Sep 26 22:32:03 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 30 21:00:12 2025 +0000" }, "message": "Test load8 index32 segmented\n\nChange-Id: I7cef664f5a18939b12fee2d42bf6d3f36acce522\n" }, { "commit": "c38bef0d55a4daea3127e8f0b7e482779ac035be", "tree": "d30ef4ad669743eb789c2c721c0aa8991bdb464f", "parents": [ "a715d40895ae0a603d739929ee5133384ef4abc6" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 29 19:02:56 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 30 21:00:12 2025 +0000" }, "message": "Simplify indexed load testing\n\nNon-segmented cases are now handled as if they\u0027re 1-segmented.\n\nMinor improvement to expected output computation.\n\nChange-Id: Ide24ee6e4e33bcb04966266b9d8c43cf2638723c\n" }, { "commit": "a715d40895ae0a603d739929ee5133384ef4abc6", "tree": "e0245dd019550fb6fcd414eb5d8a2c77b57e4e28", "parents": [ "6fc717d575a275fb307e6201e60e4a14996a5af7" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Sep 26 21:49:45 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 30 21:00:12 2025 +0000" }, "message": "Test load16 index8 segmented\n\nTimeout of the load-store test suite is extended to \"eternal\" as it now\nhas a lot more cases and timeout frequently, blocking submission.\n\nChange-Id: I6df5a482ccbaf9e6613b02970722d84f248719f5\n" }, { "commit": "6fc717d575a275fb307e6201e60e4a14996a5af7", "tree": "18ea2d443cfb01e52deb0192f7f04ea2716c3119", "parents": [ "2ba772e2aca294a87533d5397261009af2e9b92b" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 29 08:33:46 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 30 21:00:12 2025 +0000" }, "message": "Simplify compiler bug workaround\n\nTo prevent the compiler from combining the vset instructions,\nwe could simply clobber the vtype. This workaround has been\ntested with gcc and clang.\n\nChange-Id: Id1b62efe5941f2508d6d99a2020329013f0dd0b4\n" }, { "commit": "2ba772e2aca294a87533d5397261009af2e9b92b", "tree": "532319019fff3a669401da2ee3549406ad6b1db5", "parents": [ "a0ccb5832ca40ef7e8e219adfc2e1c2e97adfddc" ], "author": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Tue Sep 16 14:13:50 2025 -0600" }, "committer": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Mon Sep 29 15:47:09 2025 -0600" }, "message": "[dv, cosim] Refactor co-sim DPI to use an unified \u0027mpact_get_register\u0027 API\n\nBug: 443772447\n\nChange-Id: I6813f5beb7a2dba968c717a0d7d5567c7a10fd76\n" }, { "commit": "a0ccb5832ca40ef7e8e219adfc2e1c2e97adfddc", "tree": "c9d8308d3b17d2f5e241d330311c7dab91818ec8", "parents": [ "42fc54909dfa3bf8a74f3b981303fedf9c021218" ], "author": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Tue Sep 23 18:41:55 2025 -0600" }, "committer": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Mon Sep 29 15:24:12 2025 -0600" }, "message": "[dv, cosim] Enable ELF loading in MPACT co-simulation model\n\nBug: 439909603\n\nChange-Id: I695fc2232424e66344f72b5468e73228ec194272\n" }, { "commit": "42fc54909dfa3bf8a74f3b981303fedf9c021218", "tree": "8cd27751d8f231ed444cd0c879a0765d92b5755e", "parents": [ "2b170925dbaedb1283a73949eeba800912ae81ba" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Sep 26 20:41:21 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Sep 26 21:50:15 2025 +0000" }, "message": "Mark vl and vtype as clobbered in inline asm\n\nA few missed ones affected by compiler bug is fixed too.\n\nChange-Id: I1101aea7261f54a1a1fc1749c4a639441fcabdc6\n" }, { "commit": "2b170925dbaedb1283a73949eeba800912ae81ba", "tree": "e63c5e34697b9078636a49aa27a544db6c7092e7", "parents": [ "791179d9417e3577a07b750240e1307f8d4574ee" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Sep 25 15:24:08 2025 -0400" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Sep 26 15:46:50 2025 -0400" }, "message": "Add tests for unit masked loads/stores.\n\nChange-Id: I6d89d53f24e67073a40567c5852bc0ea97192e63\n" }, { "commit": "791179d9417e3577a07b750240e1307f8d4574ee", "tree": "c88c9393d8386da7af2bf41b24f824026893e27d", "parents": [ "783e3e35ecf962f209f43e4da56b95cab7afe7c9" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Sep 26 12:40:55 2025 -0400" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Sep 26 13:04:02 2025 -0400" }, "message": "Update RVVI url to point to commit instead of branch.\n\nThe RVVI repository pushed a change to their branch. Pin to\nspecific commit.\n\nChange-Id: I9c1a4c4cce5dbbc4777bff0c1b8f7d23932a791d\n" }, { "commit": "783e3e35ecf962f209f43e4da56b95cab7afe7c9", "tree": "e579b0ff6c743547eb9d0c91e8b7c5e8b763bb91", "parents": [ "1a79d065f341b7a8d169b5bab069df65b1725946" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Sep 24 22:10:45 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Thu Sep 25 16:56:01 2025 +0000" }, "message": "Fix element length for segmented indexed loads\n\nload8 index16 tests are added.\n\nCurrently the core hangs at vluxseg2ei16_v_u8m4x2 (index is u16m8)\n\nChange-Id: I62a604a7b5880731cd3f1617867b2e9dcf123ed4\n" }, { "commit": "1a79d065f341b7a8d169b5bab069df65b1725946", "tree": "5f4a77104d14ad9b44a1fdbf95590cba03351e94", "parents": [ "3b119f89ef66c70d025dd4bf34e869546fdb3130" ], "author": { "name": "Naveen Dodda", "email": "ndodda@google.com", "time": "Tue Aug 19 20:11:04 2025 +0000" }, "committer": { "name": "Naveen Dodda", "email": "ndodda@google.com", "time": "Wed Sep 24 22:42:01 2025 -0700" }, "message": "TFMicro integration into KelvinV2 ecosystem.\n\nSuccessful integration necessitated modifications across the repository.\n\nRevisions to the build system encompass:\n * Workspace has been reconfigured to facilitate the download of the tflite_micro repository and its associated dependencies.\n * rules/repos.bzl file now incorporates new repositories for download.\n * rules/utils.bzl file has been updated to include the generate_cc_arrays tool.\n\nThe tflite_micro patch incorporates:\n * Patches designed to disable -pthreads within ruy and gemmlowp.\n * Adjustments to the visibility of the generate_cc_array and hello_world models.\n\nRegarding the toolchain, the following changes have been implemented:\n* Removal of freestanding attributes.\n* Addition of no-exceptions and no-rtti flags.\n* Introduction of a new tcm.ld file to facilitate high-memory kelvin_binaries.\n\nValidation was conducted using tests/cocotb/tutorial/tflite_micro_test.cc.\nToolchain Validation bazel test tests/cocotb/...\n\nChange-Id: I3cc05b9ad6a23d4c20c1b9c074b1b8a6b18dae5d\n" }, { "commit": "3b119f89ef66c70d025dd4bf34e869546fdb3130", "tree": "c8257dfa83994e8ea318ddaf7d69b60c1e41aa58", "parents": [ "03fa31aa589fa4bf8616ffcae54b41d301b57e73" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 23 23:27:08 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Sep 24 18:25:15 2025 +0000" }, "message": "Extend segmented indexed load test coverage\n\nFinish load8index8, add load16index16 and load32index32.\n\nChange-Id: I948cbee6c3b65a14eee46162563f98a4dc01496b\n" }, { "commit": "03fa31aa589fa4bf8616ffcae54b41d301b57e73", "tree": "df561a0612f6321710e4620dc02010c335e5d465", "parents": [ "bfe7c24a17f2aac8731f303e664392ab37a7d32f" ], "author": { "name": "Stefan Hall", "email": "stefanhall@google.com", "time": "Mon Sep 22 18:10:53 2025 -0700" }, "committer": { "name": "Stefan Hall", "email": "stefanhall@google.com", "time": "Tue Sep 23 16:09:56 2025 -0700" }, "message": "Set Clock Frequency for cocotb Sims to 800MHz\n\nSet clock period default to 1.25ns for a frequency of 800MHz. This is\nour target frequency.\n\nChange-Id: I58cee127325b89bed4768496900a1bf8dfa2cc16\n" }, { "commit": "bfe7c24a17f2aac8731f303e664392ab37a7d32f", "tree": "e8bd21d0f02def51837d936d20eacc387c996cc8", "parents": [ "e0cdcd6cf536202a472478535b613490176b98c8" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 23 18:49:29 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 23 16:00:00 2025 -0700" }, "message": "Fix segmented indexed loads\n\nCurrently tested on data8 index8.\n\nAdding the first set of tests. Will extend coverage.\n\nChange-Id: I2283b4120f35778e2d7e7134932a3dcd211b1294\n" }, { "commit": "e0cdcd6cf536202a472478535b613490176b98c8", "tree": "69aa8c60d016666484ef555b11b7db383d9a3c44", "parents": [ "651c5851a0767fd49db510b472a5ac7af4e51ff6" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Sep 23 11:45:34 2025 -0400" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Sep 23 14:05:10 2025 -0400" }, "message": "Improve coverage for indexed stores ddtype \u003e idtype.\n\nChange-Id: I678b1239826d2b0aa1f0ee0476ed1e825dd0df90\n" }, { "commit": "651c5851a0767fd49db510b472a5ac7af4e51ff6", "tree": "ddf2bf0090f770ca73fcd0b7c83cec4bc4e747df", "parents": [ "157947823888dffe21b7855277c47e819b3f74f2" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 22 22:41:17 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 22 21:58:16 2025 -0700" }, "message": "Fix index\u003edata indexed load \u003em1\n\nAdd a new counter alongside lmul to determine which section of\nindex vectors to use.\n\nBad test cases are fixed.\n\nChange-Id: I07fa4cfa6d60f2a2fe745912f6e0e1f889522441\n" }, { "commit": "157947823888dffe21b7855277c47e819b3f74f2", "tree": "f5d7ab65cb78956b4f2921d190a5fd0d71e7ae17", "parents": [ "9596c40de6d697a0e4cc3937dd4d12c79737ce65" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 22 09:24:58 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 22 21:58:16 2025 -0700" }, "message": "LSU state machine for vector loops\n\nAdd a counter class to implement loops, and move all the looping logic\ninto a centralized state machine.\n\nThe lmul counter now counts up, main LSU logic is not changed.\n\nChange-Id: I7ebfc9ac66d8b7a41bcaabefa150ac961322815f\n" }, { "commit": "9596c40de6d697a0e4cc3937dd4d12c79737ce65", "tree": "bed6d1590aed1dee853d48b6a53281cd88c4213f", "parents": [ "a326cd54c862786d9bebb90f793eb9844745fe0a" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Mon Sep 22 15:12:52 2025 -0400" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Mon Sep 22 15:39:08 2025 -0400" }, "message": "Set vill based on sew and lmul.\n\nChange-Id: I7a4bec14380c910ca147bc372f942648da9d47c9\n" }, { "commit": "a326cd54c862786d9bebb90f793eb9844745fe0a", "tree": "f5f45bccf42a05c406d8a8b41d922c12001f032d", "parents": [ "e7c87ff77408722f7581db6d59a1558d218d4a1e" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Sat Sep 20 06:26:34 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Sun Sep 21 21:42:20 2025 -0700" }, "message": "Expand tests for indexed store of same ddtype and idtype.\n\nChange-Id: I4d00fd837c8b18308d7bac0bd273403c76c3c213\n" }, { "commit": "e7c87ff77408722f7581db6d59a1558d218d4a1e", "tree": "6963d6dd0538ea661b78759757588fe625762b76", "parents": [ "6e984db30268501ef4a76213e0ec2ab62b8add00" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Sun Sep 21 04:26:31 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Sun Sep 21 08:52:37 2025 +0000" }, "message": "Apply inline asm only to vle in indexed load tests\n\nWhen data width is different from index width, lmul is also different.\nIf written in intrinsics, we hit a compiler bug in llvm and gcc that\nincorrectly combines the vset, causing the vle to see bad lmul.\n\nA previous workaround rewrites the tests in inline asm.\n\nThis new workaround rewrites only the vle part in inline asm, passing\nthe results out as intrinsics-compatible vector data types, allowing\nthe indexed loads to happen in intrinsics. This reduces the number of\nconstraints we need on the asm blocks and reduces the chance of\nbugs.\n\nA bug within indexed load tests\u0027 expected output generation is fixed.\n\nChange-Id: I7bf1e8a7e9208753e6428a19c178f6f0e40e43e6\n" }, { "commit": "6e984db30268501ef4a76213e0ec2ab62b8add00", "tree": "80844c975393177655de548866da7faccf5161f5", "parents": [ "cd84f01317f602f27355c77ecbc3b557e484b15a" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Sep 18 16:11:42 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Sep 19 21:40:23 2025 -0700" }, "message": "Improve support for mixed dtype indexed loads/stores.\n\nBetter support data dtype \u003c index dtype cases.\n\nChange-Id: I607af046bfed91d321d68bf50813a165e96676c9\n" }, { "commit": "cd84f01317f602f27355c77ecbc3b557e484b15a", "tree": "e458cc5afff58aaae2ad0bf377abaf4a34724ff5", "parents": [ "f906d354f860f5e044a78598292a61a3e2fcf440" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Sep 19 18:39:59 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Sep 19 21:02:19 2025 +0000" }, "message": "Add load16/32_index8 tests\n\nChange-Id: Iaf0ce97e1c4f580d9541aa7c976b8f3e566a21f9\n" }, { "commit": "f906d354f860f5e044a78598292a61a3e2fcf440", "tree": "168e5eaf3f75e68592a4dca22c16be40d95e84ea", "parents": [ "38e3297f3f8b6037980a9e2a9962cfa846e9463a" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Thu Sep 18 18:23:26 2025 +0000" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Sep 19 11:05:05 2025 -0700" }, "message": "Fix wrong results for mixed prec indexed loads\n\nAdding a bunch of indexed load tests too.\n\nThe fix is tested on data8 index16 loads below m1 and index32 below mf2.\nPending another fix for larger lmul.\n\nTODO: test store\nTODO: test load data16/32\n\nChange-Id: I83b986339ff0900449fa4b57fa2eb895ca4e26f8\n" }, { "commit": "38e3297f3f8b6037980a9e2a9962cfa846e9463a", "tree": "5151c14755fef516b5906670040d1c0f927d4387", "parents": [ "c2c02f7ed3decad9fbb33e24fb2c59cc926e4a8d" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Fri Sep 12 16:23:09 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Sep 18 18:14:03 2025 -0700" }, "message": "[rvvi] Handle vd conflicts for vector tracing\n\n- Multiple vector instructions can be dispatched concurrently with the\n same destination register. Update our retirement logic to only consume\n one write to a given register, per cycle.\n\nChange-Id: I1acf2ac2db19d3d048f295ac754d9ffc23cbd075\n" }, { "commit": "c2c02f7ed3decad9fbb33e24fb2c59cc926e4a8d", "tree": "73c6c55bb112cda6346c4f4e92b83053f52625b0", "parents": [ "4aa97a944ac2c5c399d2f05a77fcfd0a27352c0e" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Thu Sep 18 17:14:21 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Thu Sep 18 13:03:43 2025 -0700" }, "message": "Add vsseg*e16/32 tests\n\nChange-Id: I7d38628c389743c1d0bf335e3cfdc7518ddeb20d\n" }, { "commit": "4aa97a944ac2c5c399d2f05a77fcfd0a27352c0e", "tree": "7db367673cfd79e7b172598b79bb635a6d8744a4", "parents": [ "5fad6ba07730f96e34f323f734dcf656fff199df" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 02 16:27:33 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Sep 18 10:30:34 2025 -0700" }, "message": "feat(dv): Add Python-based SPI loader for Verilator\n\nThis commit introduces a Python-based toolchain for loading and running software on the Verilator simulation of the Kelvin SoC. This toolchain interacts with the `spi_dpi_master` via its TCP socket interface.\n\nThe new toolchain in `utils/kelvin_soc_loader/` includes:\n- **`spi_driver.py`**: A Python client library that connects to the DPI server and provides a high-level API for SPI operations (read/write/poll registers, bulk data transfer).\n- **`loader.py`**: An application that uses the `spi_driver` to parse an ELF file, load its segments into the SoC\u0027s memory through the simulated SPI bridge, and then start the core\u0027s execution.\n- **`run_simulation.py`**: An orchestration script that manages the entire simulation and loading flow. It starts the Verilator binary, waits for the DPI server to initialize, executes the loader script, and manages the simulation runtime.\n\nThis provides a complete, scriptable workflow for running software tests on the hardware design in a simulation environment, greatly improving the development and verification loop.\n\nChange-Id: I950efdff040c49502cc74e4b7ad71ed5e3c9124c\n" }, { "commit": "5fad6ba07730f96e34f323f734dcf656fff199df", "tree": "19304191fab669b98b7e06b837461d3aaf515432", "parents": [ "5a16231216eeb507e8863578a299b9de672a6218" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 02 16:25:19 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Sep 18 10:30:34 2025 -0700" }, "message": "feat(fpga): Integrate Chisel Subsystem into FPGA build\n\nThis commit integrates the newly created `KelvinChiselSubsystem` into the top-level FPGA design for both Verilator simulation and the Nexus hardware target.\n\nKey changes:\n- **`kelvin_soc.sv`**: The top-level SoC module is updated to instantiate the `KelvinChiselSubsystem` instead of the individual Chisel-generated modules (core, crossbar). This greatly simplifies the top-level Verilog.\n- **FPGA Build System**: The `fpga/BUILD` file is updated to build and use the `KelvinChiselSubsystem`. The dependencies on the old, individual modules (`rvv_core_mini_tlul`, `xbar_kelvin_soc_chisel`, `rv_core_ibex`) have been removed.\n- **Verilator Simulation**: The `chip_verilator.sv` wrapper now includes the `spi_dpi_master`, allowing host-driven SPI communication with the simulated SoC.\n- **Ibex Boot ROM Removal**: The Ibex core and its associated software boot ROM have been removed from the FPGA build.\n- **Clocking**: The clock generator has been simplified to remove the dedicated clock for the now-removed standalone Ibex core.\n\nThis commit completes the transition to the unified Chisel subsystem architecture at the FPGA level.\n\nChange-Id: I8de2a29e3f59ec834647f644c13bd9f6b9b4bb6c\n" }, { "commit": "5a16231216eeb507e8863578a299b9de672a6218", "tree": "ae80734f8bb9cb8ecf44501ea4a7cca0ed86cdfa", "parents": [ "bd14438f39e4979800bf8f043c50bd78c2084f4c" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 02 16:23:24 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Sep 18 10:30:34 2025 -0700" }, "message": "feat(fpga): Add SPI DPI Master for Verilator simulation\n\nThis commit introduces a SPI DPI master module to enable host-driven testing of the SoC in Verilator simulations. This provides a way to interact with the simulated design over SPI, mimicking how a host computer would interact with the physical FPGA.\n\nThe implementation consists of:\n- **`spi_dpi_master.sv`**: A SystemVerilog module that uses the SystemVerilog DPI to call into a C++ backend.\n- **`spi_dpi_master.cc`**: A C++ backend that implements the DPI functions. It starts a TCP server that listens for high-level commands (e.g., WRITE_REG, BULK_READ). It then translates these commands into the correct sequence of SPI signal toggles, which are driven back into the simulation.\n\nThis DPI module allows Python test scripts to connect to the simulation via a TCP socket and drive SPI transactions, enabling more realistic and hardware-in-the-loop style testing.\n\nChange-Id: I030bdbbb5598c75a9b11f82895de60a8c77d588f\n" }, { "commit": "bd14438f39e4979800bf8f043c50bd78c2084f4c", "tree": "fe87d8b037c729dad530c39d701b59734bd43ca6", "parents": [ "813d03e1c896c4c6c44a9eda9e25e7686d0b4e85" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 02 16:21:16 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Sep 18 10:30:34 2025 -0700" }, "message": "refactor(soc): Introduce unified KelvinChiselSubsystem\n\nThis commit introduces a major architectural refactoring by creating a unified `KelvinChiselSubsystem`. This new top-level module programmatically instantiates and connects all Chisel-based components of the SoC, including the RV core, crossbar, and peripherals like the Spi2TLUL bridge.\n\nKey changes:\n- **`SoCChiselConfig.scala`**: A new central configuration file that defines the modules to be instantiated, their parameters, and their connections. This allows for a more flexible and maintainable SoC architecture.\n- **`KelvinChiselSubsystem.scala`**: The new top-level module that reads the configuration and builds the hardware graph, connecting modules to the crossbar and exposing external ports.\n- **`CrossbarConfig.scala`**: Updated to be more dynamic. It now sources its configuration from `SoCChiselConfig` and supports a test harness mode. The Ibex core hosts have been removed and replaced by the `spi2tlul` host and a generic 32-bit test host.\n- **Tests**:\n - The existing crossbar tests (`kelvin_xbar_test.py`) have been updated to use the new test harness and reflect the new port mapping.\n - A new subsystem-level test suite (`test_subsystem.py`) has been added to verify the integrated subsystem. These tests demonstrate loading and executing an ELF file on the core via both a TL-UL test host and the SPI bridge.\n\nThis refactoring simplifies the top-level Verilog (`kelvin_soc.sv`) and provides a more scalable and configurable way to build the SoC.\n\nChange-Id: Ib8249023d3df3da32a62b00006e103b5f8236f4f\n" }, { "commit": "813d03e1c896c4c6c44a9eda9e25e7686d0b4e85", "tree": "114e4c42a1fe8dbdfc879d3c3ae917052527877c", "parents": [ "7759a66faa0121563684b83fabb179db5f0ca410" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Sep 17 16:16:46 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Sep 18 10:30:34 2025 -0700" }, "message": "feat(spi): Increase Spi2TLUL bulk transfer size to 16-bit\n\nThis change increases the maximum bulk transfer size of the Spi2TLUL module from 256 bytes to 65536 bytes by widening the length registers from 8 to 16 bits.\n\nThe key changes include:\n- Updated the Spi2TLUL Chisel module to use 16-bit length registers for both bulk and regular TileLink transfers.\n- Modified the SPI command state machine to handle two-byte length transactions.\n- Re-implemented the internal data buffers using SyncReadMem to support larger, configurable depths, and increased the buffer size to 4KB.\n- Introduced pipelining for SRAM reads to improve performance with larger data transfers.\n- Updated the Python SPI master utility and cocotb tests to support 16-bit register accesses and larger data transfers.\n- Added new cocotb tests to verify large (up to 4KB) packed writes and pipelined reads.\n\nChange-Id: I4420f969584976c4fb16b25513c1791e54aced4c\n" }, { "commit": "7759a66faa0121563684b83fabb179db5f0ca410", "tree": "2d83b156bdab41a6e94e5216c930d09809e42c01", "parents": [ "6178d5da9da877f4565553b9e3b5985e30fde842" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Sep 17 21:29:17 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Sep 17 22:46:36 2025 +0000" }, "message": "Consolidate load8/16/32 segmented test cases\n\nAnd add more coverage on the vlseg*.\nMinor fixes to other existing tests to make the binaries runnable\nwithout the test runtime.\n\nChange-Id: I5e6a6e9d439291ec44ef00610072e37b1a152613\n" }, { "commit": "6178d5da9da877f4565553b9e3b5985e30fde842", "tree": "260dfd0403f2911d72d5ba4a29f0669b4ff51b30", "parents": [ "acf084c3cbd073e0dc15b891029cdfa2fb761f35" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 16 23:10:57 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Sep 17 13:34:38 2025 -0700" }, "message": "Fix segmented load-store register layout\n\nOrder of operations from memory PoV is unchanged.\nOrder of register access is changed.\n\nThe fix is now complete, affected tests are enabled.\n\nChange-Id: Ib7bf17b0d60c18a8b0b4cb8163277cd0afe8e37c\n" }, { "commit": "acf084c3cbd073e0dc15b891029cdfa2fb761f35", "tree": "fcb767e6befe9c755a57e2494033941018e2a5b1", "parents": [ "19eeec6dc2f1f82d98fcfc1612bdd9b99babaa93" ], "author": { "name": "tianyu.li", "email": "tianyu.li@verisilicon.com", "time": "Tue Sep 16 17:34:44 2025 -0700" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Sep 17 13:34:38 2025 -0700" }, "message": "Adjust vector register order in Decoder for segment load/store. Update rvv_backend_tb for lsu changes.\n\nChange-Id: I60d55196d033b70f5e64baddf17ae2d40e96c574\n" }, { "commit": "19eeec6dc2f1f82d98fcfc1612bdd9b99babaa93", "tree": "50e7fd0d62cc0a6193ecd82b6e7913145e09e859", "parents": [ "5ae968951d90f9dbb654509853c3e8b8afd635b3" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 15 22:33:20 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Sep 17 13:34:38 2025 -0700" }, "message": "Add segmented store8 tests\n\nseg 2 to seg 8.\nm2 and m4 currently fail.\n\nChange-Id: I8ab3dee832de91651b949bb8763b47066a20fe8a\n" }, { "commit": "5ae968951d90f9dbb654509853c3e8b8afd635b3", "tree": "201ef10af6c593a1ba2e85204c58d5dfa87ea3f8", "parents": [ "d28bde072267460cc8680bb736b8e625d87eeb7e" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Sep 17 17:33:03 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Wed Sep 17 13:34:38 2025 -0700" }, "message": "Fix load segment2 m2 test cases\n\n- set vl correctly\n- fix expected output pattern\n\nBecause the impl is currently incorrect, the changed test cases now\nfail, and are temporarily marked as skipped before we have the fixes.\n\nChange-Id: Ibee12af3d6ae1eca16f59edfa2cc9aa9a1d4a13b\n" }, { "commit": "d28bde072267460cc8680bb736b8e625d87eeb7e", "tree": "a04dde39f4715a2b29da4761b65a46f9c9adb1b1", "parents": [ "707495c9dda43cebc685606ea32c95eb99503b67" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 09 10:15:17 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 16 17:52:23 2025 -0700" }, "message": "feat(spi2tlul): Implement efficient bulk data transfers\n\nImplements a high-throughput bulk data transfer mechanism for the\nSpi2TLUL bridge. The previous implementation relied on single-byte\nread/write operations to the data buffer port, which was inefficient\nfor large data transfers due to the overhead of sending an address\nfor every byte.\n\nThis change introduces dedicated bulk read and write ports. A single\nSPI command can now initiate a transfer of up to 256 bytes,\nsignificantly improving data throughput for tasks like loading programs\nor model weights.\n\nKey changes include:\n- A new command-decoding FSM in the Spi2TLUL Chisel module to\n distinguish between single-register access and bulk transfers.\n- A robust, double-buffered MISO path to prevent data loss during\n back-to-back SPI transactions.\n- New `new_bulk_write` and `new_bulk_read` methods in the Python\n `SPIMaster` test utility.\n- Enumerations for SPI register addresses and commands in the Python\n test utilities for improved readability and maintainability.\n- Comprehensive cocotb tests verifying the new bulk transfer modes,\n including a stress test for transfers up to 64KB.\n\nChange-Id: I72c614fadb5620c86a4150bedffef14857f47217\n" }, { "commit": "707495c9dda43cebc685606ea32c95eb99503b67", "tree": "bc074ceaa10db430a442306d280c7744ea68981e", "parents": [ "725eb3bc706816b705d64d6fed12e37a409ccbc1" ], "author": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Mon Sep 08 15:31:10 2025 -0600" }, "committer": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Tue Sep 16 11:59:28 2025 -0600" }, "message": "[dv, flow] Add ELF loader feature\n\nAdds a Python script (`utils/elf_to_mem.py`) to parse the test ELF,\ngenerate separate ITCM/DTCM memory files, and extract the \u0027tohost\u0027\nsymbol address.\n\nChange-Id: I1fcd97e523206604b1fcb7e6007073263eb9ee14\n" }, { "commit": "725eb3bc706816b705d64d6fed12e37a409ccbc1", "tree": "760d3fcd7a924be483aa2686eaef51486d746925", "parents": [ "10dea542b0fd8f13573dede33744c568da473f4d" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 15 17:51:45 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Mon Sep 15 19:40:08 2025 +0000" }, "message": "Add VLM/VSM tests\n\nThis set of tests cover the allowed usage reachable from intrinsics.\n\nThese only pass after change 74304.\n\nChange-Id: I6fbd9ad14e86aeb4827dd4dc57323602b22a815a\n" }, { "commit": "10dea542b0fd8f13573dede33744c568da473f4d", "tree": "da3aa6bb8f9b10f8ad66f19da30b2d2e640b6b35", "parents": [ "56decb04fac9fd450141b2e096facd09b6ada06d" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Sep 12 15:21:20 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Mon Sep 15 12:28:22 2025 -0700" }, "message": "Handle masked loads and stores.\n\nChange-Id: I107037ba52bf39cca0e2883bc46401422deb04ae\n" }, { "commit": "56decb04fac9fd450141b2e096facd09b6ada06d", "tree": "be9e0e3734892ba905ebdcce5af93b3f8b25a754", "parents": [ "c775ee31c0ef80ea79e04f3cfadb91e999dd1157" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Sep 12 22:52:14 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Fri Sep 12 18:42:17 2025 -0700" }, "message": "Switch from VLM to VLE in VCPOP tests\n\nAtm our VLM is broken. Use VLE with reinterpret for VCPOP tests.\nDedicated VLM/VSM tests will be added later.\n\nAdded fractional byte support so we can test VCPOP more thouroughly.\n\nChange-Id: I531270db1fe23d380903fb96c4c8772cecf850b6\n" }, { "commit": "c775ee31c0ef80ea79e04f3cfadb91e999dd1157", "tree": "82138643b00b6eff115666e6ba6d312ed46bccc1", "parents": [ "a1149e19fece342db7d8a28db19a277bc865c7e9" ], "author": { "name": "Naveen Dodda", "email": "ndodda@google.com", "time": "Wed Sep 10 20:41:59 2025 +0000" }, "committer": { "name": "Naveen Dodda", "email": "ndodda@google.com", "time": "Fri Sep 12 13:52:39 2025 -0700" }, "message": "Refactoring core parts of toolchain_kelvin_v2\n\nThe following changes were made to upgrade dependencies and\nrefactor the build process.\n\n* Upgrade RISC-V GNU Toolchian to git-branch `2025.08.29`\n* Upgrade LLVM project to version `20.1.0`\n* Simplify the build by removing the separate build step for `riscv-newlib`\n and update submodules.\n* Update toolchain url and sha256 in `WORKSPACE` file to support new toolchain\n* Update c++ toolchain configuration to include paths for GCC 15.1.0\n\nChange-Id: I52b5cc37d47c2d672bd6c2b0f2b280883b37ac42\n" }, { "commit": "a1149e19fece342db7d8a28db19a277bc865c7e9", "tree": "a23c56ad92d8caef06e9e5c1407c948ba9a63544", "parents": [ "6506d565bcefb75cf3a8e42b6c15c02c8d7e5702" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Tue Sep 09 19:52:05 2025 +0000" }, "committer": { "name": "David Gao", "email": "davidgao@google.com", "time": "Thu Sep 11 16:29:22 2025 -0700" }, "message": "Confirm no more rvv instructions write rd\n\nTests are added for vcpop.\n\nChange-Id: I0178482dd8a8c7623ae14a234dddcc5bbcdee0aa\n" }, { "commit": "6506d565bcefb75cf3a8e42b6c15c02c8d7e5702", "tree": "6c01caafdaa0497ca26b542ea32c2c39243d8652", "parents": [ "7fc2fcc60908cc8b83546db788df43489e7af83f" ], "author": { "name": "Stefan Hall", "email": "stefanhall@google.com", "time": "Thu Sep 04 11:55:29 2025 -0700" }, "committer": { "name": "Stefan Hall", "email": "stefanhall@google.com", "time": "Wed Sep 10 16:33:47 2025 -0700" }, "message": "Update ClockGate.sv to support GF22\n\nClockGate.sv updated to support GF22. Also refactored for readablility.\n\nChange-Id: Ie12f006a44abb6da2c2c189997ad8264a9063bb9\n" }, { "commit": "7fc2fcc60908cc8b83546db788df43489e7af83f", "tree": "27422937d376110b280bebaa9f7bb386486a3569", "parents": [ "2133ce96fda9c7f7ee33c053a38db4f370f0bf03" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Sep 09 11:04:05 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Sep 09 17:12:42 2025 -0700" }, "message": "Add vill bit to config state and trap on bad state.\n\nChange-Id: I09c100b46bcfd64dbf09922efe6ced794ad4fbe9\n" }, { "commit": "2133ce96fda9c7f7ee33c053a38db4f370f0bf03", "tree": "32f3b47e4a6876ee283138b171c78ce7f33d73c2", "parents": [ "d79c4a7b1535787d4b002fc8b8a2412b7744da39" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 09 10:15:17 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 09 12:26:11 2025 -0700" }, "message": "feat(spi): Add packed write transaction support\n\nThis change introduces a \"packed\" write transaction to the SPI master,\nallowing for a full TileLink write transaction to be sent in a single,\nuninterrupted SPI burst. This significantly improves performance for\nloading data to the device.\n\nThe following changes are included:\n\n- A `packed_write_transaction` method has been added to the `SPIMaster`\n in `kelvin_test_utils/spi_master.py`.\n- A new test case, `test_packed_write_transaction`, has been added to\n `tests/cocotb/tlul/test_spi_to_tlul.py` to validate the new\n functionality.\n- The `poll_reg_for_value` method in `SPIMaster` has been refactored to\n correctly handle the pipelined nature of SPI reads, which was\n discovered during the development of the packed write feature.\n\nChange-Id: I1703af4d083dc75781550a38c43ac726a40cfb43\n" }, { "commit": "d79c4a7b1535787d4b002fc8b8a2412b7744da39", "tree": "3ba55abcfe6ea374ad611049453834188c466e9a", "parents": [ "63cdfa9f188cd6fc52b917ef8ccbc41a253dfe42" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 09 10:51:22 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 09 11:15:52 2025 -0700" }, "message": "Minor BUILD fixups for vcs_sim\n\nChange-Id: I3e5a8dd692fd57db2420a9231b45a1db7334459a\n" }, { "commit": "63cdfa9f188cd6fc52b917ef8ccbc41a253dfe42", "tree": "6af2c8129522989f48e0fe7391d831c47305c415", "parents": [ "faeb564ab99091321e0cab97ffcccb8ebef6096b" ], "author": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Mon Sep 08 15:32:03 2025 -0600" }, "committer": { "name": "Yenkai Wang", "email": "ykwang@google.com", "time": "Mon Sep 08 15:42:51 2025 -0700" }, "message": "[dv] Implement tohost termination mechanism\n\n- Update Makefile and testbench to use `$readmemh` for memory loading\n and detect writes to the `tohost` address.\n- The base test is updated to use this new `tohost` event for test\n termination and pass/fail checking based on the written status code.\n\nChange-Id: Ieef12b5b360645b2e3dc2dfb9263f180042ecaae\n" }, { "commit": "faeb564ab99091321e0cab97ffcccb8ebef6096b", "tree": "f92b3c53f48120e2c09f81d1301741cbcc84c294", "parents": [ "88b0bbde9007e0e52a4dcd8dd8b2c1cf9ef45120" ], "author": { "name": "David Gao", "email": "davidgao@google.com", "time": "Thu Sep 04 19:15:57 2025 +0000" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Sep 05 11:20:23 2025 -0700" }, "message": "Add vstart check for additional instructions\n\nThese follow the reduction instructions. Related functions are renamed\nto reflect the change.\n\nChange-Id: Ibed09dd9cb1cbc09f33003e5f923fc5a98f0bbef\n" }, { "commit": "88b0bbde9007e0e52a4dcd8dd8b2c1cf9ef45120", "tree": "4778875a6c705ef38994fafc39280d011ef7cd25", "parents": [ "a9ce01c608f8afd9f8f205e2077257ccc3b5339c" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 02 15:54:02 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Fri Sep 05 10:52:09 2025 -0700" }, "message": "feat(soc): Add Spi2TLUL bridge and tests\n\nThis commit introduces a new Chisel module, `Spi2TLUL`, which functions as a bridge between a SPI slave interface and a TileLink UL master interface. This allows an external SPI master to initiate TileLink transactions within the SoC.\n\nThe bridge includes:\n- A register map accessible via SPI for configuring TileLink transactions (address, length, command).\n- A data buffer for staging data for both read and write operations.\n- Asynchronous queues to handle clock domain crossing between the SPI clock and the main SoC clock.\n- State machines to manage SPI commands and TileLink transactions for both reads and writes.\n\nTo support verification, this commit also adds:\n- A Python-based `SPIMaster` class for cocotb, providing an easy-to-use interface for driving the SPI slave.\n- A comprehensive cocotb test suite (`test_spi_to_tlul.py`) with tests for:\n - Register read/write access.\n - Single and multi-beat TileLink reads.\n - Single and multi-beat TileLink writes.\n\nThe necessary BUILD file modifications are included to integrate the new module and its tests into the Chisel and cocotb build systems.\n\nChange-Id: Ie1280db53e77cec7b3f734b5bd6d63c8d41b2ca9\n" }, { "commit": "a9ce01c608f8afd9f8f205e2077257ccc3b5339c", "tree": "d5692b3973667209f4c7be9ba5f274b6ac8e5a34", "parents": [ "8f96ae746704a417ca2f1313c3963cbd224902f1" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Sep 04 11:57:28 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Sep 04 15:38:35 2025 -0700" }, "message": "Add vtype CSR.\n\nChange-Id: I4ebbadcf0b76d3477f22e682da1b844375fbd4ce\n" }, { "commit": "8f96ae746704a417ca2f1313c3963cbd224902f1", "tree": "0d9010ad76d8fada8bb52b7928abc6fe00916b33", "parents": [ "7e3321729104ffea13f1d8d8b666d5e7ea2174e4" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Sep 03 14:18:13 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Sep 04 13:34:01 2025 -0700" }, "message": "Update rvv_idle signal to include frontend and fix mpause dispatch.\n\nChange-Id: I98c613ccf3609cbb4d8dccca7bd2c86a4d85c85f\n" }, { "commit": "7e3321729104ffea13f1d8d8b666d5e7ea2174e4", "tree": "29b8e42f3160a335a19f5c67ae888b8dcf907dd7", "parents": [ "42785799aa364a7bc34057db3e3c4bf9d5c2a744" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Sep 02 16:27:58 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Sep 04 11:47:27 2025 -0700" }, "message": "fix(cocotb): Correct decorator syntax in debug test\n\nThis commit fixes a syntax error in the `core_mini_axi_debug.py` test file where a `@cocotb.test` decorator was missing parentheses. It has been corrected to `@cocotb.test()`.\n\nAdditionally, the `core_mini_axi_debug_scalar_registers` test is now included in the `core_mini_axi_debug_cocotb` test suite in the BUILD file.\n\nChange-Id: I0cb3216fd36da8db039b3202660cf6ef6c7d244e\n" }, { "commit": "42785799aa364a7bc34057db3e3c4bf9d5c2a744", "tree": "e630d7ac626020d654aa8050a0c56d2b2c0f3391", "parents": [ "dfae871cf536ca69b522223194a3ed22e17a791a" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Sep 03 18:23:03 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Sep 03 19:04:25 2025 -0700" }, "message": "Mask LsuV2 regfile writes based on faults.\n\nChange-Id: I5903a12366394c0cbfa51736db97b59061bb5915\n" }, { "commit": "dfae871cf536ca69b522223194a3ed22e17a791a", "tree": "68e67b28417bc65ece551f652f41a47a58854dca", "parents": [ "2affd50913a921de700444d52189c8a42fc4e460" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Sep 03 17:59:09 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Sep 03 19:04:14 2025 -0700" }, "message": "Apply masks to all write ports.\n\nChange-Id: If9636c190777ed28bc52b9f881ffa4a56878f11e\n" }, { "commit": "2affd50913a921de700444d52189c8a42fc4e460", "tree": "8b8adb5acab995b8ecd20b7df362f9ca1ccfa3b8", "parents": [ "f66f498a5203f2248b18f998b39b5c777833e94c" ], "author": { "name": "Stefan Hall", "email": "stefanhall@google.com", "time": "Tue Sep 02 16:50:25 2025 -0700" }, "committer": { "name": "Stefan Hall", "email": "stefanhall@google.com", "time": "Tue Sep 02 16:55:25 2025 -0700" }, "message": "CircularBufferMulti replace when with Mux\n\n\u0027when\u0027 replaced with \u0027Mux\u0027 in CircularBufferMulti in order to make the\ncode safer (all states are defined) and more concise. In this case\nhardware generated should be identical.\n\nChange-Id: I3df562801341274778443b80ca00c57c43a0d69d\n" }, { "commit": "f66f498a5203f2248b18f998b39b5c777833e94c", "tree": "500d60d7fabe94e0fb0bd512e022f5bd54f87c9e", "parents": [ "7eb4dec16585041a9e44cef6820d8a8528c34d41" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Sat Aug 30 17:56:13 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Sep 02 16:15:44 2025 -0700" }, "message": "Fault for reduction instructions when vstart !\u003d 0.\n\nChange-Id: I69c8f28402e760971d23b63776bec3afd68110b7\n" }, { "commit": "7eb4dec16585041a9e44cef6820d8a8528c34d41", "tree": "60891e1113a31c7fe0b194ee3ad6006c63cc9678", "parents": [ "296d738bd7a11f16664b4f5912a74c527b633b96" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Aug 27 20:39:44 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Sep 02 14:36:18 2025 -0700" }, "message": "Add SvGenerationUtils.\n\nUseful functions for interfacing Chisel with SV.\n\nChange-Id: I6f08996d4017f38864eada9a34f6169525a58ecc\n" }, { "commit": "296d738bd7a11f16664b4f5912a74c527b633b96", "tree": "dd084cf0cba11bcad5f286e809de6018c08efb0e", "parents": [ "6edcd4e5a3f1bba747833970daf821a54c573fd1" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 19 15:51:03 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Aug 28 17:16:23 2025 -0700" }, "message": "fix(cocotb): Improve test discovery for tests with arguments\n\nThe `update_cocotb_tests.py` script previously used a regex that failed to discover cocotb tests defined with arguments in the `@cocotb.test()` decorator (e.g., `@cocotb.test(skip\u003dTrue)`).\n\nThis commit updates the regex to correctly parse these definitions.\n\nAs a result of applying the updated script, several `BUILD` files have been regenerated to:\n- Create uniquely named testcase lists for each `cocotb_test_suite`.\n- Correctly list all discovered tests.\n\nChange-Id: Id0da034c786f333f731f669e1ee69909b9416c64\n" }, { "commit": "6edcd4e5a3f1bba747833970daf821a54c573fd1", "tree": "df6c375c3259669b31a287455047a52f92505056", "parents": [ "0004fc32c1b0d4287693d1d0d1febce780730cf0" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 19 13:31:45 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Aug 28 17:16:21 2025 -0700" }, "message": "refactor(fpga): Replace tlgen xbar with Chisel-based KelvinXbar\n\nThis commit replaces the legacy `tlgen`-based crossbar with the new,\ndata-driven Chisel-based `KelvinXbar` in the FPGA design. This change\nsimplifies the build system, improves maintainability, and provides a\nmore flexible and robust interconnect.\n\nKey changes:\n- Removed the `tlgen` and `post_process_xbar.py` infrastructure from\n the FPGA build system.\n- Instantiated the new `KelvinXbar` in `kelvin_soc.sv`, replacing the\n old crossbar and all associated width-sizers.\n- Updated the clocking and reset logic to support the new crossbar\u0027s\n asynchronous domains, placing the Ibex core on its own clock.\n- Removed the now-redundant Verilog implementations of the TileLink-UL\n primitives (FIFOs, sockets, width bridges).\n- Added integrity generation to the `CoreTlul` module to ensure data\n integrity on the TileLink bus.\n- Increased the FPGA clock frequency to 80MHz.\n\nChange-Id: I340658419ca5cc93acee481c16334aeb026b2e7e\n" }, { "commit": "0004fc32c1b0d4287693d1d0d1febce780730cf0", "tree": "2915f8998a98da26677dcaeb2a36e0040a8b65f5", "parents": [ "be106f192e7e77a9038adf577aafa6c2d4e03b6c" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 19 13:29:51 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Aug 28 17:09:51 2025 -0700" }, "message": "feat(soc): Add data-driven TileLink-UL crossbar\n\nThis commit introduces a data-driven TileLink-UL crossbar for the\nKelvin SoC. The entire crossbar topology is defined in a single\n`CrossbarConfig.scala` file, which serves as the single source of\ntruth for hosts, devices, address maps, and connections.\n\nThe `KelvinXbar.scala` module programmatically generates the crossbar\nby instantiating and connecting the necessary TileLink primitives\n(sockets, FIFOs, width bridges) based on the configuration. This\napproach provides a flexible and maintainable way to manage the SoC\u0027s\ninterconnect.\n\nKey features:\n- Centralized configuration in `CrossbarConfig.scala`.\n- A validator to check for configuration errors, such as overlapping\n address ranges.\n- Automatic instantiation of TileLink primitives.\n- Programmatic address decoding and wiring.\n- Support for multiple, asynchronous clock domains.\n- A comprehensive cocotb test suite (`kelvin_xbar_test.py`) that\n verifies various data paths, including width and clock domain\n crossings, error responses, and integrity checks.\n\nChange-Id: I6b341aadfabcc9c2220c1818246989c35bba8ad5\n" }, { "commit": "be106f192e7e77a9038adf577aafa6c2d4e03b6c", "tree": "952c899da41243dae45144168d4f4eb585d02780", "parents": [ "148e450ec330c1cd4236d5caa317c0b4b1e34f9f" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 19 13:27:55 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Aug 28 16:49:59 2025 -0700" }, "message": "feat(bus): Add TileLink-UL primitives\n\nThis commit introduces a collection of primitive modules for building\nTileLink-UL interconnects, including FIFOs, sockets, and a width\nbridge.\n\nThe new modules are:\n- TlulFifoSync: A synchronous TileLink FIFO with optional spare\n side-channels.\n- TlulFifoAsync: An asynchronous TileLink FIFO for clock domain\n crossing, built on the rocket-chip AsyncQueue.\n- TlulSocket1N: A 1-to-N socket for steering requests from a single\n host to one of N devices.\n- TlulSocketM1: An M-to-1 socket that arbitrates requests from M\n hosts to a single device using a round-robin arbiter.\n- TlulWidthBridge: A bridge for connecting TileLink-UL buses of\n different widths.\n\nEach of these modules is accompanied by a comprehensive cocotb test\nsuite to ensure its correctness.\n\nChange-Id: I2ca34caad9332b0621a68957c043a91deee45999\n" }, { "commit": "148e450ec330c1cd4236d5caa317c0b4b1e34f9f", "tree": "126e67a850338811ada1742451acf848e9af47e0", "parents": [ "b9b0d55ba96b549756bb207a33dae793a9495859" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 19 13:27:12 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Aug 28 16:49:58 2025 -0700" }, "message": "refactor(bus): Clean up AXI/TL-UL bridges and tests\n\nThis commit refactors the AXI-to-TileLink and TileLink-to-AXI bridge\nlogic and cleans up the associated test infrastructure.\n\nKey changes:\n- Simplified the ready signal logic in `Axi2TLUL.scala` for better\n clarity and correctness.\n- Moved the cocotb test files for the AXI/TL-UL bridges from\n `hdl/chisel/src/bus` to a dedicated `tests/cocotb/tlul` directory.\n- Reorganized the Bazel BUILD files to reflect the new test locations\n and improve dependency management.\n- Added minor delays at the end of the `tlul2axi` tests to facilitate\n easier waveform debugging.\n\nChange-Id: I9a2a3c6510d34b010e0ecc2ba1da1db3e1462f2b\n" }, { "commit": "b9b0d55ba96b549756bb207a33dae793a9495859", "tree": "51f5f9da62f5b35fc9aac3d69a5309035ab27ca8", "parents": [ "131a9c544c539e32488bc30284b7ef3f2604b5d2" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 19 13:16:46 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Aug 20 11:04:51 2025 -0700" }, "message": "feat(bus): Add SECDED integrity for TileLink-UL\n\nThis commit implements SECDED (Single Error Correction, Double Error\nDetection) for the TileLink-UL bus to ensure data integrity. The\nimplementation is compatible with OpenTitan\u0027s `prim_secded_inv` logic.\n\nKey changes include:\n- A parameterized `SecdedEncoder` Chisel module that supports 32-bit,\n 57-bit, and 128-bit data widths. The 128-bit implementation uses a\n folded ECC scheme.\n- `RequestIntegrityGen/Check` and `ResponseIntegrityGen/Check` modules\n to generate and verify integrity codes for the TileLink A and D\n channels.\n- A Python-based golden model (`secded_golden.py`) for the SECDED\n logic to ensure correctness.\n- A new `TileLinkULInterface` cocotb utility for simplified,\n transaction-based testing of the TileLink bus.\n- Comprehensive cocotb tests that verify the `SecdedEncoder` against\n the golden model and test the full `TlulIntegrity` functionality,\n including fault injection.\n\nChange-Id: I20a059b78a47699f145ae397b0e037d8c56dab69\n" }, { "commit": "131a9c544c539e32488bc30284b7ef3f2604b5d2", "tree": "7bb5f132f530d037b65753c50906b211aaa96250", "parents": [ "9eaf5f18d5066408c4d93fedbfe32104fad4ead0" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 19 13:04:00 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 19 14:27:02 2025 -0700" }, "message": "feat(hdl): Add rocket-chip AsyncQueue and smoke test\n\nThis commit introduces the `AsyncQueue` from the `chipsalliance/rocket-chip`\nlibrary to handle asynchronous clock domain crossings.\n\nThe key changes are:\n- Added `rocket-chip` and `diplomacy` as external dependencies.\n- Created a `chisel_library` for the `AsyncQueue` module and its\n dependencies from `rocket-chip`.\n- Added `AsyncQueueSmokeTest.scala`, a ChiselSim-based smoke test that\n verifies the functionality of the `AsyncQueue` by passing a value\n between two different clock domains. The test also enables VCD waveform\n dumping for easier debugging.\n- Updated the `chisel_library` Bazel rule to allow suppressing fatal\n warnings, which was necessary for the `rocket-chip` library.\n\nThis provides a robust and tested solution for handling asynchronous\nFIFOs in the Chisel design.\n\nChange-Id: I53ee24a52852ebd49f27a3e2f6792b88a828f978\n" }, { "commit": "9eaf5f18d5066408c4d93fedbfe32104fad4ead0", "tree": "54b0801c50f1a1d4209c10b76318ececd4d5ee98", "parents": [ "d0b475aae98f268362652ff3de95d68bae8e7f5c" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 18 10:28:58 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 18 10:28:58 2025 -0700" }, "message": "Remove extra vd from RvvCompressedInstruction\n\n- We don\u0027t need this extra field, simply extract the low bits from\n `bits` when needed.\n\nChange-Id: I5f19f3588a52f0616425cd6ed0b9e7eb9fb10b14\n" }, { "commit": "d0b475aae98f268362652ff3de95d68bae8e7f5c", "tree": "d8b93ff6be4e6e348bd84b1dbbc93623cbcc755a", "parents": [ "129b346dcaf2741e4d808876aca51db90fd75c95" ], "author": { "name": "Naveen Dodda", "email": "ndodda@google.com", "time": "Tue Aug 12 20:50:35 2025 +0000" }, "committer": { "name": "Naveen Dodda", "email": "ndodda@google.com", "time": "Wed Aug 13 13:14:36 2025 -0700" }, "message": "Matmul rvv intrinsics in cpp\n\nThis add matmul test in cpp along with ablity to count cycles utilized.\n\nChange-Id: I01d802519b2e6c4854d63ad858f0466c8de693d2\n" }, { "commit": "129b346dcaf2741e4d808876aca51db90fd75c95", "tree": "6e39293675a9af651cc488166e7dce4814919cf9", "parents": [ "98e88c479e8f4f73e4b7e4a41e30b4b7f50c15ff" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Aug 12 12:57:18 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Aug 12 16:28:02 2025 -0700" }, "message": "Generic test bench for loads/stores.\n\nChange-Id: I1193581f8240826da99592c6193e58ece7edfb04\n" }, { "commit": "98e88c479e8f4f73e4b7e4a41e30b4b7f50c15ff", "tree": "b99f0fa44cd92bb8bbbefec85ce2e7463114401c", "parents": [ "1aee13e8cb90d42e777e5588af4a51c0d58cf1b9" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Jul 08 15:26:34 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Tue Aug 12 15:41:37 2025 -0700" }, "message": "Add RVV to tracing\n\n- Plumb the output from rvvCore\u0027s writeback into the RetirementBuffer.\n- If rvv is enabled, RetirementBuffer is expanded to handle the full\n VLEN.\n- Pass along the vector data to rvviTrace, as well.\n\nChange-Id: I418a9963e336ef9b916fc268371cc8339d0a88a8\n" }, { "commit": "1aee13e8cb90d42e777e5588af4a51c0d58cf1b9", "tree": "10e24b00746e302c785b928f91cf41258dc708ee", "parents": [ "814bc6c3ec9f287309db9571510f6dc02ab19b1d" ], "author": { "name": "Lun Dong", "email": "lundong@google.com", "time": "Thu Aug 07 21:51:07 2025 +0000" }, "committer": { "name": "Lun Dong", "email": "lundong@google.com", "time": "Tue Aug 12 15:09:13 2025 -0700" }, "message": "Add support for RVV for kelvin simulator\n\nAlso some minor clean-ups.\n\nChange-Id: I091bd299ac49a2d19ecab0c1b7ee0b6435a5d264\n" }, { "commit": "814bc6c3ec9f287309db9571510f6dc02ab19b1d", "tree": "9194a33a0eb892a702a2eee6aad22d258276b1c6", "parents": [ "e4d283fba5e582c32a83ed693328d25636bdbfd8" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Aug 07 14:45:30 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Thu Aug 07 14:45:30 2025 -0700" }, "message": "Update debug docs to reflect new addresses.\n\nChange-Id: I562bf601ebdede9cac970c9e78787a2e04ad4589\n" }, { "commit": "e4d283fba5e582c32a83ed693328d25636bdbfd8", "tree": "b422701a3f18e9b6952b018590616839973eacc0", "parents": [ "c16307dd69e87ee2c6e3179488ff7aee5d1b2c42" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Aug 07 13:11:08 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Aug 07 13:11:08 2025 -0700" }, "message": "Move debug CSR addresses\n\n- Move from 0x31000 -\u003e 0x30800.\n\nChange-Id: I90e8955b79d065beb72505ef5e7d409a07bd0c65\n" }, { "commit": "c16307dd69e87ee2c6e3179488ff7aee5d1b2c42", "tree": "b17380cfa25d46fd0dbeff3b407d9d8046a566ac", "parents": [ "59bb2dda94bb558c3636f6e2a5a4e88af2403554" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 04 13:44:21 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Thu Aug 07 10:43:31 2025 -0700" }, "message": "feat(fpga): Add Kelvin SoC top-level and build infrastructure\n\nChange-Id: I93885002bc8675f17f62d75440fa39ece7ddc3e0\n" }, { "commit": "59bb2dda94bb558c3636f6e2a5a4e88af2403554", "tree": "21fde34535faf7490b7192fe042226c97a8a1e92", "parents": [ "a9d0294073a83fec97fae4992cd231c1cdde6dd8" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 04 13:44:14 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Aug 06 16:55:45 2025 -0700" }, "message": "feat(fpga): Add supporting IPs for Kelvin SoC\n\nChange-Id: I127d67f8c0e87d13972c7b804ba8db8dc4ffc202\n" }, { "commit": "a9d0294073a83fec97fae4992cd231c1cdde6dd8", "tree": "bfbf71d49e5245a950910a98f959241e9af4b98a", "parents": [ "502e0d9a666f48d9eab7fe8e67a727e2d4fbe165" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 04 13:44:06 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Aug 06 16:55:44 2025 -0700" }, "message": "feat(fpga): Add Ibex core IP and generation docs\n\nChange-Id: Ia89d87940b11e60e17c74669a36fc5cbe7694cb2\n" }, { "commit": "502e0d9a666f48d9eab7fe8e67a727e2d4fbe165", "tree": "6c39deab1d6483eb42808bc0d29cf2f974b08e0d", "parents": [ "3a18e1d3be283f77e66660c5c09face6fa416459" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 04 13:35:21 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Aug 06 16:54:35 2025 -0700" }, "message": "feat(build): Add FPGA toolchain support and enhance binary rules\n\nChange-Id: Iede67e519368f5f58ac368cf1d40acc909cd37b0\n" }, { "commit": "3a18e1d3be283f77e66660c5c09face6fa416459", "tree": "dd2ce71d36b559baf7acbbd8c5224deb9c566a9b", "parents": [ "4782b765cbd4a159b3791b2fca67243e1d47f9c3" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 04 14:55:53 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Aug 06 16:54:35 2025 -0700" }, "message": "refactor(hdl): Make CoreAxiCSR bus-width agnostic\n\nThis change refactors the CoreAxiCSR module to be bus-width agnostic.\nThis is a precursor to adding TileLink support, which has a different\nbus width than AXI.\n\nChange-Id: I83424b4b587a5bd6833d9a5e9db862a613af2210\n" }, { "commit": "4782b765cbd4a159b3791b2fca67243e1d47f9c3", "tree": "48769ed4790e6f6150b990501be247ac08a8f711", "parents": [ "97b73bfa8229815735763bc6335181a8c732ffc8" ], "author": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Mon Aug 04 14:54:34 2025 -0700" }, "committer": { "name": "Alex Van Damme", "email": "atv@google.com", "time": "Wed Aug 06 16:54:35 2025 -0700" }, "message": "feat(hdl): Add Chisel TL-UL \u003c-\u003e AXI bridges and CoreTlul\n\nChange-Id: I2ffc39a7d559eb64074c214c18e5f46e30f84aa1\n" }, { "commit": "97b73bfa8229815735763bc6335181a8c732ffc8", "tree": "aa7cb6cd0f202006f89216f53f26a0fe408738d9", "parents": [ "088a57782dbdf57660439a9b53b6cdda89d2d2fb" ], "author": { "name": "zsp_hw_cd_dev", "email": "beck.zhang@verisilicon.com", "time": "Tue Aug 05 10:55:33 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Wed Aug 06 13:05:23 2025 -0700" }, "message": "Clean lint warning: W416b,W362,W486...\n\nChange-Id: Ie5350b57c334c856fee8815411ea03960649bfa5\n" }, { "commit": "088a57782dbdf57660439a9b53b6cdda89d2d2fb", "tree": "1f9c492f77419582f13f5f7d1718be5227adcf88", "parents": [ "8dc9126d8ae0da44219fa3f04f0149968641732c" ], "author": { "name": "pu.wang", "email": "pu.wang@verisilicon.com", "time": "Fri Jul 25 17:52:41 2025 +0800" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Aug 05 10:51:45 2025 -0700" }, "message": "update monitor in rvv backend tb\n\nChange-Id: I1b7b6de2c4b25f32340b420fa5ca7904f466fc44\n" }, { "commit": "8dc9126d8ae0da44219fa3f04f0149968641732c", "tree": "ee7e6ab6a2974f2d1d164c3530f70595bcefa391", "parents": [ "7f34b1728279dec1d6f6159a1314557edaefc5e2" ], "author": { "name": "pu.wang", "email": "pu.wang@verisilicon.com", "time": "Tue Jul 22 16:26:10 2025 +0800" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Aug 05 10:51:36 2025 -0700" }, "message": "Update rvv_backend exclusion file\n\nChange-Id: I6aacbe3c238ec8d4c3f36fd6172a2851524b917b\n" }, { "commit": "7f34b1728279dec1d6f6159a1314557edaefc5e2", "tree": "fdfde50ecf5e154a22f0a8c8395f1c163e2e0e0a", "parents": [ "c0600ce66c09cd536a49d88eb3cb1aaf788dcbc8" ], "author": { "name": "Tianyu", "email": "Tianyu@verisilicon.com", "time": "Mon Jul 14 17:11:31 2025 +0800" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Aug 05 10:49:53 2025 -0700" }, "message": "update waiver file for decoder\n\nChange-Id: I625b7318d7f758186eb50aca4c5d99b395bba7c0\n" }, { "commit": "c0600ce66c09cd536a49d88eb3cb1aaf788dcbc8", "tree": "501084a12115d95d294bdd8abfd117c5872ead2e", "parents": [ "150b1ae6e6718e363331ea498e45bd7b1f529231" ], "author": { "name": "pu.wang", "email": "pu.wang@verisilicon.com", "time": "Mon Jul 14 14:48:32 2025 +0800" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Aug 05 10:49:42 2025 -0700" }, "message": "update backend exclusion files\n\nChange-Id: I339fadbd71cb3de50c74d570e20391e0b28327c2\n" }, { "commit": "150b1ae6e6718e363331ea498e45bd7b1f529231", "tree": "c66ea6fa43d92ff4f5b5ebc58a34cc93110bfa54", "parents": [ "9bb0dd9d19e7b9d78ac4e4bc1c9c9f7663cc63e2" ], "author": { "name": "pu.wang", "email": "pu.wang@verisilicon.com", "time": "Wed Jul 09 10:52:33 2025 +0800" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Tue Aug 05 10:48:24 2025 -0700" }, "message": "Fix constraint reserve inst\n\nChange-Id: I3ced524e4c918f50290537349078dacef67a0622\n" }, { "commit": "9bb0dd9d19e7b9d78ac4e4bc1c9c9f7663cc63e2", "tree": "f8e72d5df56855797e67c322fb052ea2ef2289e0", "parents": [ "ee09cb611c1027c0d44c4beaac985ed62e67f035" ], "author": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Aug 01 10:35:28 2025 -0700" }, "committer": { "name": "Derek Chow", "email": "derekjchow@google.com", "time": "Fri Aug 01 13:53:47 2025 -0700" }, "message": "Fill in unreachable state in cvfpu.\n\nAddress ELAB-1094\n\nChange-Id: Iea6bc593f8e02f8df0a86f5f2fb121000d3e79b2\n" } ], "next": "ee09cb611c1027c0d44c4beaac985ed62e67f035" }