| commit | e6060aafe8e500deb08890edbbb718c61f990aee | [log] [tgz] |
|---|---|---|
| author | Zhidong Liang <Zhidong.Liang@verisilicon.com> | Tue Nov 19 14:34:39 2024 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Wed Nov 20 21:41:31 2024 +0000 |
| tree | 63209778216f7f305357d0f620a5245b5a23080f | |
| parent | 5d616da1c0654af7a59019f0bc72482392711203 [diff] |
add lint flow for RVV Change-Id: Iaac964557f3e830418b68bf40a2c3ed33565b81b
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog