| commit | 17ed624be7dc6646007793e0057dfe211a4868bd | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Aug 20 16:24:27 2024 -0700 |
| committer | Alex Van Damme <atv@google.com> | Thu Sep 05 14:07:59 2024 -0700 |
| tree | e64954a0026f5081e887c069ccee543e68333c93 | |
| parent | 94d1e41380154f09396cc541726a828f01566508 [diff] |
Run a Verilated CoreMiniAxi in Renode - Construct a simple Renode system w/ a RiscV CPU+Memory, CoreMiniAxi, and a UART. Change-Id: I57b7d18d61180f63549308dcdb2b7ac7522e7aff
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog