third_party/renode/core_axi_mini-renode.patch

diff --git a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/hdl/modules/axi/renode_axi_if.sv b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/hdl/modules/axi/renode_axi_if.sv
index 9b4d0318..3ccc5f64 100644
--- a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/hdl/modules/axi/renode_axi_if.sv
+++ b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/hdl/modules/axi/renode_axi_if.sv
@@ -7,7 +7,7 @@
 
 interface renode_axi_if #(
     int unsigned AddressWidth = 32,
-    int unsigned DataWidth = 32,
+    int unsigned DataWidth = 128,
     int unsigned TransactionIdWidth = 8
 ) (
     input logic aclk
diff --git a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp
index 4df493fb..29cf25e3 100644
--- a/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp
+++ b/src/Plugins/VerilatorPlugin/VerilatorIntegrationLibrary/src/buses/axi.cpp
@@ -9,8 +9,8 @@
 
 BaseAxi::BaseAxi(uint32_t dataWidth, uint32_t addrWidth)
 {
-    if(dataWidth != 32)
-        throw "Unsupported AXI data width";
+    if(dataWidth > 128)
+        throw "Unsupported AXI data width";
 
     this->dataWidth = dataWidth;
 
@@ -90,9 +90,9 @@ uint64_t Axi::read(int width, uint64_t addr)
 {
     uint64_t result;
 
     *arvalid = 1;
     *arlen   = 0; // TODO: Variable read length
-    *arsize  = 2; // TODO: Variable read width
+    *arsize  = std::log2(width);
     *arburst = static_cast<uint8_t>(AxiBurstType::INCR);
     *araddr  = addr;