| commit | 963bc1b11c31bcad29c69ad1a810768df9dc671e | [log] [tgz] |
|---|---|---|
| author | Tianyu Li <Tianyu.Li@verisilicon.com> | Tue Nov 19 14:34:23 2024 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Wed Nov 20 21:41:31 2024 +0000 |
| tree | d6f5cd02e822554d50e429399ea18011fe18a20f | |
| parent | bece15cfba8c5b715897220fbfed04b5b7d576bc [diff] |
1. Complete a mask instruction(vmandn) in alu. 2. Add ignore_vta_vma signal and some signals into ALU_RS_t and ROB_t Change-Id: Id02b98f827f882661d29a59ce246b14a2219233c
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog