| commit | 5c2f1750d5a92105fc79256f3d0144271da7e096 | [log] [tgz] |
|---|---|---|
| author | Srikanth Muroor <smuroor@google.com> | Wed Nov 13 20:59:14 2024 -0800 |
| committer | Srikanth Muroor <smuroor@google.com> | Wed Nov 13 21:03:45 2024 -0800 |
| tree | 1b7a08b3fd591520c13c2cceca9bef477ad713a5 | |
| parent | 1f231dd09c1d2f33c491548e8aebbe64d0fbb1c9 [diff] |
Swapping out library clockgate to the 6T version. Change-Id: Ibd8cfc3286c81fe87d64237d1b6a0867f828aab6
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog