| commit | e9d9e1f1aaf70497871b142643243c1ac6391d14 | [log] [tgz] |
|---|---|---|
| author | Srikanth Muroor <smuroor@google.com> | Wed Nov 06 12:20:23 2024 -0800 |
| committer | Srikanth Muroor <smuroor@google.com> | Wed Nov 06 21:19:40 2024 +0000 |
| tree | 768e4417f624beca47dcaca08245faba1ef63106 | |
| parent | 9a7d442d8d928327993d6fab1be6f8ad3c9ce58b [diff] |
Lint cleaning RTL fix. Change-Id: I2113c5d87c51bde74347c815a6883af63a7c82ef
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog