| commit | 9a7d442d8d928327993d6fab1be6f8ad3c9ce58b | [log] [tgz] |
|---|---|---|
| author | Derek Chow <derekjchow@google.com> | Tue Nov 05 16:44:29 2024 -0800 |
| committer | Derek Chow <derekjchow@google.com> | Wed Nov 06 20:30:42 2024 +0000 |
| tree | 745adacfe416f276f3a61f9d4e8dbdd45dc042a6 | |
| parent | 773d9ed746b80e5ada2ed8ebd2129fd0671787dd [diff] |
Conditionally include FPGA clock gate implementation. Change-Id: I136812a1796969c19c2d337e28804f243143a505
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog