| commit | bcfbc2b3765e9848d268ab270f19a67237410b49 | [log] [tgz] |
|---|---|---|
| author | Tianyu Li <Tianyu.Li@verisilicon.com> | Tue Nov 19 14:34:30 2024 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Wed Nov 20 21:41:31 2024 +0000 |
| tree | 4855ac8e6d6a8d20f824fd73d0c16db9a26a8a94 | |
| parent | 7e8caeaf604d973596e8dcf7227d303a6a9ab397 [diff] |
change its module name. Change-Id: I646f6d6ac1d678c49548da596858456c3f9ecabb
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog