| commit | 18133203e938fcb4f2a48001b0870ec8afc0049f | [log] [tgz] |
|---|---|---|
| author | Mingzhe Chen <Mingzhe.Chen@verisilicon.com> | Tue Nov 19 14:34:43 2024 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Wed Nov 20 21:41:31 2024 +0000 |
| tree | 20f907c937e7c1fafacb34c472a187e4f36c6cbe | |
| parent | 021600d5c828ca3dfd044c5e1b04748ee3796ead [diff] |
1. Add VRF struct in rvv.svh 2. Add some define in rvv_define.svh Change-Id: I51cb4b5a84224d1dc83a8ff0098ac1b769ee6724
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog