| commit | 9a0c519632346cda7442d1d00df33f4344594801 | [log] [tgz] |
|---|---|---|
| author | Tianyu Li <Tianyu Li Tianyu.Li@verisilicon.com> | Thu Jan 09 16:05:40 2025 -0800 |
| committer | Derek Chow <derekjchow@google.com> | Thu Jan 09 16:05:56 2025 -0800 |
| tree | 54932756e1b93580995e1f29d854e15f3fa9cb87 | |
| parent | 7c5fe326d46bb25b1ed5598587fefd0e70db31a0 [diff] |
Merge the content defined by Derek Change-Id: I790ceb3948b4459182915523b3e8ed4a48ad909e
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog