| commit | 021600d5c828ca3dfd044c5e1b04748ee3796ead | [log] [tgz] |
|---|---|---|
| author | Tianyu Li <Tianyu.Li@verisilicon.com> | Tue Nov 19 14:34:41 2024 +0800 |
| committer | Derek Chow <derekjchow@google.com> | Wed Nov 20 21:41:31 2024 +0000 |
| tree | 70451df43ba8ffd2551d17adfbf439355bd78e00 | |
| parent | e6060aafe8e500deb08890edbbb718c61f990aee [diff] |
Update assertion. Change-Id: If770a4217a556b9f9ad71403eba1ee7a0a04684e
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog