| commit | 048fb757883621af2248bde5d5ca3cabf28ed0c7 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Mon Aug 26 11:25:33 2024 -0700 |
| committer | Alex Van Damme <atv@google.com> | Mon Aug 26 12:39:12 2024 -0700 |
| tree | 97c6edec65858943f2c8ea5a6cbef1264306ab8a | |
| parent | d82518d5105e9b9518ed13d1e5866adfcd57d9b6 [diff] |
Adjust top-level interface for CoreAxi - Refactor CoreAxi to expose a reasonable top-level interface: - AXI Clock/Reset - 1 AXI Master - 1 AXI Slave - Gated clock input - Interrupt vector - Output interrupts - Debug - String log Change-Id: I54900cc302366c9a483b3045674c5c89fe8a9c17
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog