Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 1 | // Copyright lowRISC contributors. |
| 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | // SPDX-License-Identifier: Apache-2.0 |
Michael Schaffner | 2608b59 | 2023-01-13 14:12:48 -0800 | [diff] [blame] | 4 | { name: "csrng", |
Andreas Kurth | 6211349 | 2023-02-13 14:50:22 +0100 | [diff] [blame] | 5 | human_name: "Cryptographically Secure Random Number Generator", |
Andreas Kurth | 218294b | 2023-02-07 19:03:35 +0100 | [diff] [blame] | 6 | one_line_desc: "Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software", |
Andreas Kurth | f8500c0 | 2023-02-10 11:40:59 +0100 | [diff] [blame] | 7 | one_paragraph_desc: ''' |
Andreas Kurth | 6211349 | 2023-02-13 14:50:22 +0100 | [diff] [blame] | 8 | Cryptographically Secure Random Number Generator (CSRNG) consumes random seeds from Entropy Source and generates random numbers for separate application interface contexts, such as multiple entropy distribution networks and software. |
Andreas Kurth | f8500c0 | 2023-02-10 11:40:59 +0100 | [diff] [blame] | 9 | When used in fully deterministic mode, the random numbers are generated just based on seeds provided by the application input. |
Andreas Kurth | 6211349 | 2023-02-13 14:50:22 +0100 | [diff] [blame] | 10 | CSRNG targets compliance with [BSI's AIS31 recommendations for Common Criteria (CC)][bsi-ais31] as well as NIST's [SP 800-90A][nist-sp-800-90a] and [SP 800-90C][nist-sp-800-90c]. |
Andreas Kurth | f8500c0 | 2023-02-10 11:40:59 +0100 | [diff] [blame] | 11 | Internally, it uses the CTR_DRBG construction with a security strength of 256 bits as specified by [SP 800-90A][nist-sp-800-90a]. |
| 12 | |
| 13 | [bsi-ais31]: https://www.bsi.bund.de/SharedDocs/Downloads/DE/BSI/Zertifizierung/Interpretationen/AIS_31_Functionality_classes_for_random_number_generators_e.pdf |
| 14 | [nist-sp-800-90a]: https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-90Ar1.pdf |
| 15 | [nist-sp-800-90c]: https://csrc.nist.gov/CSRC/media/Publications/sp/800-90c/draft/documents/sp800_90c_second_draft.pdf |
| 16 | ''' |
Michael Schaffner | 2608b59 | 2023-01-13 14:12:48 -0800 | [diff] [blame] | 17 | design_spec: "../doc", |
| 18 | dv_doc: "../doc/dv", |
| 19 | hw_checklist: "../doc/checklist", |
| 20 | sw_checklist: "/sw/device/lib/dif/dif_csrng", |
| 21 | version: "1.0", |
| 22 | life_stage: "L1", |
| 23 | design_stage: "D2S", |
| 24 | verification_stage: "V2S", |
| 25 | dif_stage: "S2", |
Rupert Swarbrick | d0cbfad | 2021-06-29 17:04:51 +0100 | [diff] [blame] | 26 | clocking: [{clock: "clk_i", reset: "rst_ni"}], |
Rupert Swarbrick | 6c83129 | 2021-02-25 17:08:53 +0000 | [diff] [blame] | 27 | bus_interfaces: [ |
| 28 | { protocol: "tlul", direction: "device" } |
| 29 | ], |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 30 | param_list: [ |
Mark Branstad | c56b59d | 2021-06-09 14:34:05 -0700 | [diff] [blame] | 31 | // Random netlist constants |
| 32 | { name: "RndCnstCsKeymgrDivNonProduction", |
| 33 | desc: "Compile-time random bits for csrng state group diversification value", |
| 34 | type: "csrng_pkg::cs_keymgr_div_t", |
| 35 | randcount: "384", |
| 36 | randtype: "data", |
| 37 | } |
| 38 | { name: "RndCnstCsKeymgrDivProduction", |
| 39 | desc: "Compile-time random bits for csrng state group diversification value", |
| 40 | type: "csrng_pkg::cs_keymgr_div_t", |
| 41 | randcount: "384", |
| 42 | randtype: "data", |
| 43 | } |
| 44 | // Regular parameters |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 45 | { name: "SBoxImpl", |
Mark Branstad | ff80736 | 2020-11-16 07:56:15 -0800 | [diff] [blame] | 46 | type: "aes_pkg::sbox_impl_e", |
Pirmin Vogel | f839476 | 2021-02-19 11:32:39 +0100 | [diff] [blame] | 47 | default: "aes_pkg::SBoxImplCanright", |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 48 | desc: "Selection of the S-Box implementation. See aes_pkg.sv.", |
| 49 | local: "false", |
| 50 | expose: "true" |
| 51 | }, |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 52 | ], |
| 53 | interrupt_list: [ |
| 54 | { name: "cs_cmd_req_done" |
| 55 | desc: "Asserted when a command request is completed."} |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 56 | { name: "cs_entropy_req" |
| 57 | desc: "Asserted when a request for entropy has been made."} |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 58 | { name: "cs_hw_inst_exc" |
| 59 | desc: "Asserted when a hardware-attached CSRNG instance encounters a command exception"} |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 60 | { name: "cs_fatal_err" |
| 61 | desc: "Asserted when a FIFO error or a fatal alert occurs. Check the !!ERR_CODE register to get more information."} |
| 62 | ], |
| 63 | alert_list: [ |
Mark Branstad | 6fec52e | 2021-07-29 08:56:14 -0700 | [diff] [blame] | 64 | { name: "recov_alert", |
| 65 | desc: "This alert is triggered when a recoverable alert occurs. Check the !!RECOV_ALERT_STS register to get more information." |
| 66 | } |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 67 | { name: "fatal_alert", |
Michael Schaffner | f44853f | 2021-06-07 15:46:50 -0700 | [diff] [blame] | 68 | desc: ''' |
| 69 | This alert triggers (i) if an illegal state machine state is reached, or |
| 70 | (ii) if an AES fatal alert condition occurs, or (iii) if a fatal integrity |
| 71 | failure is detected on the TL-UL bus. |
| 72 | ''' |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 73 | } |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 74 | ], |
| 75 | inter_signal_list: [ |
Mark Branstad | ff80736 | 2020-11-16 07:56:15 -0800 | [diff] [blame] | 76 | { struct: "csrng" |
| 77 | type: "req_rsp" |
| 78 | name: "csrng_cmd" |
| 79 | act: "rsp" |
| 80 | package: "csrng_pkg" |
| 81 | width: "2", |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 82 | } |
| 83 | { struct: "entropy_src_hw_if" |
| 84 | type: "req_rsp", |
| 85 | name: "entropy_src_hw_if" |
| 86 | act: "req" |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 87 | package: "entropy_src_pkg" |
| 88 | } |
Mark Branstad | de7eba3 | 2021-03-22 14:18:38 -0700 | [diff] [blame] | 89 | { struct: "cs_aes_halt" |
| 90 | type: "req_rsp", |
| 91 | name: "cs_aes_halt" |
| 92 | act: "rsp" |
| 93 | package: "entropy_src_pkg" |
| 94 | } |
Timothy Chen | b9bc487 | 2021-10-13 15:54:02 -0700 | [diff] [blame] | 95 | { struct: "mubi8" |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 96 | type: "uni" |
Michael Schaffner | 4d8199f | 2021-05-25 18:20:19 -0700 | [diff] [blame] | 97 | name: "otp_en_csrng_sw_app_read" |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 98 | act: "rcv" |
Timothy Chen | b9bc487 | 2021-10-13 15:54:02 -0700 | [diff] [blame] | 99 | package: "prim_mubi_pkg" |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 100 | } |
Mark Branstad | ff80736 | 2020-11-16 07:56:15 -0800 | [diff] [blame] | 101 | { struct: "lc_tx" |
| 102 | type: "uni" |
Mark Branstad | 1c3b160 | 2020-12-11 15:09:10 -0800 | [diff] [blame] | 103 | name: "lc_hw_debug_en" |
Mark Branstad | ff80736 | 2020-11-16 07:56:15 -0800 | [diff] [blame] | 104 | act: "rcv" |
| 105 | default: "lc_ctrl_pkg::Off" |
| 106 | package: "lc_ctrl_pkg" |
| 107 | } |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 108 | ], |
Mark Branstad | ce92af3 | 2021-12-07 13:40:22 -0800 | [diff] [blame] | 109 | countermeasures: [ |
Mark Branstad | da2e6c8 | 2022-01-17 06:36:13 -0800 | [diff] [blame] | 110 | { name: "CONFIG.REGWEN" |
| 111 | desc: "Registers are protected from writes." |
| 112 | } |
| 113 | { name: "CONFIG.MUBI" |
| 114 | desc: "Registers have multi-bit encoded fields." |
| 115 | } |
| 116 | { name: "INTERSIG.MUBI" |
| 117 | desc: "OTP signal used to enable software access to registers." |
| 118 | } |
Mark Branstad | ca6dabf | 2022-01-17 14:57:46 -0800 | [diff] [blame] | 119 | { name: "MAIN_SM.FSM.SPARSE" |
| 120 | desc: "The CSRNG main state machine uses a sparse state encoding." |
Mark Branstad | ce92af3 | 2021-12-07 13:40:22 -0800 | [diff] [blame] | 121 | } |
Mark Branstad | ca6dabf | 2022-01-17 14:57:46 -0800 | [diff] [blame] | 122 | { name: "UPDATE.FSM.SPARSE" |
| 123 | desc: "The CSRNG update state machine uses a sparse state encoding." |
| 124 | } |
| 125 | { name: "BLK_ENC.FSM.SPARSE" |
| 126 | desc: "The CSRNG block encrypt state machine uses a sparse state encoding." |
| 127 | } |
| 128 | { name: "OUTBLK.FSM.SPARSE" |
| 129 | desc: "The CSRNG block output state machine uses a sparse state encoding." |
| 130 | } |
| 131 | { name: "GEN_CMD.CTR.REDUN" |
| 132 | desc: "The generate command uses a counter that is protected by a second counter that counts in the opposite direction." |
| 133 | } |
| 134 | { name: "DRBG_UPD.CTR.REDUN" |
| 135 | desc: "The ctr_drbg update algorthm uses a counter that is protected by a second counter that counts in the opposite direction." |
| 136 | } |
| 137 | { name: "DRBG_GEN.CTR.REDUN" |
| 138 | desc: "The ctr_drbg generate algorthm uses a counter that is protected by a second counter that counts in the opposite direction." |
| 139 | } |
| 140 | { name: "CTRL.MUBI" |
| 141 | desc: "Multi-bit field used for selection control." |
| 142 | } |
| 143 | { name: "MAIN_SM.CTR.LOCAL_ESC" |
| 144 | desc: "A mismatch detected inside any CSRNG counter moves the main state machine into a terminal error state." |
| 145 | } |
| 146 | { name: "CONSTANTS.LC_GATED" |
| 147 | desc: "Seed diversification based on the lifecycle state." |
| 148 | } |
Mark Branstad | da2e6c8 | 2022-01-17 06:36:13 -0800 | [diff] [blame] | 149 | { name: "SW_GENBITS.BUS.CONSISTENCY" |
Mark Branstad | 9599253 | 2021-12-15 08:05:23 -0800 | [diff] [blame] | 150 | desc: "Comparison on successive bus values for genbits returned on the software channel." |
Mark Branstad | ce92af3 | 2021-12-07 13:40:22 -0800 | [diff] [blame] | 151 | } |
Mark Branstad | da2e6c8 | 2022-01-17 06:36:13 -0800 | [diff] [blame] | 152 | { name: "TILE_LINK.BUS.INTEGRITY" |
Mark Branstad | 9599253 | 2021-12-15 08:05:23 -0800 | [diff] [blame] | 153 | desc: "Tilelink end-to-end bus integrity scheme." |
Mark Branstad | ce92af3 | 2021-12-07 13:40:22 -0800 | [diff] [blame] | 154 | } |
Mark Branstad | ca6dabf | 2022-01-17 14:57:46 -0800 | [diff] [blame] | 155 | { name: "AES_CIPHER.FSM.SPARSE", |
Mark Branstad | a9b005f | 2022-02-07 08:52:07 -0800 | [diff] [blame] | 156 | desc: ''' |
| 157 | The AES cipher core FSM uses a sparse state encoding. |
| 158 | See the AES module documentation for AES-specific countermeasures. |
| 159 | ''' |
Mark Branstad | ca6dabf | 2022-01-17 14:57:46 -0800 | [diff] [blame] | 160 | } |
| 161 | { name: "AES_CIPHER.FSM.REDUN", |
Mark Branstad | a9b005f | 2022-02-07 08:52:07 -0800 | [diff] [blame] | 162 | desc: ''' |
| 163 | The AES cipher core FSM uses multiple, independent logic rails. |
| 164 | See the AES module documentation for AES-specific countermeasures. |
| 165 | ''' |
Mark Branstad | ca6dabf | 2022-01-17 14:57:46 -0800 | [diff] [blame] | 166 | } |
| 167 | { name: "AES_CIPHER.CTRL.SPARSE", |
Mark Branstad | a9b005f | 2022-02-07 08:52:07 -0800 | [diff] [blame] | 168 | desc: ''' |
| 169 | Critical control signals for the AES cipher core such as handshake and MUX control signals use sparse encodings. |
| 170 | See the AES module documentation for AES-specific countermeasures. |
| 171 | ''' |
Mark Branstad | ca6dabf | 2022-01-17 14:57:46 -0800 | [diff] [blame] | 172 | } |
Mark Branstad | a9b005f | 2022-02-07 08:52:07 -0800 | [diff] [blame] | 173 | { name: "AES_CIPHER.FSM.LOCAL_ESC", |
| 174 | desc: ''' |
| 175 | The AES cipher core FSM moves to a terminal error state upon local escalation. |
| 176 | Can be triggered by AES_CIPHER.FSM.SPARSE, AES_CIPHER.FSM.REDUN, AES_CIPHER.CTR.REDUN and AES_CIPHER.CTRL.SPARSE. |
| 177 | See the AES module documentation for AES-specific countermeasures. |
| 178 | ''' |
| 179 | } |
| 180 | { name: "AES_CIPHER.CTR.REDUN", |
| 181 | desc: ''' |
| 182 | The AES round counter inside the AES cipher core FSM is protected with multiple, independent logic rails. |
| 183 | See the AES module documentation for AES-specific countermeasures. |
| 184 | ''' |
Mark Branstad | ca6dabf | 2022-01-17 14:57:46 -0800 | [diff] [blame] | 185 | } |
| 186 | { name: "AES_CIPHER.DATA_REG.LOCAL_ESC", |
Mark Branstad | a9b005f | 2022-02-07 08:52:07 -0800 | [diff] [blame] | 187 | desc: ''' |
| 188 | Upon local escalation, the AES cipher core doesn't output intermediate state. |
| 189 | See the AES module documentation for AES-specific countermeasures. |
| 190 | ''' |
Mark Branstad | ca6dabf | 2022-01-17 14:57:46 -0800 | [diff] [blame] | 191 | } |
Mark Branstad | ce92af3 | 2021-12-07 13:40:22 -0800 | [diff] [blame] | 192 | ], |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 193 | regwidth: "32", |
| 194 | registers: [ |
Michael Schaffner | ef348c9 | 2021-02-09 14:55:17 -0800 | [diff] [blame] | 195 | { name: "REGWEN", |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 196 | desc: "Register write enable for all control registers", |
Mark Branstad | a6541be | 2021-07-20 14:21:46 -0700 | [diff] [blame] | 197 | swaccess: "rw0c", |
| 198 | hwaccess: "none", |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 199 | fields: [ |
| 200 | { |
Mark Branstad | 5974167 | 2021-04-26 12:38:35 -0700 | [diff] [blame] | 201 | bits: "0", |
| 202 | desc: ''' When true, all writeable registers can be modified. |
| 203 | When false, they become read-only. |
| 204 | ''' |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 205 | resval: 1 |
Mark Branstad | 5974167 | 2021-04-26 12:38:35 -0700 | [diff] [blame] | 206 | } |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 207 | ] |
| 208 | }, |
| 209 | { name: "CTRL", |
| 210 | desc: "Control register", |
| 211 | swaccess: "rw", |
| 212 | hwaccess: "hro", |
Mark Branstad | a6541be | 2021-07-20 14:21:46 -0700 | [diff] [blame] | 213 | regwen: "REGWEN", |
Mark Branstad | 6bebda0 | 2022-02-23 14:26:58 -0800 | [diff] [blame] | 214 | tags: [// Keep HW from affecting other registers. |
Mark Branstad | 6fec52e | 2021-07-29 08:56:14 -0700 | [diff] [blame] | 215 | "excl:CsrAllTests:CsrExclWrite"] |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 216 | fields: [ |
| 217 | { |
Mark Branstad | a6541be | 2021-07-20 14:21:46 -0700 | [diff] [blame] | 218 | bits: "3:0", |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 219 | name: "ENABLE", |
Timothy Chen | b9bc487 | 2021-10-13 15:54:02 -0700 | [diff] [blame] | 220 | mubi: true |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 221 | desc: ''' |
Andreas Kurth | c6d92ff | 2022-11-17 11:39:44 +0000 | [diff] [blame] | 222 | Setting this field to kMultiBitBool4True will enable the CSRNG module. The modules |
| 223 | of the entropy complex may only be enabled and disabled in a specific order, see |
| 224 | Programmers Guide for details. |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 225 | ''' |
Timothy Chen | b9bc487 | 2021-10-13 15:54:02 -0700 | [diff] [blame] | 226 | resval: false |
Mark Branstad | a6541be | 2021-07-20 14:21:46 -0700 | [diff] [blame] | 227 | }, |
| 228 | { |
| 229 | bits: "7:4", |
| 230 | name: "SW_APP_ENABLE", |
Timothy Chen | b9bc487 | 2021-10-13 15:54:02 -0700 | [diff] [blame] | 231 | mubi: true |
Mark Branstad | a6541be | 2021-07-20 14:21:46 -0700 | [diff] [blame] | 232 | desc: ''' |
Michael Schaffner | 2e3fe6a | 2022-04-15 13:42:51 -0700 | [diff] [blame] | 233 | Setting this field to kMultiBitBool4True will enable reading from the !!GENBITS register. |
Mark Branstad | a6541be | 2021-07-20 14:21:46 -0700 | [diff] [blame] | 234 | This application interface for software (register based) will be enabled |
Mark Branstad | 5a7a1c8 | 2021-11-19 07:18:21 -0800 | [diff] [blame] | 235 | only if the otp_en_csrng_sw_app_read input vector is set to the enable encoding. |
Mark Branstad | a6541be | 2021-07-20 14:21:46 -0700 | [diff] [blame] | 236 | ''' |
Timothy Chen | b9bc487 | 2021-10-13 15:54:02 -0700 | [diff] [blame] | 237 | resval: false |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 238 | }, |
Mark Branstad | 6ae7ae4 | 2021-07-26 14:37:53 -0700 | [diff] [blame] | 239 | { |
| 240 | bits: "11:8", |
| 241 | name: "READ_INT_STATE", |
Timothy Chen | b9bc487 | 2021-10-13 15:54:02 -0700 | [diff] [blame] | 242 | mubi: true |
Mark Branstad | 6ae7ae4 | 2021-07-26 14:37:53 -0700 | [diff] [blame] | 243 | desc: ''' |
Michael Schaffner | 2e3fe6a | 2022-04-15 13:42:51 -0700 | [diff] [blame] | 244 | Setting this field to kMultiBitBool4True will enable reading from the !!INT_STATE_VAL register. |
Mark Branstad | 6ae7ae4 | 2021-07-26 14:37:53 -0700 | [diff] [blame] | 245 | Reading the internal state of the enable instances will be enabled |
Mark Branstad | 5a7a1c8 | 2021-11-19 07:18:21 -0800 | [diff] [blame] | 246 | only if the otp_en_csrng_sw_app_read input vector is set to the enable encoding. |
Mark Branstad | 6ae7ae4 | 2021-07-26 14:37:53 -0700 | [diff] [blame] | 247 | ''' |
Timothy Chen | b9bc487 | 2021-10-13 15:54:02 -0700 | [diff] [blame] | 248 | resval: false |
Mark Branstad | 6ae7ae4 | 2021-07-26 14:37:53 -0700 | [diff] [blame] | 249 | }, |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 250 | ] |
| 251 | }, |
| 252 | { |
| 253 | name: "CMD_REQ", |
| 254 | desc: "Command request register", |
| 255 | swaccess: "wo", |
| 256 | hwaccess: "hro", |
| 257 | hwqe: "true", |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 258 | fields: [ |
| 259 | { bits: "31:0", |
| 260 | name: "CMD_REQ", |
| 261 | desc: ''' |
| 262 | Writing this request with defined CSRNG commands will initiate all |
| 263 | possible CSRNG actions. The application interface must wait for the |
| 264 | "ack" to return before issuing new commands. |
| 265 | ''' |
| 266 | } |
| 267 | ] |
| 268 | }, |
| 269 | { |
Mark Branstad | 33e387f | 2020-11-06 15:00:34 -0800 | [diff] [blame] | 270 | name: "SW_CMD_STS", |
| 271 | desc: "Application interface command status register", |
| 272 | swaccess: "ro", |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 273 | hwaccess: "hwo", |
Mark Branstad | 59e7a76 | 2021-12-30 08:29:12 -0800 | [diff] [blame] | 274 | tags: [// Internal HW can modify status register |
| 275 | "excl:CsrNonInitTests:CsrExclCheck"] |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 276 | fields: [ |
| 277 | { bits: "0", |
| 278 | name: "CMD_RDY", |
| 279 | desc: '''This bit indicates when the command interface is ready to accept commands. |
| 280 | ''' |
Mark Branstad | ff80736 | 2020-11-16 07:56:15 -0800 | [diff] [blame] | 281 | resval: "1" |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 282 | } |
| 283 | { bits: "1", |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 284 | name: "CMD_STS", |
| 285 | desc: ''' |
| 286 | This one bit field is the status code returned with the application command ack. |
Mark Branstad | 33e387f | 2020-11-06 15:00:34 -0800 | [diff] [blame] | 287 | It is updated each time a command ack is asserted on the internal application |
| 288 | interface for software use. |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 289 | 0b0: Request completed successfully |
| 290 | 0b1: Request completed with an error |
| 291 | ''' |
Mark Branstad | ff80736 | 2020-11-16 07:56:15 -0800 | [diff] [blame] | 292 | resval: "0" |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 293 | } |
| 294 | ] |
| 295 | }, |
| 296 | { |
| 297 | name: "GENBITS_VLD", |
| 298 | desc: "Generate bits returned valid register", |
| 299 | swaccess: "ro", |
| 300 | hwaccess: "hwo", |
| 301 | hwext: "true", |
| 302 | fields: [ |
| 303 | { bits: "0", |
| 304 | name: "GENBITS_VLD", |
| 305 | desc: "This bit is set when genbits are available on this application interface." |
| 306 | } |
| 307 | { bits: "1", |
| 308 | name: "GENBITS_FIPS", |
| 309 | desc: "This bit is set when genbits are FIPS/CC compliant." |
| 310 | } |
| 311 | ] |
| 312 | }, |
| 313 | { |
| 314 | name: "GENBITS", |
| 315 | desc: "Generate bits returned register", |
| 316 | swaccess: "ro", |
| 317 | hwaccess: "hrw", |
| 318 | hwext: "true", |
| 319 | hwre: "true", |
| 320 | fields: [ |
| 321 | { bits: "31:0", |
| 322 | name: "GENBITS", |
| 323 | desc: ''' |
| 324 | Reading this register will get the generated bits that were requested with |
| 325 | the generate request. This register must be four times for each request |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 326 | number made. For example, a application command generate request with |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 327 | a `creq` value of 4 requires this register to be read 16 times to get all |
| 328 | of the data out of the FIFO path. |
| 329 | ''' |
| 330 | } |
| 331 | ] |
| 332 | }, |
Mark Branstad | 3ff4287 | 2020-12-15 15:18:28 -0800 | [diff] [blame] | 333 | { name: "INT_STATE_NUM", |
| 334 | desc: "Internal state number register", |
| 335 | swaccess: "rw", |
| 336 | hwaccess: "hro", |
| 337 | hwqe: "true", |
Mark Branstad | 3ff4287 | 2020-12-15 15:18:28 -0800 | [diff] [blame] | 338 | fields: [ |
| 339 | { |
| 340 | bits: "3:0", |
| 341 | name: "INT_STATE_NUM", |
| 342 | desc: ''' |
| 343 | Setting this field will set the number for which internal state can be |
| 344 | selected for a read access. Up to 16 internal state values can be chosen |
| 345 | from this register. The actual number of valid internal state fields |
Mark Branstad | 38955fc | 2021-08-12 05:23:33 -0700 | [diff] [blame] | 346 | is set by parameter NHwApps plus 1 software app. For those selections that point |
Mark Branstad | 3ff4287 | 2020-12-15 15:18:28 -0800 | [diff] [blame] | 347 | to reserved locations (greater than NHwApps plus 1), the returned value |
| 348 | will be zero. Writing this register will also reset the internal read |
Mark Branstad | 38955fc | 2021-08-12 05:23:33 -0700 | [diff] [blame] | 349 | pointer for the !!INT_STATE_VAL register. |
| 350 | Note: This register should be read back after being written to ensure |
| 351 | that the !!INT_STATE_VAL read back is accurate. |
Mark Branstad | 3ff4287 | 2020-12-15 15:18:28 -0800 | [diff] [blame] | 352 | ''' |
| 353 | }, |
| 354 | ] |
| 355 | }, |
| 356 | { |
| 357 | name: "INT_STATE_VAL", |
| 358 | desc: "Internal state read access register", |
| 359 | swaccess: "ro", |
| 360 | hwaccess: "hrw", |
| 361 | hwext: "true", |
| 362 | hwre: "true", |
| 363 | fields: [ |
| 364 | { bits: "31:0", |
| 365 | name: "INT_STATE_VAL", |
| 366 | desc: ''' |
| 367 | Reading this register will dump out the contents of the selected internal state field. |
| 368 | Since the internal state field is 448 bits wide, it will require 14 reads from this |
| 369 | register to gather the entire field. Once 14 reads have been done, the internal read |
Mark Branstad | 38955fc | 2021-08-12 05:23:33 -0700 | [diff] [blame] | 370 | pointer (selects 32 bits of the 448 bit field) will reset to zero. The !!INT_STATE_NUM |
Mark Branstad | 3ff4287 | 2020-12-15 15:18:28 -0800 | [diff] [blame] | 371 | can be re-written at this time (internal read pointer is also reset), and then |
| 372 | another internal state field can be read. |
Mark Branstad | 3ff4287 | 2020-12-15 15:18:28 -0800 | [diff] [blame] | 373 | ''' |
| 374 | } |
| 375 | ] |
| 376 | }, |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 377 | { |
| 378 | name: "HW_EXC_STS", |
| 379 | desc: "Hardware instance exception status register", |
Mark Branstad | baf037e | 2021-08-24 15:22:31 -0700 | [diff] [blame] | 380 | swaccess: "rw0c", |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 381 | hwaccess: "hwo", |
| 382 | fields: [ |
Mark Branstad | 056c2ae | 2022-07-14 11:54:48 -0700 | [diff] [blame] | 383 | { bits: "15:0", |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 384 | name: "HW_EXC_STS", |
| 385 | desc: ''' |
| 386 | Reading this register indicates whether one of the CSRNG HW instances has |
| 387 | encountered an exception. Each bit corresponds to a particular hardware |
| 388 | instance, with bit 0 corresponding to instance HW0, bit 1 corresponding |
| 389 | to instance HW1, and so forth. (To monitor the status of requests made |
Andreas Kurth | d6b778a | 2022-07-11 11:08:31 +0200 | [diff] [blame] | 390 | to the SW instance, check the !!SW_CMD_STS register). Writing a zero to this register |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 391 | resets the status bits. |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 392 | ''' |
| 393 | } |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 394 | ] |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 395 | }, |
| 396 | { |
Mark Branstad | 6fec52e | 2021-07-29 08:56:14 -0700 | [diff] [blame] | 397 | name: "RECOV_ALERT_STS", |
| 398 | desc: "Recoverable alert status register", |
| 399 | swaccess: "rw0c", |
| 400 | hwaccess: "hwo", |
| 401 | fields: [ |
| 402 | { bits: "0", |
| 403 | name: "ENABLE_FIELD_ALERT", |
| 404 | desc: ''' |
| 405 | This bit is set when the ENABLE field in the !!CTRL register is set to |
Michael Schaffner | 2e3fe6a | 2022-04-15 13:42:51 -0700 | [diff] [blame] | 406 | a value other than kMultiBitBool4True or kMultiBitBool4False. |
Mark Branstad | b3d673d | 2021-10-05 10:51:08 -0700 | [diff] [blame] | 407 | Writing a zero resets this status bit. |
Mark Branstad | 6fec52e | 2021-07-29 08:56:14 -0700 | [diff] [blame] | 408 | ''' |
| 409 | } |
| 410 | { bits: "1", |
| 411 | name: "SW_APP_ENABLE_FIELD_ALERT", |
| 412 | desc: ''' |
| 413 | This bit is set when the SW_APP_ENABLE field in the !!CTRL register is set to |
Michael Schaffner | 2e3fe6a | 2022-04-15 13:42:51 -0700 | [diff] [blame] | 414 | a value other than kMultiBitBool4True or kMultiBitBool4False. |
Mark Branstad | b3d673d | 2021-10-05 10:51:08 -0700 | [diff] [blame] | 415 | Writing a zero resets this status bit. |
Mark Branstad | 6fec52e | 2021-07-29 08:56:14 -0700 | [diff] [blame] | 416 | ''' |
| 417 | } |
| 418 | { bits: "2", |
| 419 | name: "READ_INT_STATE_FIELD_ALERT", |
| 420 | desc: ''' |
| 421 | This bit is set when the READ_INT_STATE field in the !!CTRL register is set to |
Michael Schaffner | 2e3fe6a | 2022-04-15 13:42:51 -0700 | [diff] [blame] | 422 | a value other than kMultiBitBool4True or kMultiBitBool4False. |
Mark Branstad | b3d673d | 2021-10-05 10:51:08 -0700 | [diff] [blame] | 423 | Writing a zero resets this status bit. |
Mark Branstad | 6fec52e | 2021-07-29 08:56:14 -0700 | [diff] [blame] | 424 | ''' |
| 425 | } |
Mark Branstad | e8d96bf | 2022-09-26 13:43:10 -0700 | [diff] [blame] | 426 | { bits: "3", |
| 427 | name: "ACMD_FLAG0_FIELD_ALERT", |
| 428 | desc: ''' |
| 429 | This bit is set when the FLAG0 field in the Application Command is set to |
| 430 | a value other than kMultiBitBool4True or kMultiBitBool4False. |
| 431 | Writing a zero resets this status bit. |
| 432 | ''' |
| 433 | } |
Mark Branstad | c26089a | 2021-11-02 13:32:28 -0700 | [diff] [blame] | 434 | { bits: "12", |
| 435 | name: "CS_BUS_CMP_ALERT", |
| 436 | desc: ''' |
| 437 | This bit is set when the software application port genbits bus value is equal |
| 438 | to the prior valid value on the bus, indicating a possible attack. |
| 439 | Writing a zero resets this status bit. |
| 440 | ''' |
| 441 | } |
Mark Branstad | 4902c76 | 2022-07-21 08:21:54 -0700 | [diff] [blame] | 442 | { bits: "13", |
| 443 | name: "CS_MAIN_SM_ALERT", |
| 444 | desc: ''' |
Marno van der Maas | e16b7f0 | 2022-11-22 16:14:18 +0000 | [diff] [blame] | 445 | This bit is set when an unsupported/illegal CSRNG command is being processed. |
Mark Branstad | 4902c76 | 2022-07-21 08:21:54 -0700 | [diff] [blame] | 446 | The main FSM will hang unless the module enable field is set to the disabled state. |
Mark Branstad | 4902c76 | 2022-07-21 08:21:54 -0700 | [diff] [blame] | 447 | ''' |
| 448 | } |
Mark Branstad | 6fec52e | 2021-07-29 08:56:14 -0700 | [diff] [blame] | 449 | ] |
| 450 | }, |
| 451 | { |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 452 | name: "ERR_CODE", |
| 453 | desc: "Hardware detection of error conditions status register", |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 454 | swaccess: "ro", |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 455 | hwaccess: "hwo", |
| 456 | fields: [ |
| 457 | { bits: "0", |
| 458 | name: "SFIFO_CMD_ERR", |
| 459 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 460 | This bit will be set to one when an error has been detected for the |
| 461 | command stage command FIFO. The type of error is reflected in the type status |
| 462 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 463 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 464 | ''' |
| 465 | } |
| 466 | { bits: "1", |
| 467 | name: "SFIFO_GENBITS_ERR", |
| 468 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 469 | This bit will be set to one when an error has been detected for the |
| 470 | command stage genbits FIFO. The type of error is reflected in the type status |
| 471 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 472 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 473 | ''' |
| 474 | } |
| 475 | { bits: "2", |
| 476 | name: "SFIFO_CMDREQ_ERR", |
| 477 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 478 | This bit will be set to one when an error has been detected for the |
| 479 | cmdreq FIFO. The type of error is reflected in the type status |
| 480 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 481 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 482 | ''' |
| 483 | } |
| 484 | { bits: "3", |
| 485 | name: "SFIFO_RCSTAGE_ERR", |
| 486 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 487 | This bit will be set to one when an error has been detected for the |
| 488 | rcstage FIFO. The type of error is reflected in the type status |
| 489 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 490 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 491 | ''' |
| 492 | } |
| 493 | { bits: "4", |
| 494 | name: "SFIFO_KEYVRC_ERR", |
| 495 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 496 | This bit will be set to one when an error has been detected for the |
| 497 | keyvrc FIFO. The type of error is reflected in the type status |
| 498 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 499 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 500 | ''' |
| 501 | } |
| 502 | { bits: "5", |
| 503 | name: "SFIFO_UPDREQ_ERR", |
| 504 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 505 | This bit will be set to one when an error has been detected for the |
| 506 | updreq FIFO. The type of error is reflected in the type status |
| 507 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 508 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 509 | ''' |
| 510 | } |
| 511 | { bits: "6", |
| 512 | name: "SFIFO_BENCREQ_ERR", |
| 513 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 514 | This bit will be set to one when an error has been detected for the |
| 515 | bencreq FIFO. The type of error is reflected in the type status |
| 516 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 517 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 518 | ''' |
| 519 | } |
| 520 | { bits: "7", |
| 521 | name: "SFIFO_BENCACK_ERR", |
| 522 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 523 | This bit will be set to one when an error has been detected for the |
| 524 | bencack FIFO. The type of error is reflected in the type status |
| 525 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 526 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 527 | ''' |
| 528 | } |
| 529 | { bits: "8", |
| 530 | name: "SFIFO_PDATA_ERR", |
| 531 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 532 | This bit will be set to one when an error has been detected for the |
| 533 | pdata FIFO. The type of error is reflected in the type status |
| 534 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 535 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 536 | ''' |
| 537 | } |
| 538 | { bits: "9", |
| 539 | name: "SFIFO_FINAL_ERR", |
| 540 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 541 | This bit will be set to one when an error has been detected for the |
| 542 | final FIFO. The type of error is reflected in the type status |
| 543 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 544 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 545 | ''' |
| 546 | } |
| 547 | { bits: "10", |
| 548 | name: "SFIFO_GBENCACK_ERR", |
| 549 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 550 | This bit will be set to one when an error has been detected for the |
| 551 | gbencack FIFO. The type of error is reflected in the type status |
| 552 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 553 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 554 | ''' |
| 555 | } |
| 556 | { bits: "11", |
| 557 | name: "SFIFO_GRCSTAGE_ERR", |
| 558 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 559 | This bit will be set to one when an error has been detected for the |
| 560 | grcstage FIFO. The type of error is reflected in the type status |
| 561 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 562 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 563 | ''' |
| 564 | } |
| 565 | { bits: "12", |
| 566 | name: "SFIFO_GGENREQ_ERR", |
| 567 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 568 | This bit will be set to one when an error has been detected for the |
| 569 | ggenreq FIFO. The type of error is reflected in the type status |
| 570 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 571 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 572 | ''' |
| 573 | } |
| 574 | { bits: "13", |
| 575 | name: "SFIFO_GADSTAGE_ERR", |
| 576 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 577 | This bit will be set to one when an error has been detected for the |
| 578 | gadstage FIFO. The type of error is reflected in the type status |
| 579 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 580 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 581 | ''' |
| 582 | } |
| 583 | { bits: "14", |
| 584 | name: "SFIFO_GGENBITS_ERR", |
| 585 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 586 | This bit will be set to one when an error has been detected for the |
| 587 | ggenbits FIFO. The type of error is reflected in the type status |
| 588 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 589 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 590 | ''' |
| 591 | } |
| 592 | { bits: "15", |
| 593 | name: "SFIFO_BLKENC_ERR", |
| 594 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 595 | This bit will be set to one when an error has been detected for the |
| 596 | blkenc FIFO. The type of error is reflected in the type status |
| 597 | bits (bits 28 through 30 of this register). |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 598 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 599 | ''' |
| 600 | } |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 601 | { bits: "20", |
| 602 | name: "CMD_STAGE_SM_ERR", |
| 603 | desc: ''' |
| 604 | This bit will be set to one when an illegal state has been detected for the |
| 605 | command stage state machine. This error will signal a fatal alert, and also |
| 606 | an interrupt if enabled. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 607 | This bit will stay set until the next reset. |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 608 | ''' |
| 609 | } |
| 610 | { bits: "21", |
| 611 | name: "MAIN_SM_ERR", |
| 612 | desc: ''' |
| 613 | This bit will be set to one when an illegal state has been detected for the |
| 614 | main state machine. This error will signal a fatal alert, and also |
| 615 | an interrupt if enabled. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 616 | This bit will stay set until the next reset. |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 617 | ''' |
| 618 | } |
| 619 | { bits: "22", |
| 620 | name: "DRBG_GEN_SM_ERR", |
| 621 | desc: ''' |
| 622 | This bit will be set to one when an illegal state has been detected for the |
Andreas Kurth | 6c84cbb | 2022-07-11 08:40:21 +0200 | [diff] [blame] | 623 | ctr_drbg gen state machine. This error will signal a fatal alert, and also |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 624 | an interrupt if enabled. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 625 | This bit will stay set until the next reset. |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 626 | ''' |
| 627 | } |
| 628 | { bits: "23", |
| 629 | name: "DRBG_UPDBE_SM_ERR", |
| 630 | desc: ''' |
| 631 | This bit will be set to one when an illegal state has been detected for the |
Andreas Kurth | 6c84cbb | 2022-07-11 08:40:21 +0200 | [diff] [blame] | 632 | ctr_drbg update block encode state machine. This error will signal a fatal alert, and also |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 633 | an interrupt if enabled. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 634 | This bit will stay set until the next reset. |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 635 | ''' |
| 636 | } |
| 637 | { bits: "24", |
| 638 | name: "DRBG_UPDOB_SM_ERR", |
| 639 | desc: ''' |
| 640 | This bit will be set to one when an illegal state has been detected for the |
Andreas Kurth | 6c84cbb | 2022-07-11 08:40:21 +0200 | [diff] [blame] | 641 | ctr_drbg update out block state machine. This error will signal a fatal alert, and also |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 642 | an interrupt if enabled. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 643 | This bit will stay set until the next reset. |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 644 | ''' |
| 645 | } |
| 646 | { bits: "25", |
| 647 | name: "AES_CIPHER_SM_ERR", |
| 648 | desc: ''' |
| 649 | This bit will be set to one when an AES fatal error has been detected. |
| 650 | This error will signal a fatal alert, and also |
| 651 | an interrupt if enabled. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 652 | This bit will stay set until the next reset. |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 653 | ''' |
| 654 | } |
Mark Branstad | 3192827 | 2021-11-02 12:03:33 -0700 | [diff] [blame] | 655 | { bits: "26", |
| 656 | name: "CMD_GEN_CNT_ERR", |
| 657 | desc: ''' |
Andreas Kurth | 3aa60ff | 2022-11-14 14:40:07 +0000 | [diff] [blame] | 658 | This bit will be set to one when a mismatch in any of the hardened counters |
Mark Branstad | 3192827 | 2021-11-02 12:03:33 -0700 | [diff] [blame] | 659 | has been detected. |
| 660 | This error will signal a fatal alert, and also |
| 661 | an interrupt if enabled. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 662 | This bit will stay set until the next reset. |
Mark Branstad | 3192827 | 2021-11-02 12:03:33 -0700 | [diff] [blame] | 663 | ''' |
| 664 | } |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 665 | { bits: "28", |
| 666 | name: "FIFO_WRITE_ERR", |
| 667 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 668 | This bit will be set to one when any of the source bits (bits 0 through 15 of this |
| 669 | this register) are asserted as a result of an error pulse generated from |
| 670 | any full FIFO that has been recieved a write pulse. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 671 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 672 | ''' |
| 673 | } |
| 674 | { bits: "29", |
| 675 | name: "FIFO_READ_ERR", |
| 676 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 677 | This bit will be set to one when any of the source bits (bits 0 through 15 of this |
| 678 | this register) are asserted as a result of an error pulse generated from |
| 679 | any empty FIFO that has recieved a read pulse. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 680 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 681 | ''' |
| 682 | } |
| 683 | { bits: "30", |
| 684 | name: "FIFO_STATE_ERR", |
| 685 | desc: ''' |
Mark Branstad | 0c1f180 | 2020-11-02 09:01:55 -0800 | [diff] [blame] | 686 | This bit will be set to one when any of the source bits (bits 0 through 15 of this |
| 687 | this register) are asserted as a result of an error pulse generated from |
| 688 | any FIFO where both the empty and full status bits are set. |
Mark Branstad | 0b8ff59 | 2021-12-15 14:08:36 -0800 | [diff] [blame] | 689 | This bit will stay set until the next reset. |
Mark Branstad | 12ba5ff | 2020-10-16 13:25:46 -0700 | [diff] [blame] | 690 | ''' |
| 691 | } |
| 692 | ] |
| 693 | }, |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 694 | { name: "ERR_CODE_TEST", |
| 695 | desc: "Test error conditions register", |
| 696 | swaccess: "rw", |
| 697 | hwaccess: "hro", |
| 698 | hwqe: "true", |
| 699 | regwen: "REGWEN", |
Mark Branstad | 6bebda0 | 2022-02-23 14:26:58 -0800 | [diff] [blame] | 700 | tags: [// Keep HW from affecting other registers. |
| 701 | "excl:CsrAllTests:CsrExclWrite"] |
Mark Branstad | d65d139 | 2021-02-10 13:15:39 -0800 | [diff] [blame] | 702 | fields: [ |
| 703 | { |
| 704 | bits: "4:0", |
| 705 | name: "ERR_CODE_TEST", |
| 706 | desc: ''' |
| 707 | Setting this field will set the bit number for which an error |
| 708 | will be forced in the hardware. This bit number is that same one |
| 709 | found in the !!ERR_CODE register. The action of writing this |
| 710 | register will force an error pulse. The sole purpose of this |
| 711 | register is to test that any error properly propagates to either |
| 712 | an interrupt or an alert. |
| 713 | ''' |
| 714 | }, |
| 715 | ] |
| 716 | }, |
Mark Branstad | 6bebda0 | 2022-02-23 14:26:58 -0800 | [diff] [blame] | 717 | { name: "MAIN_SM_STATE", |
| 718 | desc: "Main state machine state debug register", |
Mark Branstad | 38f5cac | 2021-04-14 07:34:23 -0700 | [diff] [blame] | 719 | swaccess: "ro", |
| 720 | hwaccess: "hwo", |
| 721 | fields: [ |
Mark Branstad | 6d4436f | 2021-07-15 09:23:15 -0700 | [diff] [blame] | 722 | { bits: "7:0", |
Mark Branstad | 44b3f6e | 2022-02-18 09:50:44 -0800 | [diff] [blame] | 723 | name: "MAIN_SM_STATE", |
| 724 | desc: '''This is the state of the CSRNG main state machine. |
| 725 | See the RTL file `csrng_main_sm` for the meaning of the values. |
Mark Branstad | 6d4436f | 2021-07-15 09:23:15 -0700 | [diff] [blame] | 726 | ''' |
Mark Branstad | 6bebda0 | 2022-02-23 14:26:58 -0800 | [diff] [blame] | 727 | resval: 0x4e |
Mark Branstad | 38f5cac | 2021-04-14 07:34:23 -0700 | [diff] [blame] | 728 | } |
| 729 | ] |
| 730 | }, |
Martin Lueker-Boden | c76cbc7 | 2020-07-21 21:13:35 +0000 | [diff] [blame] | 731 | ] |
| 732 | } |