| commit | d0cbfad15ccb1e8962e2e961ca69db4aaa3f2090 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Jun 29 17:04:51 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed Jun 30 17:10:31 2021 +0100 |
| tree | 6dc749bf86af840d3a26a153c2e20c9fa4c8b659 | |
| parent | fc5fb2da41cbb6e32814c0e438bb2d76465dbee6 [diff] |
[reggen] Pair up clock and reset signals This commit doesn't really change anything of note (indeed, there are no changes to the auto-generated SystemVerilog code!), but it changes the reggen hjson schema so that clocks and resets that belong together get bundled together. The idea is that a followup can define idle signals for "hint" clocks by adding them to the ClockingItems. This is much nicer than depending on order (it avoids counting, plus not every clock is a "hint" clock, so not every clock needs an idle signal). Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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