Google Git
Sign in
opensecura / 3p / lowrisc / opentitan / 54815c9c0b5a41c36c23b69a587573c9e2fd265c / . / hw / vendor / lowrisc_ibex / ibex_configs.yaml
blob: 4b693d0e66eb983867398f0b3ec15c53ae0d33ea [file] [log] [blame]
Greg Chadwick063e5cc2020-04-07 13:13:07 +0100[diff] [blame]1# Copyright lowRISC contributors.
2# Licensed under the Apache License, Version 2.0, see LICENSE for details.
3# SPDX-License-Identifier: Apache-2.0
4
5# Ibex configurations files, holds the parameter sets that are tested under CI.
6# Each configuration must specify the same set of parameters
7
8# Two-stage pipeline without additional branch target ALU and 3 cycle multiplier
9# (4 cycles for mulh), resulting in 2 stall cycles for mul (3 for mulh)
Philipp Wagner4f735bc2020-05-27 10:33:17 +0100[diff] [blame]10small:
Tom Robertsd14b37a2020-04-20 16:51:18 +0100[diff] [blame]11 RV32E : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]12 RV32M : "ibex_pkg::RV32MFast"
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]13 RV32B : "ibex_pkg::RV32BNone"
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]14 RegFile : "ibex_pkg::RegFileFF"
Tom Robertsd14b37a2020-04-20 16:51:18 +0100[diff] [blame]15 BranchTargetALU : 0
16 WritebackStage : 0
Tom Roberts3a5fdd62020-11-05 11:01:08 +0000[diff] [blame]17 ICache : 0
18 ICacheECC : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]19 ICacheScramble : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]20 BranchPredictor : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]21 DbgTriggerEn : 0
22 SecureIbex : 0
Philipp Wagner4f735bc2020-05-27 10:33:17 +0100[diff] [blame]23 PMPEnable : 0
24 PMPGranularity : 0
25 PMPNumRegions : 4
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]26 MHPMCounterNum : 0
27 MHPMCounterWidth : 40
Tom Roberts8ae623f2021-08-26 17:00:33 +0100[diff] [blame]28
29# Configuration to match that used in the OpenTitan project
30opentitan:
31 RV32E : 0
32 RV32M : "ibex_pkg::RV32MSingleCycle"
Pirmin Vogel69d8d272021-12-17 09:39:48 +0100[diff] [blame]33 RV32B : "ibex_pkg::RV32BOTEarlGrey"
Tom Roberts8ae623f2021-08-26 17:00:33 +0100[diff] [blame]34 RegFile : "ibex_pkg::RegFileFF"
35 BranchTargetALU : 1
36 WritebackStage : 1
37 ICache : 1
38 ICacheECC : 1
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]39 ICacheScramble : 1
Tom Roberts8ae623f2021-08-26 17:00:33 +0100[diff] [blame]40 BranchPredictor : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]41 DbgTriggerEn : 1
42 SecureIbex : 1
Tom Roberts8ae623f2021-08-26 17:00:33 +0100[diff] [blame]43 PMPEnable : 1
44 PMPGranularity : 0
45 PMPNumRegions : 16
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]46 MHPMCounterNum : 10
47 MHPMCounterWidth : 32
Greg Chadwick063e5cc2020-04-07 13:13:07 +0100[diff] [blame]48
49# ===============================
50# * EXPERIMENTAL CONFIGURATIONS *
51# ===============================
52
53# Three-stage pipeline with additional branch traget ALU and 1 cycle multiplier
54# (2 cycles for mulh) so mul does not stall (mulh stall 1 cycles). This is the
Philipp Wagner59d08722020-06-22 23:01:21 +0100[diff] [blame]55# maximum performance configuration.
56experimental-maxperf:
57 RV32E : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]58 RV32M : "ibex_pkg::RV32MSingleCycle"
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]59 RV32B : "ibex_pkg::RV32BNone"
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]60 RegFile : "ibex_pkg::RegFileFF"
Philipp Wagner59d08722020-06-22 23:01:21 +0100[diff] [blame]61 BranchTargetALU : 1
62 WritebackStage : 1
Tom Roberts3a5fdd62020-11-05 11:01:08 +0000[diff] [blame]63 ICache : 0
64 ICacheECC : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]65 ICacheScramble : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]66 BranchPredictor : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]67 DbgTriggerEn : 0
68 SecureIbex : 0
Philipp Wagner59d08722020-06-22 23:01:21 +0100[diff] [blame]69 PMPEnable : 0
70 PMPGranularity : 0
71 PMPNumRegions : 4
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]72 MHPMCounterNum : 0
73 MHPMCounterWidth : 40
Philipp Wagner59d08722020-06-22 23:01:21 +0100[diff] [blame]74
75# experimental-maxperf config above plus PMP enabled with 16 regions.
Philipp Wagner4f735bc2020-05-27 10:33:17 +0100[diff] [blame]76experimental-maxperf-pmp:
Tom Robertsd14b37a2020-04-20 16:51:18 +0100[diff] [blame]77 RV32E : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]78 RV32M : "ibex_pkg::RV32MSingleCycle"
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]79 RV32B : "ibex_pkg::RV32BNone"
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]80 RegFile : "ibex_pkg::RegFileFF"
Tom Robertsd14b37a2020-04-20 16:51:18 +0100[diff] [blame]81 BranchTargetALU : 1
82 WritebackStage : 1
Tom Roberts3a5fdd62020-11-05 11:01:08 +0000[diff] [blame]83 ICache : 0
84 ICacheECC : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]85 ICacheScramble : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]86 BranchPredictor : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]87 DbgTriggerEn : 0
88 SecureIbex : 0
Philipp Wagner4f735bc2020-05-27 10:33:17 +0100[diff] [blame]89 PMPEnable : 1
90 PMPGranularity : 0
91 PMPNumRegions : 16
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]92 MHPMCounterNum : 0
93 MHPMCounterWidth : 40
Greg Chadwick063e5cc2020-04-07 13:13:07 +0100[diff] [blame]94
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]95# experimental-maxperf-pmp config above with balanced bitmanip extension
96experimental-maxperf-pmp-bmbalanced:
Tom Robertsd14b37a2020-04-20 16:51:18 +0100[diff] [blame]97 RV32E : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]98 RV32M : "ibex_pkg::RV32MSingleCycle"
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]99 RV32B : "ibex_pkg::RV32BBalanced"
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]100 RegFile : "ibex_pkg::RegFileFF"
Tom Robertsd14b37a2020-04-20 16:51:18 +0100[diff] [blame]101 BranchTargetALU : 1
102 WritebackStage : 1
Tom Roberts3a5fdd62020-11-05 11:01:08 +0000[diff] [blame]103 ICache : 0
104 ICacheECC : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]105 ICacheScramble : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]106 BranchPredictor : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]107 DbgTriggerEn : 0
108 SecureIbex : 0
Philipp Wagner4f735bc2020-05-27 10:33:17 +0100[diff] [blame]109 PMPEnable : 1
110 PMPGranularity : 0
111 PMPNumRegions : 16
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]112 MHPMCounterNum : 0
113 MHPMCounterWidth : 40
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]114
115# experimental-maxperf-pmp config above with full bitmanip extension
116experimental-maxperf-pmp-bmfull:
117 RV32E : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]118 RV32M : "ibex_pkg::RV32MSingleCycle"
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]119 RV32B : "ibex_pkg::RV32BFull"
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]120 RegFile : "ibex_pkg::RegFileFF"
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]121 BranchTargetALU : 1
122 WritebackStage : 1
Tom Roberts3a5fdd62020-11-05 11:01:08 +0000[diff] [blame]123 ICache : 0
124 ICacheECC : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]125 ICacheScramble : 0
Tom Roberts3a5fdd62020-11-05 11:01:08 +0000[diff] [blame]126 BranchPredictor : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]127 DbgTriggerEn : 0
128 SecureIbex : 0
Tom Roberts3a5fdd62020-11-05 11:01:08 +0000[diff] [blame]129 PMPEnable : 1
130 PMPGranularity : 0
131 PMPNumRegions : 16
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]132 MHPMCounterNum : 0
133 MHPMCounterWidth : 40
Tom Roberts3a5fdd62020-11-05 11:01:08 +0000[diff] [blame]134
135# experimental-maxperf-pmp-bmfull config above with icache enabled
136experimental-maxperf-pmp-bmfull-icache:
137 RV32E : 0
138 RV32M : "ibex_pkg::RV32MSingleCycle"
139 RV32B : "ibex_pkg::RV32BFull"
140 RegFile : "ibex_pkg::RegFileFF"
141 BranchTargetALU : 1
142 WritebackStage : 1
143 ICache : 1
144 ICacheECC : 1
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]145 ICacheScramble : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]146 BranchPredictor : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]147 DbgTriggerEn : 0
148 SecureIbex : 0
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]149 PMPEnable : 1
150 PMPGranularity : 0
151 PMPNumRegions : 16
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]152 MHPMCounterNum : 0
153 MHPMCounterWidth : 40
Michael Schaffner1a1b94d2020-07-13 19:27:25 -0700[diff] [blame]154
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]155# experimental-maxperf with branch predictor switched on. This exists to allow
156# easy use of Ibex with the branch predictor in particular for CI runs. The
157# branch predictor will be enabled in all the 'maxperf' configs after further
158# development.
159experimental-branch-predictor:
160 RV32E : 0
161 RV32M : "ibex_pkg::RV32MSingleCycle"
162 RV32B : "ibex_pkg::RV32BNone"
163 RegFile : "ibex_pkg::RegFileFF"
164 BranchTargetALU : 1
165 WritebackStage : 1
Tom Roberts3a5fdd62020-11-05 11:01:08 +0000[diff] [blame]166 ICache : 0
167 ICacheECC : 0
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]168 ICacheScramble : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]169 BranchPredictor : 1
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]170 DbgTriggerEn : 0
171 SecureIbex : 0
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]172 PMPEnable : 0
173 PMPGranularity : 0
174 PMPNumRegions : 4
Timothy Chendb965132022-06-16 08:03:02 -0700[diff] [blame]175 MHPMCounterNum : 0
176 MHPMCounterWidth : 40
Pirmin Vogele3814642020-08-27 12:44:23 +0200[diff] [blame]177