commit 1a1b94d01fd7022438e2bd651e48ad2d99e3abca
author Michael Schaffner <msf@opentitan.org> Mon Jul 13 19:27:25 2020 -0700
committer Michael Schaffner <msf@google.com> Tue Jul 14 09:50:07 2020 -0700
tree 215e1e8359fea7ca057cbf36b6434b3bfaa20951
parent 82a936eb42ae8a4c342902efd42dddb946894ed2

Update lowrisc_ibex to lowRISC/ibex@6b9165f

Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
6b9165fa66b49534226acfcb739f2c252be4853c

* [doc] Update READMEs with best CoreMark results (Greg Chadwick)
* [sw] Enable choice of -march= string for CoreMark (Greg Chadwick)
* Value passed to UVM set_timeout is calculated as 1000000000 basing
  on 1ns/1ps timescale. But if you are using precompiled UVM it may be
  compiled with other timescale depending on compilation option used
  when it was compiled or tools default timescale value (uvm does not
  set timescale int the code). In this case for us precompiled UVM
  timescale is 1ps/1ps - so UVM gets 1000000000 in set timeout but
  interprets it as ps. As a result timeout is 1000 times smaller that
  you expect. That is why we are getting timeouts. It is hard to find
  perfect solution. One of them is to recompile the UVM with
  -timescale 1ns/ps (or whatever you will use for your design). (Dawid
  Zimonczyk)
* update readme for Riviera-PRO (Dawid Zimonczyk)
* correct wrong assignment to enum (Dawid Zimonczyk)
* Lint: Fix some line length warnings (Philipp Wagner)
* ibex_counter: Use always_ff (Philipp Wagner)
* Enforce lint of simple system in CI (Philipp Wagner)
* Specify data type for all parameters in simple_system (Philipp
  Wagner)
* Clarifications to the README of the simple system (Philipp Wagner)
* Only include necessary LFSR primitive (Philipp Wagner)
* Update lowrisc_ip to lowRISC/opentitan@ebf4663b (Philipp Wagner)
* [dv/ibex] Add two new interrupt/debug tests (Udi)
* [doc] Fix spelling of CoreMark (Pirmin Vogel)
* Handle --help properly in simple_system top-level (Rupert Swarbrick)
* Update lowrisc_ip to lowRISC/opentitan@9ac4f9c8 (Rupert Swarbrick)
* Use the Xilinx primitives for the Arty board (Philipp Wagner)
* [doc] Clarify that the supported version of the B extension is a
  draft (Pirmin Vogel)
* Clean up Verilator sections in core files (Philipp Wagner)
* Fix and waive Verilator lint errors in tb_cs_registers (Philipp
  Wagner)
* Remove lowrisc:prim:clock_gating from shared core collections
  (Philipp Wagner)
* Add lint for ibex_simple_system to CI (Philipp Wagner)
* ibex_simple_system: Add lint target (Philipp Wagner)
* Simplify lint targets (Philipp Wagner)
* Remove unrelated files from lint in ibex_core_tracing (Philipp
  Wagner)
* Add dependency on prim_clock_gating (Philipp Wagner)
* Fix Ibex description in core file (Philipp Wagner)
* icache: Depend on prim_assert (Philipp Wagner)
* Fix SRAM initialisation for fpga/artya example (Rupert Swarbrick)
* Drop SRAM_INIT_FILE from ibex_riscv_compliance.core (Rupert
  Swarbrick)
* Get simple_system working for VCS (Rupert Swarbrick)
* Pass MemInitFile parameter from our ram_*p wrappers (Rupert
  Swarbrick)
* Update lowrisc_ip to lowRISC/opentitan@976d9b9c (Philipp Wagner)
* Icache: It's not a draft any more (Philipp Wagner)
* Remove outdated documentation (Philipp Wagner)
* CI: Show exact command to run Verilator lint (Philipp Wagner)
* CI: Enable Verible lint for all configs (Philipp Wagner)
* CI: use the new binary name of Verible (Philipp Wagner)
* Add a waiver file for Verible lint (Philipp Wagner)
* Fix Verible lint issues (Philipp Wagner)
* Add some formal cover properties for ICache (Rupert Swarbrick)
* Add an ICacheECC parameter to ICache formal flow (Rupert Swarbrick)
* Formal protocol checking for icache <-> core interface (Rupert
  Swarbrick)
* A simple formal flow for the ICache based on SymbiYosys (Rupert
  Swarbrick)
* Move riscv-formal code into formal/riscv-formal (Rupert Swarbrick)
* [doc] Add bitmanip spec to introduction page (Philipp Wagner)
* [CI] Update Verible version (Philipp Wagner)
* Update lowrisc_ip to lowRISC/opentitan@5cae0cf1 (Rupert Swarbrick)
* [bitmanip] Optimizations and Parametrization (ganoam)
* [rtl] Fix icache xprop issue (Tom Roberts)
* Prevent writing CSR_SECURESEED to get the seed of dummy instruction
  (Xiang Wang)

Signed-off-by: Michael Schaffner <msf@opentitan.org>