commit 59d0872f458f27383e9de2745961517a60cf84f9
author Philipp Wagner <phw@lowrisc.org> Mon Jun 22 23:01:21 2020 +0100
committer Philipp Wagner <mail@philipp-wagner.com> Tue Jun 23 09:17:52 2020 +0100
tree df5cfa9f3a93b1300e9ba4763d90345880586e5b
parent 1bc20f278395641f98a0caf92f0cfe692d6791a2

Update lowrisc_ibex to lowRISC/ibex@ae547c8

Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
ae547c8d3010d86ef7afdee900d461616c3cb414

* [top_pkg] Fix style lint warnings (Michael Schaffner)
* [ibex/dv] Add clocking blocks to Ibex interfaces (Udi)
* Add a stress_all_with_reset ICache test (Rupert Swarbrick)
* Invalidate in an ICache sequence after a change to mem_err_shift
  (Rupert Swarbrick)
* Fix ICache caching window test with combination sequences (Rupert
  Swarbrick)
* Add ibex_icache_stress_all test (Rupert Swarbrick)
* Tidy up properly after overriding class in ICache back_line_seq
  (Rupert Swarbrick)
* Remove empty tasks from ibex_icache_base_vseq.sv (Rupert Swarbrick)
* Use dv_base_vseq's num_trans field rather than making our own
  (Rupert Swarbrick)
* Control core sequence's transaction count from top in ICache tests
  (Rupert Swarbrick)
* Remove ibex_icache_sanity_vseq (Rupert Swarbrick)
* Configure ICache mem_error tests from the vseq (not a test class)
  (Rupert Swarbrick)
* Pass mem_err_shift to the ICache memory model on each error check
  (Rupert Swarbrick)
* Configure ICache ECC tests just from the vseq (not a test class)
  (Rupert Swarbrick)
* [rtl] disable clock between reset and fetch_enable_i (Bert Pieters)
* Add some basic protocol checking to the icache's RAM interface
  (Rupert Swarbrick)
* Enable ICache ECC in the way dvsim.py requires (Rupert Swarbrick)
* Update lec_sv2v.sh (NilsGraf)
* Update lec_sv2v.sh (NilsGraf)
* Update lec_sv2v.do (NilsGraf)
* Add LEC script to formally verify sv2v translation (Nils Graf)
* [dv/ibex] Update riscv_core_setting to match latest version of
  riscv-dv (Udi)
* Correct window_width calculation in ICache UVM scoreboard (Rupert
  Swarbrick)
* Fix ordering in ICache core monitor start-up (Rupert Swarbrick)
* Correct "cancelled_valid" sequence in ICache UVM core coverage
  (Rupert Swarbrick)
* Allow ready & branch in ICache UVM tests (Rupert Swarbrick)
* Weight branches in icache tests to favour edges of address space
  (Rupert Swarbrick)
* Update google_riscv-dv to google/riscv-dv@6cf6b4f (Udi)
* Fix documentation markup for tracer (Philipp Wagner)
* [rtl] Remove use of `define in decoder (Bert Pieters)
* Increase priority of failure messages in ICache scoreboard (Rupert
  Swarbrick)
* Fix verbosity in ECC UVM driver (Rupert Swarbrick)
* [dv] Fix DUT probe IF paths (Tom Roberts)
* Add ECC agents to ICache DV plan document (Rupert Swarbrick)
* Define an "ECC agent" for icache testing and a test that uses it
  (Rupert Swarbrick)
* Add and use a 'badbit' RAM for ICache tests (Rupert Swarbrick)
* Enable ECC in ICache tests (Rupert Swarbrick)
* Drive the branch_spec line in ICache UVM tests (Rupert Swarbrick)
* [ibex/dv] add Questa support (Bert Pieters)
* Simplify timestamps in ICache tests (Rupert Swarbrick)
* Update lowrisc_ip to lowRISC/opentitan@c91b50f3 (Rupert Swarbrick)
* [rtl] Simplify I$ ECC error handling (Tom Roberts)
* [rtl] Use outer generate loop for latch RF (Greg Chadwick)
* [doc] Add top-level status table (Tom Roberts)
* [configs] Add a maxperf config (Tom Roberts)
* [rtl] Use gated clock for wb_stage and rf (Greg Chadwick)
* [rtl] Use generate loop in FF register file (Greg Chadwick)

Signed-off-by: Philipp Wagner <phw@lowrisc.org>