commit 4f735bc6e72691152b3a87dd7d29bb394be5c785
author Philipp Wagner <phw@lowrisc.org> Wed May 27 10:33:17 2020 +0100
committer Philipp Wagner <mail@philipp-wagner.com> Wed May 27 14:37:38 2020 +0100
tree 7b5cbcaab3cc36efff33ae2ef36a97162ec5d038
parent b1888b8a9eee558bdb53c2bc8e7a07a01bd9522e

Update lowrisc_ibex to lowRISC/ibex@dd39ec0

Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
dd39ec0c91d13d6288e4f131a39d049ccfe32173

* Optimize use of RAM primitive in icache (Philipp Wagner)
* [DV] Tie test_en_i to zero (Tom Roberts)
* [dv] Add missing signal to i$ tb (Tom Roberts)
* Use vendored-in primitives from OpenTitan (Philipp Wagner)
* Move Verilator simutil upstream to OpenTitan (Philipp Wagner)
* [CI] Install wheel for easier package installation (Philipp Wagner)
* [CI] Add dependency on pyyaml (Philipp Wagner)
* Fix deprecation warning in ibex_config.py (Philipp Wagner)
* Add '.gitignore' entry for file generated by Xcelium (Tudor Timi)
* Add wave dumping to Xcelium simulation setup (Tudor Timi)
* Fix non-standard usage of '`"` operator (Tudor Timi)
* Add Xcelium simulation setup (Tudor Timi)
* Update lowrisc_ip to lowRISC/opentitan@249b4c31 (Rupert Swarbrick)
* Merge vendor scripts for opentitan imports (Rupert Swarbrick)
* Update opentitan vendor imports to lowRISC/opentitan@249b4c31
  (Rupert Swarbrick)
* [rtl] Add speculative branch signal (Tom Roberts)
* [assertions] Tweak xprop assertion qualifiers (Tom Roberts)
* [rtl] Prevent xprop from fetch fifo (Tom Roberts)
* [rtl] Fix PMP address matching (Tom Roberts)
* [dv/icache] revert ff5c0c5 (Tom Roberts)
* [dv/icache] Add qualifications in protocol checker (Tom Roberts)
* [rtl] Various small icache bugfixes (Tom Roberts)
* [rtl] Remove redundant assignment (Tobias Wölfel)
* [rtl] Update RVFI order (Tobias Wölfel)
* [rtl] Forward register data with status (Tobias Wölfel)
* [rtl] Set RVFI program counter (Tobias Wölfel)
* [formal] Create Ibex Verilog source (Tobias Wölfel)
* [rtl] Add RVFI IXL interface (Tobias Wölfel)
* [bitmanip] Add ZBR instruction group (ganoam)
* Make RAM size configurable in compliance test system (Philipp
  Wagner)
* Use prim_generic_ram_1p in ram_1p (Philipp Wagner)
* [dv] Change performance counter access to DPI (Stefan Wallentowitz)
* Change simple system core file to provide default files (Stefan
  Wallentowitz)
* Get rid of some duplication in ICache virtual sequences (Rupert
  Swarbrick)
* Use control knobs rather than subclassing in ICache core sequences
  (Rupert Swarbrick)
* Add passthru test for ICache (Rupert Swarbrick)
* Update google_riscv-dv to google/riscv-dv@7b38e54 (Udi)
* [rtl] Add dummy instruction insertion (Tom Roberts)
* added missing cmp_opts to Riviera compilation options (Dawid
  Zimonczyk)
* [syn] Add more Ibex parameters to flow (Greg Chadwick)
* [syn] Add STA util for investigating feedthroughs (Greg Chadwick)
* Search backwards for grant seeds in icache memory model (Rupert
  Swarbrick)
* Apply new seeds to memory request in icache memory model (Rupert
  Swarbrick)
* Use --start_seed rather than --seed in core_ibex/Makefile (Rupert
  Swarbrick)
* Update google_riscv-dv to google/riscv-dv@e6a63ff (Rupert Swarbrick)
* Add a --start_seed argument to core_ibex/sim.py (Rupert Swarbrick)
* [bitmanip] Add ZBC instruction group (ganoam)
* Update ICache testplan after review meeting (Rupert Swarbrick)
* Move seed updates into sequence in ICache memory agent (Rupert
  Swarbrick)
* [rtl] Fix instr_valid_i exception issue (Tom Roberts)
* [config] Change default PMPNumRegions (Tom Roberts)
* [rtl] Add data-independent timing to multdiv_fast (Tom Roberts)
* [rtl] data-independent execution for multdiv_slow (Tom Roberts)
* [rtl] multdiv_slow general tidy-up (Tom Roberts)
* [dv] Enable use of ibex configs in DV (Greg Chadwick)
* [cfg] Add PMP parameters to ibex_config.yaml (Greg Chadwick)
* [bitmanip] Add sext.b/h instructions (ganoam)
* [bitmanip] Add ZBF instruction group (ganoam)
* [bitmanip] Add ZBE Instruction Group (ganoam)
* Print commands in core_ibex/Makefile when VERBOSE=1 (Rupert
  Swarbrick)
* Check for correct "high" bits in icache core protocol checker
  (Rupert Swarbrick)
* Weaken some checks on cache in ibex_icache_core_protocol_checker
  (Rupert Swarbrick)
* Fix assertion in ibex_icache_core_protocol_checker (Rupert
  Swarbrick)
* Update google_riscv-dv to google/riscv-dv@162ea73 (Udi)
* Add an empty common_cov_excl.el (Rupert Swarbrick)
* Allow coverage collection in icache/dv/Makefile (Rupert Swarbrick)
* Always assert ready in core driver for ICache UVM testbench (Rupert
  Swarbrick)
* [dv/cs_registers] Remove .* binding (Tom Roberts)
* Specify "-xlrm uniq_prior_final" for VCS (Rupert Swarbrick)
* Update google_riscv-dv to google/riscv-dv@ace2805 (Udi)
* [dv] Manually update dvsim config files (Udi)
* [dv] enable writeback stage and branch ALU (Udi)
* [rtl] Stop regfile writeback for load errors (Tom Roberts)

Signed-off-by: Philipp Wagner <phw@lowrisc.org>