Add include guards for svh files and fix errors. - Use ";" in structs and unions - Re-order types - Fix some duplicate encoding names. - Clean up some whitespace issues. Change-Id: I940b8e527314568542eb01e1a8f58da7d72bbe8c
diff --git a/hdl/verilog/rvv/design/rvv.svh b/hdl/verilog/rvv/design/rvv.svh index 296b328..d790ccf 100755 --- a/hdl/verilog/rvv/design/rvv.svh +++ b/hdl/verilog/rvv/design/rvv.svh
@@ -1,34 +1,37 @@ +`ifndef HDL_VERILOG_RVV_DESIGN_RVV_SVH +`define HDL_VERILOG_RVV_DESIGN_RVV_SVH + `include "rvv_define.svh" // // IF stage, RVS to Command Queue // typedef struct packed { - logic [`VTYPE_VILL_WIDTH-1:0] vill, // 0:not illegal, 1:illegal - logic [`VTYPE_VMA_WIDTH-1:0] vma, // 0:inactive element undisturbed, 1:inactive element agnostic - logic [`VTYPE_VTA_WIDTH-1:0] vta, // 0:tail undisturbed, 1:tail agnostic - logic [`VTYPE_VSEW_WIDTH-1:0] vsew, // support: 000:SEW8, 001:SEW16, 010:SEW32 - logic [`VTYPE_VLMUL_WIDTH-1:0] vlmul // support: 110:LMUL1/4, 111:LMUL1/2, 000:LMUL1, 001:LMUL2, 010:LMUL4, 011:LMUL8 + logic [`VTYPE_VILL_WIDTH-1:0] vill; // 0:not illegal, 1:illegal + logic [`VTYPE_VMA_WIDTH-1:0] vma; // 0:inactive element undisturbed, 1:inactive element agnostic + logic [`VTYPE_VTA_WIDTH-1:0] vta; // 0:tail undisturbed, 1:tail agnostic + logic [`VTYPE_VSEW_WIDTH-1:0] vsew; // support: 000:SEW8, 001:SEW16, 010:SEW32 + logic [`VTYPE_VLMUL_WIDTH-1:0] vlmul; // support: 110:LMUL1/4, 111:LMUL1/2, 000:LMUL1, 001:LMUL2, 010:LMUL4, 011:LMUL8 } VTYPE_t; typedef struct packed { - logic [`VCSR_VXRM_WIDTH-1:0] vxrm, - logic [`VCSR_VXSAT_WIDTH-1:0] vxsat + logic [`VCSR_VXRM_WIDTH-1:0] vxrm; + logic [`VCSR_VXSAT_WIDTH-1:0] vxsat; } VCSR_t; typedef struct packed { - logic [`VSTART_WIDTH-1:0] vstart, - logic [`VL_WIDTH-1:0] vl, - VTYPE_t vtype, - VCSR_t vcsr + logic [`VSTART_WIDTH-1:0] vstart; + logic [`VL_WIDTH-1:0] vl; + VTYPE_t vtype; + VCSR_t vcsr; } VECTOR_CSR_t; typedef struct packed { - logic [`PC_WIDTH-1:0] insts_pc, - logic [`INST_WIDTH-1:0] insts, - VECTOR_CSR_t vector_csr, - logic [`XLEN-1:0] rs1_data -} INST_t; + logic [`PC_WIDTH-1:0] insts_pc; + logic [`INST_WIDTH-1:0] insts; + VECTOR_CSR_t vector_csr; + logic [`XLEN-1:0] rs1_data; +} INST_t; // // DE stage, Uops Queue to Dispatch unit @@ -51,7 +54,7 @@ OPIVX, // vs2, rs1, vd. OPFVF, // vs2, rs1, vd. float, not support OPMVX, // vs2, rs1, vd/rd. - OPCFG // vset* instructions + OPCFG // vset* instructions } EXE_FUNCT3_e; // when EXE_UNIT_e is not LSU, it identifys what instruction, vadd or vmacc or ..? based on inst_encoding[31:26] @@ -62,13 +65,13 @@ VMINU = 6'b000_100, VMIN = 6'b000_101, VMAXU = 6'b000_110, - VMAXU = 6'b000_111, + VMAX = 6'b000_111, VAND = 6'b001_001, VOR = 6'b001_010, VXOR = 6'b001_011, VRGATHER = 6'b001_100, VSLIDEUP = 6'b001_110, - VRGATHEREI16 = 6'b001_110, + // VRGATHEREI16 = 6'b001_110, // Overlaps with VSLIDEUP VSLIDEDOWN = 6'b001_111, VADC = 6'b010_000, VMADC = 6'b010_001, @@ -98,7 +101,7 @@ VNCLIPU = 6'b101_110, VNCLIP = 6'b101_111, VWREDSUMU = 6'b110_000, - VWREDSUM = 6'b110_001 + VWREDSUM = 6'b110_001 } OPI_TYPE_e; typedef enum logic [5:0] { @@ -144,17 +147,17 @@ VWADD = 6'b110_001, VWSUBU = 6'b110_010, VWSUB = 6'b110_011, - VWADDU = 6'b110_100, - VWADD = 6'b110_101, - VWSUBU = 6'b110_110, - VWSUB = 6'b110_111, + VWADDUW = 6'b110_100, + VWADDW = 6'b110_101, + VWSUBUW = 6'b110_110, + VWSUBW = 6'b110_111, VWMULU = 6'b111_000, VWMULSU = 6'b111_010, VWMUL = 6'b111_011, VWMACCU = 6'b111_100, VWMACC = 6'b111_101, VWMACCUS = 6'b111_110, - VWMACCSU = 6'b111_111 + VWMACCSU = 6'b111_111 } OPM_TYPE_e; // when OPM_TYPE_e=vwxunary0, the uop could be vcpop.m, vfirst.m and vmv. They can be distinguished by vs1 field(inst_encoding[19:15]). @@ -183,47 +186,47 @@ // when EXE_UNIT_e is LSU, it identifys what LSU instruction, unit-stride load or indexed store or ..? based on inst_encoding[31:26] typedef enum logic [1:0] { - US, // Unit-Stride - IU, // Indexed Unordered - CS, // Constant Stride - IO // Indexed Ordered + LSU_MOP_US, // Unit-Stride + LSU_MOP_IU, // Indexed Unordered + LSU_MOP_CS, // Constant Stride + LSU_MOP_IO // Indexed Ordered } LSU_MOP_e; // It identifys what unit-stride instruction when LSU_MOP_e=US, based on inst_encoding[24:20] typedef enum logic [1:0] { - US, // Unit-Stride load/store - WR, // Whole Register load/store - MK, // MasK load/store, EEW=8(inst_encoding[14:12]=3'b000) - FF // Faul-only-First load + LSU_UMOP_US, // Unit-Stride load/store + LSU_UMOP_WR, // Whole Register load/store + LSU_UMOP_MK, // MasK load/store, EEW=8(inst_encoding[14:12]=3'b000) + LSU_UMOP_FF // Fault-only-First load } LSU_UMOP_e; // It identifys what inst_encoding[11:7] is used for when LSU instruction, based on inst_encoding[5] -typedef enum logic [0] { - LOAD, // when load, inst_encoding[11:7] is seen as vs3 - STORE // when load, inst_encoding[11:7] is seen as vd +typedef enum logic { + LSU_IS_STORE_LOAD, // when load, inst_encoding[11:7] is seen as vs3 + LSU_IS_STORE_STORE // when load, inst_encoding[11:7] is seen as vd } LSU_IS_STORE_e; // combine those signals to LSU_TYPE typedef struct packed { - logic rsv, // reserved - LSU_MOP_e lsu_mop, - LSU_UMOP_e lsu_umop, - LSU_IS_STORE_e lsu_is_store + logic rsv; // reserved + LSU_MOP_e lsu_mop; + LSU_UMOP_e lsu_umop; + LSU_IS_STORE_e lsu_is_store; } LSU_TYPE_t; // function opcode typedef union packed { - OPI_TYPE_e opi_funct, - OPM_TYPE_e opm_funct, - LSU_TYPE_t lsu_funct + OPI_TYPE_e opi_funct; + OPM_TYPE_e opm_funct; + LSU_TYPE_t lsu_funct; } FUNCT6_u; // vs1 field typedef union packed { - OPM_VWXUNARY0_e vwxunary0_funct, - OPM_VXUNARY0_e vxunary0_funct, - OPM_VMXUNARY0_e vmxunary0_funct, - logic [`REGFILE_INDEX_WIDTH-1:0] vs1_index, + OPM_VWXUNARY0_e vwxunary0_funct; + OPM_VXUNARY0_e vxunary0_funct; + OPM_VMXUNARY0_e vmxunary0_funct; + logic [`REGFILE_INDEX_WIDTH-1:0] vs1_index; } VS1_u; // uop classification used for dispatch rule @@ -244,34 +247,34 @@ // the uop struct stored in Uops Queue typedef struct packed { - logic [`PC_WIDTH-1:0] uop_pc, - EXE_UNIT_e uop_exe_unit, - EXE_FUNCT3_e uop_funct3, - FUNCT6_u uop_funct6, - UOP_CLASS_e uop_class, - VECTOR_CSR_t vector_csr, + logic [`PC_WIDTH-1:0] uop_pc; + EXE_UNIT_e uop_exe_unit; + EXE_FUNCT3_e uop_funct3; + FUNCT6_u uop_funct6; + UOP_CLASS_e uop_class; + VECTOR_CSR_t vector_csr; - logic vm, // Original 32bit instruction encoding: insts[25] - logic [`REGFILE_INDEX_WIDTH-1:0] vd_index, // Original 32bit instruction encoding: insts[11:7].this index is also used as vs3 in some uops - EEW_e vd_eew, - logic vd_valid, - VS1_u vs1, // when vs1_valid=1, vs1 field is used as vs1_index to address VRF - EEW_e vs1_eew, // when vs1_valid=0, vs1 field is used to decode some OPMVV uops - logic vs1_valid, - logic [`REGFILE_INDEX_WIDTH-1:0] vs2_index, // Original 32bit instruction encoding: insts[24:20] - EEW_e vs2_eew, - logic vs2_valid, - logic [`REGFILE_INDEX_WIDTH-1:0] rd_index, // Original 32bit instruction encoding: insts[11:7]. - logic rd_index_valid, - logic [`XLEN-1:0] rs1_data, // rs1_data could be from X[rs1] and imm(insts[19:15]). If it is imm, the 5-bit imm(insts[19:15]) will be sign-extend or zero-extend(shift instructions...) to XLEN-bit. - logic rs1_data_valid, - - logic [`UOP_INDEX_WIDTH-1:0] uop_index, // used for calculate v0_start in DP stage - logic last_uop_valid // one instruction may be split to many uops, this signal is used to specify the last uop in those uops of one instruction. -} UOP_QUEUE_t; + logic vm; // Original 32bit instruction encoding: insts[25] + logic [`REGFILE_INDEX_WIDTH-1:0] vd_index; // Original 32bit instruction encoding: insts[11:7].this index is also used as vs3 in some uops + EEW_e vd_eew; + logic vd_valid; + VS1_u vs1; // when vs1_valid=1, vs1 field is used as vs1_index to address VRF + EEW_e vs1_eew; // when vs1_valid=0, vs1 field is used to decode some OPMVV uops + logic vs1_valid; + logic [`REGFILE_INDEX_WIDTH-1:0] vs2_index; // Original 32bit instruction encoding: insts[24:20] + EEW_e vs2_eew; + logic vs2_valid; + logic [`REGFILE_INDEX_WIDTH-1:0] rd_index; // Original 32bit instruction encoding: insts[11:7]. + logic rd_index_valid; + logic [`XLEN-1:0] rs1_data; // rs1_data could be from X[rs1] and imm(insts[19:15]). If it is imm, the 5-bit imm(insts[19:15]) will be sign-extend or zero-extend(shift instructions...) to XLEN-bit. + logic rs1_data_valid; + + logic [`UOP_INDEX_WIDTH-1:0] uop_index; // used for calculate v0_start in DP stage + logic last_uop_valid; // one instruction may be split to many uops, this signal is used to specify the last uop in those uops of one instruction. +} UOP_QUEUE_t; // -// DP stage, +// DP stage, // // VRF struct typedef struct packed { @@ -311,218 +314,219 @@ // ALU reservation station struct typedef union packed { - logic [`VLEN-1:0] v0_data, - logic [`VLEN-1:0] vd_data + logic [`VLEN-1:0] v0_data; + logic [`VLEN-1:0] vd_data; }VS3_u; typedef struct packed { - logic [`ROB_DEPTH_WIDTH-1:0] rob_entry, - FUNCT6_u uop_funct6, - EXE_FUNCT3_e uop_funct3, - logic [`VSTART_WIDTH-1:0] vstart, + logic [`ROB_DEPTH_WIDTH-1:0] rob_entry; + FUNCT6_u uop_funct6; + EXE_FUNCT3_e uop_funct3; + logic [`VSTART_WIDTH-1:0] vstart; // vm field can be used to identify vmadc.v?m/vmadc.v? uop in the same uop_funct6(6'b010000). - // vm field can be used to identify vmsbc.v?m/vmsbc.v? uop in the same uop_funct6(6'b010011). - logic vm, - // rounding mode - logic [`VCSR_VXRM-1:0] vxrm, + // vm field can be used to identify vmsbc.v?m/vmsbc.v? uop in the same uop_funct6(6'b010011). + logic vm; + // rounding mode + logic [`VCSR_VXRM_WIDTH-1:0] vxrm; // when the uop is vmadc.v?m/vmsbc.v?m, the uop will use v0_data as the third vector operand. // when the uop is mask uop(vmandn,vmand,...), the uop will use vd_data as the third vector operand. - VS3_u vs3_data, + VS3_u vs3_data; // when vs1_data_valid=0, vs1_data is used to decode some OPMVV uops // when vs1_data_valid=1, vs1_data is valid as a vector operand - VS1_u vs1, - logic [`VLEN-1:0] vs1_data, - EEW_e vs1_eew, - logic vs1_data_valid, - ELE_TYPE_t vs1_type, - logic [`VLEN-1:0] vs2_data, - EEW_e vs2_eew, - logic vs2_data_valid, - ELE_TYPE_t vs2_type, + VS1_u vs1; + logic [`VLEN-1:0] vs1_data; + EEW_e vs1_eew; + logic vs1_data_valid; + ELE_TYPE_t vs1_type; + logic [`VLEN-1:0] vs2_data; + EEW_e vs2_eew; + logic vs2_data_valid; + ELE_TYPE_t vs2_type; // rs1_data could be from X[rs1] and imm(insts[19:15]). If it is imm, the 5-bit imm(insts[19:15]) will be sign-extend to XLEN-bit. - logic [`XLEN-1:0] rs1_data, - logic rs1_data_valid -} ALU_RS_t; + logic [`XLEN-1:0] rs1_data; + logic rs1_data_valid; +} ALU_RS_t; // DIV reservation station struct typedef struct packed { - logic [`ROB_DEPTH_WIDTH-1:0] rob_entry, - FUNCT6_u uop_funct6, - EXE_FUNCT3_e uop_funct3, + logic [`ROB_DEPTH_WIDTH-1:0] rob_entry; + FUNCT6_u uop_funct6; + EXE_FUNCT3_e uop_funct3; // when vs1_data_valid=1, vs1_data is valid as a vector operand - logic [`VLEN-1:0] vs1_data, - EEW_e vs1_eew, - logic vs1_data_valid, - ELE_TYPE_t vs1_type, - logic [`VLEN-1:0] vs2_data, - EEW_e vs2_eew, - logic vs2_data_valid, - ELE_TYPE_t vs2_type, - // rs1_data could be from X[rs1] and imm(insts[19:15]). If it is imm, the 5-bit imm(insts[19:15]) will be sign-extend to XLEN-bit. - logic [`XLEN-1:0] rs1_data, - logic rs1_data_valid -} DIV_RS_t; + logic [`VLEN-1:0] vs1_data; + EEW_e vs1_eew; + logic vs1_data_valid; + ELE_TYPE_t vs1_type; + logic [`VLEN-1:0] vs2_data; + EEW_e vs2_eew; + logic vs2_data_valid; + ELE_TYPE_t vs2_type; + // rs1_data could be from X[rs1] and imm(insts[19:15]). If it is imm, the 5-bit imm(insts[19:15]) will be sign-extend to XLEN-bit. + logic [`XLEN-1:0] rs1_data; + logic rs1_data_valid; +} DIV_RS_t; // MUL and MAC reservation station struct -typedef struct packed { - logic [`ROB_DEPTH_WIDTH-1:0] rob_entry, - FUNCT6_u uop_funct6, - EXE_FUNCT3_e uop_funct3, - logic [`VCSR_VXRM-1:0] vxrm, // rounding mode - - logic [`VLEN-1:0] vs1_data, - EEW_e vs1_eew, - logic vs1_data_valid, - ELE_TYPE_t vs1_type, - logic [`VLEN-1:0] vs2_data, - EEW_e vs2_eew, - logic vs2_data_valid, - ELE_TYPE_t vs2_type, - logic [`VLEN-1:0] vs3_data, - EEW_e vs3_eew, - logic vs3_data_valid, - ELE_TYPE_t vs3_type, - // rs1_data could be from X[rs1] and imm(insts[19:15]). If it is imm, the 5-bit imm(insts[19:15]) will be sign-extend to XLEN-bit. - logic [`XLEN-1:0] rs1_data, - logic rs1_data_valid -} MUL_RS_t; +typedef struct packed { + logic [`ROB_DEPTH_WIDTH-1:0] rob_entry; + FUNCT6_u uop_funct6; + EXE_FUNCT3_e uop_funct3; + logic [`VCSR_VXRM_WIDTH-1:0] vxrm; // rounding mode + + logic [`VLEN-1:0] vs1_data; + EEW_e vs1_eew; + logic vs1_data_valid; + ELE_TYPE_t vs1_type; + logic [`VLEN-1:0] vs2_data; + EEW_e vs2_eew; + logic vs2_data_valid; + ELE_TYPE_t vs2_type; + logic [`VLEN-1:0] vs3_data; + EEW_e vs3_eew; + logic vs3_data_valid; + ELE_TYPE_t vs3_type; + // rs1_data could be from X[rs1] and imm(insts[19:15]). If it is imm, the 5-bit imm(insts[19:15]) will be sign-extend to XLEN-bit. + logic [`XLEN-1:0] rs1_data; + logic rs1_data_valid; +} MUL_RS_t; // PMT and RDT reservation station struct -typedef struct packed { - logic [`ROB_DEPTH_WIDTH-1:0] rob_entry, - FUNCT6_u uop_funct6, - EXE_FUNCT3_e uop_funct3, +typedef struct packed { + logic [`ROB_DEPTH_WIDTH-1:0] rob_entry; + FUNCT6_u uop_funct6; + EXE_FUNCT3_e uop_funct3; // Identify vmerge and vmv in the same uop_funct6(6'b010111). - logic vm, + logic vm; // when vs1_data_valid=0, vs1 field is valid and used to decode some OPMVV uops // when vs1_data_valid=1, vs1_data is valid as a vector operand - VS1_u vs1, - logic [`VLEN-1:0] vs1_data, - EEW_e vs1_eew, - logic vs1_data_valid, - ELE_TYPE_t vs1_type, - logic [`VLEN-1:0] vs2_data, - EEW_e vs2_eew, - logic vs2_data_valid, - ELE_TYPE_t vs2_type, + VS1_u vs1; + logic [`VLEN-1:0] vs1_data; + EEW_e vs1_eew; + logic vs1_data_valid; + ELE_TYPE_t vs1_type; + logic [`VLEN-1:0] vs2_data; + EEW_e vs2_eew; + logic vs2_data_valid; + ELE_TYPE_t vs2_type; // rs1_data could be from X[rs1] and imm(insts[19:15]). If it is imm, the 5-bit imm(insts[19:15]) will be sign-extend to XLEN-bit. - logic [`XLEN-1:0] rs1_data, - logic rs1_data_valid, - logic last_uop_valid + logic [`XLEN-1:0] rs1_data; + logic rs1_data_valid; + logic last_uop_valid; } PMT_RDT_RS_t; // LSU reservation station struct -typedef struct packed { - logic [`PC_WIDTH-1:0] uop_pc, - logic [`ROB_DEPTH_WIDTH-1:0] uop_id, - LSU_TYPE_t uop_funct6, - - logic vidx_valid, - logic [`REGFILE_INDEX_WIDTH-1:0] vidx_addr, - logic [`VLEN-1:0] vidx_data, // vs2 - ELE_TYPE_t vs2_type, - logic vregfile_read_valid, - logic [`REGFILE_INDEX_WIDTH-1:0] vregfile_read_addr, - logic [`VLEN-1:0] vregfile_read_data // vs3 - ELE_TYPE_t vs3_type, -} LSU_RS_t; - -// -// EX stage, -// -// send ALU's result to ROB typedef struct packed { - logic [`ROB_DEPTH_WIDTH-1:0] rob_entry, - logic [`VLEN-1:0] w_data, // when w_type=XRF, w_data[`XLEN-1:0] will store the scalar result - W_DATA_TYPE_t w_type, - logic w_valid, - logic [`VCSR_VXSAT-1:0] vxsat, - logic ignore_vta_vma -} ALU2ROB_t; + logic [`PC_WIDTH-1:0] uop_pc; + logic [`ROB_DEPTH_WIDTH-1:0] uop_id; + LSU_TYPE_t uop_funct6; -// send uop to LSU -typedef struct packed { - // RVV send to uop_pc to help LSU match the vld/vst uop - logic [`PC_WIDTH-1:0] uop_pc, - // When LSU submit the result to RVV, LSU need to attend uop_id to help RVV retire the uop in ROB - logic [`ROB_DEPTH_WIDTH-1:0] uop_id, - // Vector regfile index interface for indexed vld/vst - logic vidx_valid, - logic [`REGFILE_INDEX_WIDTH-1:0] vidx_addr, - logic [`VLEN-1:0] vidx_data, // vs2 - ELE_TYPE_t vs2_type, // mask for vs2 - // Vector regfile read interface for vst - logic vregfile_read_valid, - logic [`REGFILE_INDEX_WIDTH-1:0] vregfile_read_addr, - logic [`VLEN-1:0] vregfile_read_data, // vs3 - ELE_TYPE_t vs3_type // mask for vs3 -} UOP_LSU_RVV2RVS_t; + logic vidx_valid; + logic [`REGFILE_INDEX_WIDTH-1:0] vidx_addr; + logic [`VLEN-1:0] vidx_data; // vs2 + ELE_TYPE_t vs2_type; + logic vregfile_read_valid; + logic [`REGFILE_INDEX_WIDTH-1:0] vregfile_read_addr; + logic [`VLEN-1:0] vregfile_read_data; // vs3 + ELE_TYPE_t vs3_type; +} LSU_RS_t; -// LSU feedback to RVV -typedef struct packed { - // When LSU submit the result to RVV, LSU need to attend uop_id to help RVV retire the uop in ROB - logic [`ROB_DEPTH_WIDTH-1:0] uop_id, - // LSU uop type - // When LSU complete the vstore uop, it need to tell RVV done signal and attend uop_id to help RVV retire the uops - // when load, it means the uop is vld. It enables vregfile_write_addr and vregfile_write_data, and submit the vector data to ROB - // when store, it means this store uop is done in LSU, ROB can retire this uop. - LSU_IS_STORE_e uop_type, - - // Vector regfile write interface for vld - logic [`REGFILE_INDEX_WIDTH-1:0] vregfile_write_addr, - logic [`VLEN-1:0] vregfile_write_data, // vd - ELE_TYPE_t vs1_type // mask for vd -} UOP_LSU_RVS2RVV_t; - +// +// EX stage, +// // ReOrder Buffer data struct -typedef enum logic [0] { +typedef enum logic { VRF, XRF } W_DATA_TYPE_t; +// send ALU's result to ROB typedef struct packed { - logic valid, // Total valid - logic [`REGFILE_INDEX_WIDTH-1:0] w_index, - logic [`VLEN-1:0] w_data, // when w_type=XRF, w_data[`XLEN-1:0] will store the scalar result - W_DATA_TYPE_t w_type, - logic w_valid, - ELE_TYPE_t vd_type, - VECTOR_CSR_t vector_csr, - logic ignore_vta_vma -} ROB_t; + logic [`ROB_DEPTH_WIDTH-1:0] rob_entry; + logic [`VLEN-1:0] w_data; // when w_type=XRF, w_data[`XLEN-1:0] will store the scalar result + W_DATA_TYPE_t w_type; + logic w_valid; + logic [`VCSR_VXSAT_WIDTH-1:0] vxsat; + logic ignore_vta_vma; +} ALU2ROB_t; + +// send uop to LSU +typedef struct packed { + // RVV send to uop_pc to help LSU match the vld/vst uop + logic [`PC_WIDTH-1:0] uop_pc; + // When LSU submit the result to RVV, LSU need to attend uop_id to help RVV retire the uop in ROB + logic [`ROB_DEPTH_WIDTH-1:0] uop_id; + // Vector regfile index interface for indexed vld/vst + logic vidx_valid; + logic [`REGFILE_INDEX_WIDTH-1:0] vidx_addr; + logic [`VLEN-1:0] vidx_data; // vs2 + ELE_TYPE_t vs2_type; // mask for vs2 + // Vector regfile read interface for vst + logic vregfile_read_valid; + logic [`REGFILE_INDEX_WIDTH-1:0] vregfile_read_addr; + logic [`VLEN-1:0] vregfile_read_data; // vs3 + ELE_TYPE_t vs3_type; // mask for vs3 +} UOP_LSU_RVV2RVS_t; + +// LSU feedback to RVV +typedef struct packed { + // When LSU submit the result to RVV, LSU need to attend uop_id to help RVV retire the uop in ROB + logic [`ROB_DEPTH_WIDTH-1:0] uop_id; + // LSU uop type + // When LSU complete the vstore uop, it need to tell RVV done signal and attend uop_id to help RVV retire the uops + // when load, it means the uop is vld. It enables vregfile_write_addr and vregfile_write_data, and submit the vector data to ROB + // when store, it means this store uop is done in LSU, ROB can retire this uop. + LSU_IS_STORE_e uop_type; + + // Vector regfile write interface for vld + logic [`REGFILE_INDEX_WIDTH-1:0] vregfile_write_addr; + logic [`VLEN-1:0] vregfile_write_data; // vd + ELE_TYPE_t vs1_type; // mask for vd +} UOP_LSU_RVS2RVV_t; + +typedef struct packed { + logic valid; // Total valid + logic [`REGFILE_INDEX_WIDTH-1:0] w_index; + logic [`VLEN-1:0] w_data; // when w_type=XRF, w_data[`XLEN-1:0] will store the scalar result + W_DATA_TYPE_t w_type; + logic w_valid; + ELE_TYPE_t vd_type; + VECTOR_CSR_t vector_csr; + logic ignore_vta_vma; +} ROB_t; // // WB stage, bypass and write back to VRF/XRF, trap handler // // write back to XRF typedef struct packed { - logic [`REGFILE_INDEX_WIDTH-1:0] w_index, - logic [`XLEN-1:0] w_data -} WB_XRF_t; + logic [`REGFILE_INDEX_WIDTH-1:0] w_index; + logic [`XLEN-1:0] w_data; +} WB_XRF_t; // write back to VRF typedef struct packed { - logic [`REGFILE_INDEX_WIDTH-1:0] w_index, - logic [`VLEN-1:0] w_data, - logic [`VLENB-1:0] w_strobe -} WB_VRF_t; + logic [`REGFILE_INDEX_WIDTH-1:0] w_index; + logic [`VLEN-1:0] w_data; + logic [`VLENB-1:0] w_strobe; +} WB_VRF_t; // trap handle -typedef enum logic [0] { - DECODE, // RVS find some illegal instructions when decoding, +typedef enum logic [1:0] { + TRAP_INFO_DECODE, // RVS find some illegal instructions when decoding, // which means a trap occurs to the instruction that is NOT executing in RVV. // So RVV will stop receiving new instructions from RVS, and complete all instructions in RVV. - LSU, // RVS find some illegal instructions when complete LSU transaction, like bus error, + TRAP_INFO_LSU, // RVS find some illegal instructions when complete LSU transaction, like bus error, // which means a trap occurs to the instruction that is executing in RVV. - // So RVV will top CQ to receive new instructions and flush Command Queue and Uops Queue, + // So RVV will top CQ to receive new instructions and flush Command Queue and Uops Queue, // and complete the instructions in EX, ME and WB stage. And RVS need to send rob_entry of that exception instruction. // After RVV retire all uops before that exception instruction, RVV response a ready signal for trap application. - LSU_FF // fault only first load, need to confirm whether has TLB or not. + TRAP_INFO_LSU_FF // fault only first load, need to confirm whether has TLB or not. } TRAP_INFO_e; typedef struct packed { - logic trap_apply, - TRAP_INFO_e trap_info, - logic [`ROB_DEPTH_WIDTH-1:0] trap_uop_rob_entry -} TRAP_t; + logic trap_apply; + TRAP_INFO_e trap_info; + logic [`ROB_DEPTH_WIDTH-1:0] trap_uop_rob_entry; +} TRAP_t; +`endif // HDL_VERILOG_RVV_DESIGN_RVV_SVH \ No newline at end of file
diff --git a/hdl/verilog/rvv/design/rvv_define.svh b/hdl/verilog/rvv/design/rvv_define.svh index be8d93b..0a2e79f 100755 --- a/hdl/verilog/rvv/design/rvv_define.svh +++ b/hdl/verilog/rvv/design/rvv_define.svh
@@ -1,3 +1,6 @@ +`ifndef HDL_VERILOG_RVV_DESIGN_RVV_DEFINE_SVH +`define HDL_VERILOG_RVV_DESIGN_RVV_DEFINE_SVH + // number of scalar core issue lane `define ISSUE_LANE 4 @@ -64,7 +67,7 @@ `define SEW16 3'b001 `define SEW32 3'b010 -// instruction opcode +// instruction opcode `define OPCODE_LOAD 2'b00 `define OPCODE_STORE 2'b01 `define OPCODE_ARITH 2'b00 @@ -72,21 +75,4 @@ // Reservation Station data width `define ALU_RS_WIDTH $bits(ALU_RS_t) - - - - - - - - - - - - - - - - - - +`endif // HDL_VERILOG_RVV_DESIGN_RVV_DEFINE_SVH