| commit | 118fe402685622520f5a54760776e8f5553abcc8 | [log] [tgz] |
|---|---|---|
| author | Derek Chow <derekjchow@google.com> | Tue Nov 26 12:47:14 2024 -0800 |
| committer | Derek Chow <derekjchow@google.com> | Tue Nov 26 13:11:50 2024 -0800 |
| tree | a10a41f63dc30f5f99f96f6b9f090baf6b0fd1cc | |
| parent | 919dfb5ef9dad644a23a2904ce55174219522fd4 [diff] |
Move Aligner and MultiFifo into design. Change-Id: I6e9e51d32fa5ef580d60886a8c5e608225b0f0de
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog