hw/top_earlgrey/data/top_earlgrey.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// TOP Earlgrey configuration
{ name: "earlgrey",
  type: "top",

  datawidth: "32",  # 32-bit datawidth

  clocks: [
    { name: "main", freq: "100000000" }
    { name: "fixed", freq: "100000000" }
    { name: "usb", freq: "48000000" }
  ]

  // Reset attributes
  // name: name of reset.
  // If type is "gen", then real name is `name`_rst_n
  // If type is "por", then real name is just `name`
  // The root type is temporary until rstmgr integration
  //
  // root: The parent reset.
  // If type is "por", there is no root, since it is the root
  //
  // clk:  related clock domain for synchronous release
  // If type is "por", there is not related clock, since it is
  // likely external or generated from a voltage comparator
  //
  resets: [
  // The rst_ni and por resets are relevant once rstmgr / pwrmgr are integrated
  //  { name: "rst_ni",     type: "por" }
  //  { name: "por",        type: "gen", root: "lc",  clk: "fixed" }
    { name: "lc",         type: "root", root: "lc",  clk: "fixed" }
    { name: "sys",        type: "root", root: "sys", clk: "main"  }
    { name: "sys_fixed",  type: "gen",  root: "sys", clk: "fixed" }
    { name: "spi_device", type: "gen",  root: "sys", clk: "fixed", sw: 1}
    { name: "usb",        type: "gen",  root: "sys", clk: "usb",   sw: 1}
  ]

  // Number of cores: used in rv_plic and timer
  num_cores: "1",

  // `module` defines the peripherals.
  // Details are coming from each modules' config file `ip.hjson`
  // TODO: Define parameter here
  module: [
    { name: "uart",     // instance name
      type: "uart",     // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
                        // and `hw/ip/{type}`

      // clock connections defines the port to top level clock connection
      // the ip.hjson will declare the clock port names
      // If none are defined at ip.hjson, clk_i is used by default
      clock_connections: {clk_i: "fixed"},

      // reset connections defines the port to top level reset connection
      // the ip.hjson will declare the reset port names
      // If none are defined at ip.hjson, rst_ni is used by default
      reset_connections: {rst_ni: "sys_fixed"},

      base_addr: "0x40000000",
    },
    { name: "gpio",
      type: "gpio",
      clock_connections: {clk_i: "fixed"},
      reset_connections: {rst_ni: "sys_fixed"},
      base_addr: "0x40010000",
    }

    { name: "spi_device",
      type: "spi_device",
      clock_connections: {clk_i: "fixed"},
      reset_connections: {rst_ni: "spi_device"},
      base_addr: "0x40020000",
    },
    { name: "flash_ctrl",
      type: "flash_ctrl",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "lc"},
      base_addr: "0x40030000",
    },
    { name: "rv_timer",
      type: "rv_timer",
      clock_connections: {clk_i: "fixed"},
      reset_connections: {rst_ni: "sys_fixed"},
      base_addr: "0x40080000",
    },
    { name: "aes",
      type: "aes",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40110000",
    },
    { name: "hmac",
      type: "hmac",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40120000",
    },
    { name: "rv_plic",
      type: "rv_plic",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40090000",
      generated: "true"         // Indicate this module is generated in the topgen
    }
    { name: "pinmux",
      type: "pinmux",
      clock: "main",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40070000",
      generated: "true"
    },
    { name: "alert_handler",
      type: "alert_handler",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40130000",
      generated: "true"         // Indicate this module is generated in the topgen
      localparam: {
        EscCntDw:  32,
        AccuCntDw: 16,
        LfsrSeed:  "0x7FFFFFFF"
      }
    }
    // dummy module to capture the alert handler escalation signals
    // and test them by converting them into IRQs
    { name: "nmi_gen",
      type: "nmi_gen",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "sys"},
      base_addr: "0x40140000",
    }
    { name: "usbdev",
      type: "usbdev",
      clock_connections: {clk_i: "fixed", clk_usb_48mhz_i: "usb"},
      reset_connections: {rst_ni: "sys_fixed", rst_usb_48mhz_ni: "usb"},
      base_addr: "0x40150000",
    },
  ]

  // Memories (ROM, RAM, eFlash) are defined at the top.
  // It utilizes the primitive cells but configurable
  memory: [
    { name: "rom",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "sys"},
      type: "rom",
      base_addr: "0x00008000",
      size: "0x4000"
    },
    { name: "ram_main",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "sys"},
      type: "ram_1p",
      base_addr: "0x10000000",
      size: "0x10000" },
    { name: "eflash",
      clock_connections: {clk_i: "main"},
      reset_connections: {rst_ni: "lc"},
      type: "eflash",
      base_addr: "0x20000000",
      size: "0x80000",
      inter_signal_list: [
        { struct: "flash",    // flash_req_t, flash_rsp_t
          type: "req_rsp",
          name: "flash_ctrl", // flash_ctrl_i (req), flash_ctrl_o (rsp)
          act:  "rsp",
        }
      ],
    },
  ],

  // Inter-module Connection.
  // format:
  //    requester: [ resp1, resp2, ... ],
  //
  //  the field and value should be module_inst.port_name
  //  e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl]
  inter_module: {
    'connect': {
      'flash_ctrl.flash': ['eflash.flash_ctrl']
    }

    // top is to connect to top net/struct.
    // It defines the signal in the top and connect from the module,
    // use of the signal is up to top template
    'top': [],

    // ext is to create port in the top.
    'ext': [],
  },

  debug_mem_base_addr: "0x1A110000",

  // Crossbars: having a top level crossbar
  // This version assumes all crossbars are instantiated at the top.
  // Assume xbar.hjson is located in the same directory of top.hjson
  xbar: [
    { name: "main",
      clock_connections: {clk_main_i: "main", clk_fixed_i: "fixed"},
      reset: "sys",
      reset_connections: {rst_main_ni: "sys", rst_fixed_ni: "sys_fixed"}
    },
    { name: "peri",
      clock_connections: {clk_peri_i: "fixed"},
      reset: "sys_fixed",
      reset_connections: {rst_peri_ni: "sys_fixed"},
    }
  ],

  // ===== INTERRUPT CTRL =====================================================
  // `rv_plic`  will be instantiate (need to be defined in `module` field
  // If interrupt is not defined, it uses the order from the module list
  // and include every modules.
  // first item goes to LSB of the interrupt source
  interrupt_module: ["gpio", "uart", "spi_device", "flash_ctrl",
                     "hmac", "alert_handler", "nmi_gen", "usbdev" ]

  // RV_PLIC has two searching algorithm internally to pick the most highest priority interrupt
  // source. "sequential" is smaller but slower, "matrix" is larger but faster.
  // Choose depends on the criteria. Currently it is set to "matrix" to meet FPGA timing @ 50MHz

  // generated:
  interrupt: [
  ]

  // ===== ALERT HANDLER ======================================================
  // list all modules that expose alerts
  // first item goes to LSB of the interrupt source
  alert_module: [ "hmac" ]

  // generated list of alerts:
  alert: [
  ]

  // TODO: PINMUX
  pinmux: {

    // Total number of Multiplexed I/O
    //  All the input/outputs from IPs are muxed in pinmux, and it has # of I/O
    //  talks to the outside of top_earlgrey.
    //  This field will be replaced to the length of PAD if padctrl is defined
    num_mio: 32

    // Dedicated IO modules. The in/out ports of the modules below are connected
    //  to TOP IO port through PADS directly. It bypasses PINMUX multiplexers
    dio_modules: [
      { name: "spi_device", pad: ["ChB[0..3]"] },
      //{ name: "uart.tx", pad: ["ChA[0]"]},
      { name: "uart", pad: ["ChA[0..1]"]},
      // { name: "dio_module.signal_input", pad: ["ChA[31]"] }
      { name: "usbdev", pad: ["ChC[0..7]"]},
    ],

    // Multiplexing IO modules. The in/out ports of the modules below are
    //  connected through PINMUX, which gives controllability of the connection
    //  between the modules and the IO PADS.
    //  If `mio_modules` aren't defined, it uses all remaining modules from
    //  module list except defined in `dio_modules`.
    mio_modules: ["uart", "gpio"]

    // If any module isn't defined in above two lists, its inputs will be tied
    //  to 0, and the output/OE signals will be floating (or connected to
    //  unused signal). `rv_plic` is special module, shouldn't be defined here.
    nc_modules: ["rv_timer", "hmac"]

    // Below fields are generated.
    // inputs: [
    //  { name: "xxx", width: xx },
    //  ]
    // outputs: [
    //  { name: "xxx", width: xx },
    //  ]
    // inouts: [
    //  { name: "xxx", width: xx },
    //  ]
  }

  // PADS instantiation
  //  Number of in/outs and the numer of PAD instances doesn't have to be
  //  same. The number given below excludes clock/reset and other necessary
  //  PADS but only defines GPIO pads.
  padctrl: {
    attr_default: ["STRONG"],
    pads: [
      { name: "ChA" type: "IO_33V", count: 32 }, // Accessing as ChA[0] .. ChA[31]
      { name: "ChB" type: "IO_33V", count: 4, attr: ["KEEP", "WEAK"]},
      { name: "ChC" type: "IO_33V", count: 4, attr: ["KEEP", "STRONG"]},
    ]
  }

}