[top] First draft of reset controller integration

- This PR does not implement the actual reset controller, but
  simply wires up the top level resets as if the controller existed
- The purpose of this PR is to get agreement on the general connectivity
  or reset nets and ports

hw/top_earlgrey/doc/top_earlgrey.hjson

diff --git a/hw/top_earlgrey/doc/top_earlgrey.hjson b/hw/top_earlgrey/doc/top_earlgrey.hjson
index 9a56d44..281455b 100644
--- a/hw/top_earlgrey/doc/top_earlgrey.hjson
+++ b/hw/top_earlgrey/doc/top_earlgrey.hjson
@@ -12,6 +12,17 @@
     { name: "main", freq: "100000000" }
   ]
 
+  // Reset attributes
+  // name: name of reset. Real name is `name`_rst_n
+  // type: reset type, either root or leaf
+  // root: if reset type not root, the root reset it is related to
+  // clk:  related clock domain for synchronous release
+  resets: [
+    { name: "lc", type: "root", clk: "main"}
+    { name: "sys", type: "root", clk: "main"}
+    { name: "spi_device", type: "leaf", root: "sys", clk: "main"}
+  ]
+
   // Number of cores: used in rv_plic and timer
   num_cores: "1",
 
@@ -22,39 +33,50 @@
     { name: "uart",     // instance name
       type: "uart",     // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted)
                         // and `hw/ip/{type}`
+
       clock: "main",    // `ip.hjson` clock is internal name, here top determines
                         // actual clock (signal matched at the top)
+
+      // reset connections defines the port to top level reset connection
+      // the ip.hjson will declare the reset port names
+      reset_connections: {rst_ni: "sys"},
       base_addr: "0x40000000",
     },
     { name: "gpio",
       type: "gpio",
       clock: "main",
+      reset_connections: {rst_ni: "sys"},
       base_addr: "0x40010000",
     }
 
     { name: "spi_device",
       type: "spi_device",
       clock: "main",
+      reset_connections: {rst_ni: "spi_device"},
       base_addr: "0x40020000",
     },
     { name: "flash_ctrl",
       type: "flash_ctrl",
       clock: "main",
+      reset_connections: {rst_ni: "lc"},
       base_addr: "0x40030000",
     },
     { name: "rv_timer",
       type: "rv_timer",
       clock: "main",
+      reset_connections: {rst_ni: "sys"},
       base_addr: "0x40080000",
     },
     { name: "hmac",
       type: "hmac",
       clock: "main",
+      reset_connections: {rst_ni: "sys"},
       base_addr: "0x40120000",
     },
     { name: "rv_plic",
       type: "rv_plic",
       clock: "main",
+      reset_connections: {rst_ni: "sys"},
       base_addr: "0x40090000",
       generated: "true"         // Indicate this module is generated in the topgen
       parameter: {
@@ -68,9 +90,9 @@
   // Memories (ROM, RAM, eFlash) are defined at the top.
   // It utilizes the primitive cells but configurable
   memory: [
-    { name: "rom",      type: "rom",    base_addr: "0x00008000", size: "0x2000"  },
-    { name: "ram_main", type: "ram_1p", base_addr: "0x10000000", size: "0x10000" },
-    { name: "eflash",   type: "eflash", base_addr: "0x20000000", size: "0x80000" },
+    { name: "rom",      reset_connections: {rst_ni: "sys"}, type: "rom",    base_addr: "0x00008000", size: "0x2000"  },
+    { name: "ram_main", reset_connections: {rst_ni: "sys"}, type: "ram_1p", base_addr: "0x10000000", size: "0x10000" },
+    { name: "eflash",   reset_connections: {rst_ni: "lc"},  type: "eflash", base_addr: "0x20000000", size: "0x80000" },
   ],
 
   debug_mem_base_addr: "0x1A110000",
@@ -81,6 +103,8 @@
   xbar: [
     { name: "main",
       clock: "main",    // Main clock, used in sockets
+      reset: "sys",
+      reset_connections: {rst_main_ni: "sys"}
     },
   ],