Rework usbdev I/O and top-level integration
This commit reworks the I/O of usbdev to enable automated top-level
integration using topgen:
- Every output gets a separte output-enable signal.
- All outputs are fed to the top-level hierarchy in
`top_earlgrey_asic/verilator...` and into the pad control, where they
might be used in the future.
- Also the differential data is fed to the pad control although it is
currently not used.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index b99152c..c5b1fd0 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -231,7 +231,7 @@
//{ name: "uart.tx", pad: ["ChA[0]"]},
{ name: "uart", pad: ["ChA[0..1]"]},
// { name: "dio_module.signal_input", pad: ["ChA[31]"] }
- { name: "usbdev", pad: ["ChC[0..3]"]},
+ { name: "usbdev", pad: ["ChC[0..7]"]},
],
// Multiplexing IO modules. The in/out ports of the modules below are
