[reggen] Make spacing uniform and simplify comments in reg_top
This is a minor "tidy-up" commit. The idea is that this commit makes
whitespace a bit more uniform, and simplifies the rules about what
comments get emitted. To review this patch, look at the changes to
reg_top.sv.tpl (which should hopefully be obviously right); the rest
of the diff is autogenerated.
The following commit will refactor the code in reg_top.sv.tpl itself.
This is less obviously correct, but *that* patch won't have any diffs
in the autogenerated code.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/ip/adc_ctrl/rtl/adc_ctrl_reg_top.sv b/hw/ip/adc_ctrl/rtl/adc_ctrl_reg_top.sv
index 40917f4..47354eb 100644
--- a/hw/ip/adc_ctrl/rtl/adc_ctrl_reg_top.sv
+++ b/hw/ip/adc_ctrl/rtl/adc_ctrl_reg_top.sv
@@ -399,8 +399,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
@@ -408,11 +408,11 @@
// from internal hardware
.de (hw2reg.intr_state.de),
- .d (hw2reg.intr_state.d ),
+ .d (hw2reg.intr_state.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.q ),
+ .q (reg2hw.intr_state.q),
// to register interface (read)
.qs (intr_state_qs)
@@ -426,8 +426,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
@@ -435,11 +435,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.q ),
+ .q (reg2hw.intr_enable.q),
// to register interface (read)
.qs (intr_enable_qs)
@@ -457,7 +457,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.qe),
- .q (reg2hw.intr_test.q ),
+ .q (reg2hw.intr_test.q),
.qs ()
);
@@ -470,8 +470,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_en_ctl_adc_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_en_ctl_adc_enable_we),
@@ -479,11 +479,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_en_ctl.adc_enable.q ),
+ .q (reg2hw.adc_en_ctl.adc_enable.q),
// to register interface (read)
.qs (adc_en_ctl_adc_enable_qs)
@@ -496,8 +496,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_en_ctl_oneshot_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_en_ctl_oneshot_mode_we),
@@ -505,11 +505,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_en_ctl.oneshot_mode.q ),
+ .q (reg2hw.adc_en_ctl.oneshot_mode.q),
// to register interface (read)
.qs (adc_en_ctl_oneshot_mode_qs)
@@ -524,8 +524,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_pd_ctl_lp_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_pd_ctl_lp_mode_we),
@@ -533,11 +533,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_pd_ctl.lp_mode.qe),
- .q (reg2hw.adc_pd_ctl.lp_mode.q ),
+ .q (reg2hw.adc_pd_ctl.lp_mode.q),
// to register interface (read)
.qs (adc_pd_ctl_lp_mode_qs)
@@ -550,8 +550,8 @@
.SWACCESS("RW"),
.RESVAL (4'h6)
) u_adc_pd_ctl_pwrup_time (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_pd_ctl_pwrup_time_we),
@@ -559,11 +559,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_pd_ctl.pwrup_time.qe),
- .q (reg2hw.adc_pd_ctl.pwrup_time.q ),
+ .q (reg2hw.adc_pd_ctl.pwrup_time.q),
// to register interface (read)
.qs (adc_pd_ctl_pwrup_time_qs)
@@ -576,8 +576,8 @@
.SWACCESS("RW"),
.RESVAL (24'h640)
) u_adc_pd_ctl_wakeup_time (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_pd_ctl_wakeup_time_we),
@@ -585,11 +585,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_pd_ctl.wakeup_time.qe),
- .q (reg2hw.adc_pd_ctl.wakeup_time.q ),
+ .q (reg2hw.adc_pd_ctl.wakeup_time.q),
// to register interface (read)
.qs (adc_pd_ctl_wakeup_time_qs)
@@ -603,8 +603,8 @@
.SWACCESS("RW"),
.RESVAL (8'h4)
) u_adc_lp_sample_ctl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_lp_sample_ctl_we),
@@ -612,11 +612,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_lp_sample_ctl.qe),
- .q (reg2hw.adc_lp_sample_ctl.q ),
+ .q (reg2hw.adc_lp_sample_ctl.q),
// to register interface (read)
.qs (adc_lp_sample_ctl_qs)
@@ -630,8 +630,8 @@
.SWACCESS("RW"),
.RESVAL (16'h9b)
) u_adc_sample_ctl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_sample_ctl_we),
@@ -639,11 +639,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_sample_ctl.qe),
- .q (reg2hw.adc_sample_ctl.q ),
+ .q (reg2hw.adc_sample_ctl.q),
// to register interface (read)
.qs (adc_sample_ctl_qs)
@@ -657,8 +657,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_fsm_rst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_fsm_rst_we),
@@ -666,11 +666,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_fsm_rst.q ),
+ .q (reg2hw.adc_fsm_rst.q),
// to register interface (read)
.qs (adc_fsm_rst_qs)
@@ -687,8 +687,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_0_min_v_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_0_min_v_0_we),
@@ -696,11 +696,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[0].min_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[0].min_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[0].min_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_0_min_v_0_qs)
@@ -713,8 +713,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn0_filter_ctl_0_cond_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_0_cond_0_we),
@@ -722,11 +722,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[0].cond.qe),
- .q (reg2hw.adc_chn0_filter_ctl[0].cond.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[0].cond.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_0_cond_0_qs)
@@ -739,8 +739,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_0_max_v_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_0_max_v_0_we),
@@ -748,11 +748,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[0].max_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[0].max_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[0].max_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_0_max_v_0_qs)
@@ -768,8 +768,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_1_min_v_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_1_min_v_1_we),
@@ -777,11 +777,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[1].min_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[1].min_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[1].min_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_1_min_v_1_qs)
@@ -794,8 +794,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn0_filter_ctl_1_cond_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_1_cond_1_we),
@@ -803,11 +803,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[1].cond.qe),
- .q (reg2hw.adc_chn0_filter_ctl[1].cond.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[1].cond.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_1_cond_1_qs)
@@ -820,8 +820,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_1_max_v_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_1_max_v_1_we),
@@ -829,11 +829,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[1].max_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[1].max_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[1].max_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_1_max_v_1_qs)
@@ -849,8 +849,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_2_min_v_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_2_min_v_2_we),
@@ -858,11 +858,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[2].min_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[2].min_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[2].min_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_2_min_v_2_qs)
@@ -875,8 +875,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn0_filter_ctl_2_cond_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_2_cond_2_we),
@@ -884,11 +884,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[2].cond.qe),
- .q (reg2hw.adc_chn0_filter_ctl[2].cond.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[2].cond.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_2_cond_2_qs)
@@ -901,8 +901,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_2_max_v_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_2_max_v_2_we),
@@ -910,11 +910,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[2].max_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[2].max_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[2].max_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_2_max_v_2_qs)
@@ -930,8 +930,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_3_min_v_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_3_min_v_3_we),
@@ -939,11 +939,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[3].min_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[3].min_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[3].min_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_3_min_v_3_qs)
@@ -956,8 +956,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn0_filter_ctl_3_cond_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_3_cond_3_we),
@@ -965,11 +965,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[3].cond.qe),
- .q (reg2hw.adc_chn0_filter_ctl[3].cond.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[3].cond.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_3_cond_3_qs)
@@ -982,8 +982,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_3_max_v_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_3_max_v_3_we),
@@ -991,11 +991,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[3].max_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[3].max_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[3].max_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_3_max_v_3_qs)
@@ -1011,8 +1011,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_4_min_v_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_4_min_v_4_we),
@@ -1020,11 +1020,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[4].min_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[4].min_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[4].min_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_4_min_v_4_qs)
@@ -1037,8 +1037,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn0_filter_ctl_4_cond_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_4_cond_4_we),
@@ -1046,11 +1046,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[4].cond.qe),
- .q (reg2hw.adc_chn0_filter_ctl[4].cond.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[4].cond.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_4_cond_4_qs)
@@ -1063,8 +1063,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_4_max_v_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_4_max_v_4_we),
@@ -1072,11 +1072,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[4].max_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[4].max_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[4].max_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_4_max_v_4_qs)
@@ -1092,8 +1092,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_5_min_v_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_5_min_v_5_we),
@@ -1101,11 +1101,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[5].min_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[5].min_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[5].min_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_5_min_v_5_qs)
@@ -1118,8 +1118,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn0_filter_ctl_5_cond_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_5_cond_5_we),
@@ -1127,11 +1127,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[5].cond.qe),
- .q (reg2hw.adc_chn0_filter_ctl[5].cond.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[5].cond.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_5_cond_5_qs)
@@ -1144,8 +1144,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_5_max_v_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_5_max_v_5_we),
@@ -1153,11 +1153,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[5].max_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[5].max_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[5].max_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_5_max_v_5_qs)
@@ -1173,8 +1173,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_6_min_v_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_6_min_v_6_we),
@@ -1182,11 +1182,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[6].min_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[6].min_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[6].min_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_6_min_v_6_qs)
@@ -1199,8 +1199,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn0_filter_ctl_6_cond_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_6_cond_6_we),
@@ -1208,11 +1208,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[6].cond.qe),
- .q (reg2hw.adc_chn0_filter_ctl[6].cond.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[6].cond.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_6_cond_6_qs)
@@ -1225,8 +1225,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_6_max_v_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_6_max_v_6_we),
@@ -1234,11 +1234,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[6].max_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[6].max_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[6].max_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_6_max_v_6_qs)
@@ -1254,8 +1254,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_7_min_v_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_7_min_v_7_we),
@@ -1263,11 +1263,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[7].min_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[7].min_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[7].min_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_7_min_v_7_qs)
@@ -1280,8 +1280,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn0_filter_ctl_7_cond_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_7_cond_7_we),
@@ -1289,11 +1289,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[7].cond.qe),
- .q (reg2hw.adc_chn0_filter_ctl[7].cond.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[7].cond.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_7_cond_7_qs)
@@ -1306,8 +1306,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn0_filter_ctl_7_max_v_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn0_filter_ctl_7_max_v_7_we),
@@ -1315,11 +1315,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn0_filter_ctl[7].max_v.qe),
- .q (reg2hw.adc_chn0_filter_ctl[7].max_v.q ),
+ .q (reg2hw.adc_chn0_filter_ctl[7].max_v.q),
// to register interface (read)
.qs (adc_chn0_filter_ctl_7_max_v_7_qs)
@@ -1337,8 +1337,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_0_min_v_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_0_min_v_0_we),
@@ -1346,11 +1346,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[0].min_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[0].min_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[0].min_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_0_min_v_0_qs)
@@ -1363,8 +1363,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn1_filter_ctl_0_cond_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_0_cond_0_we),
@@ -1372,11 +1372,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[0].cond.qe),
- .q (reg2hw.adc_chn1_filter_ctl[0].cond.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[0].cond.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_0_cond_0_qs)
@@ -1389,8 +1389,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_0_max_v_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_0_max_v_0_we),
@@ -1398,11 +1398,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[0].max_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[0].max_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[0].max_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_0_max_v_0_qs)
@@ -1418,8 +1418,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_1_min_v_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_1_min_v_1_we),
@@ -1427,11 +1427,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[1].min_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[1].min_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[1].min_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_1_min_v_1_qs)
@@ -1444,8 +1444,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn1_filter_ctl_1_cond_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_1_cond_1_we),
@@ -1453,11 +1453,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[1].cond.qe),
- .q (reg2hw.adc_chn1_filter_ctl[1].cond.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[1].cond.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_1_cond_1_qs)
@@ -1470,8 +1470,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_1_max_v_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_1_max_v_1_we),
@@ -1479,11 +1479,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[1].max_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[1].max_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[1].max_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_1_max_v_1_qs)
@@ -1499,8 +1499,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_2_min_v_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_2_min_v_2_we),
@@ -1508,11 +1508,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[2].min_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[2].min_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[2].min_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_2_min_v_2_qs)
@@ -1525,8 +1525,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn1_filter_ctl_2_cond_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_2_cond_2_we),
@@ -1534,11 +1534,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[2].cond.qe),
- .q (reg2hw.adc_chn1_filter_ctl[2].cond.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[2].cond.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_2_cond_2_qs)
@@ -1551,8 +1551,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_2_max_v_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_2_max_v_2_we),
@@ -1560,11 +1560,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[2].max_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[2].max_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[2].max_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_2_max_v_2_qs)
@@ -1580,8 +1580,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_3_min_v_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_3_min_v_3_we),
@@ -1589,11 +1589,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[3].min_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[3].min_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[3].min_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_3_min_v_3_qs)
@@ -1606,8 +1606,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn1_filter_ctl_3_cond_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_3_cond_3_we),
@@ -1615,11 +1615,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[3].cond.qe),
- .q (reg2hw.adc_chn1_filter_ctl[3].cond.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[3].cond.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_3_cond_3_qs)
@@ -1632,8 +1632,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_3_max_v_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_3_max_v_3_we),
@@ -1641,11 +1641,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[3].max_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[3].max_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[3].max_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_3_max_v_3_qs)
@@ -1661,8 +1661,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_4_min_v_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_4_min_v_4_we),
@@ -1670,11 +1670,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[4].min_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[4].min_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[4].min_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_4_min_v_4_qs)
@@ -1687,8 +1687,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn1_filter_ctl_4_cond_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_4_cond_4_we),
@@ -1696,11 +1696,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[4].cond.qe),
- .q (reg2hw.adc_chn1_filter_ctl[4].cond.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[4].cond.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_4_cond_4_qs)
@@ -1713,8 +1713,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_4_max_v_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_4_max_v_4_we),
@@ -1722,11 +1722,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[4].max_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[4].max_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[4].max_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_4_max_v_4_qs)
@@ -1742,8 +1742,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_5_min_v_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_5_min_v_5_we),
@@ -1751,11 +1751,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[5].min_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[5].min_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[5].min_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_5_min_v_5_qs)
@@ -1768,8 +1768,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn1_filter_ctl_5_cond_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_5_cond_5_we),
@@ -1777,11 +1777,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[5].cond.qe),
- .q (reg2hw.adc_chn1_filter_ctl[5].cond.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[5].cond.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_5_cond_5_qs)
@@ -1794,8 +1794,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_5_max_v_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_5_max_v_5_we),
@@ -1803,11 +1803,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[5].max_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[5].max_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[5].max_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_5_max_v_5_qs)
@@ -1823,8 +1823,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_6_min_v_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_6_min_v_6_we),
@@ -1832,11 +1832,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[6].min_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[6].min_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[6].min_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_6_min_v_6_qs)
@@ -1849,8 +1849,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn1_filter_ctl_6_cond_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_6_cond_6_we),
@@ -1858,11 +1858,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[6].cond.qe),
- .q (reg2hw.adc_chn1_filter_ctl[6].cond.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[6].cond.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_6_cond_6_qs)
@@ -1875,8 +1875,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_6_max_v_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_6_max_v_6_we),
@@ -1884,11 +1884,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[6].max_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[6].max_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[6].max_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_6_max_v_6_qs)
@@ -1904,8 +1904,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_7_min_v_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_7_min_v_7_we),
@@ -1913,11 +1913,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[7].min_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[7].min_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[7].min_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_7_min_v_7_qs)
@@ -1930,8 +1930,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_chn1_filter_ctl_7_cond_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_7_cond_7_we),
@@ -1939,11 +1939,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[7].cond.qe),
- .q (reg2hw.adc_chn1_filter_ctl[7].cond.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[7].cond.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_7_cond_7_qs)
@@ -1956,8 +1956,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_adc_chn1_filter_ctl_7_max_v_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_chn1_filter_ctl_7_max_v_7_we),
@@ -1965,11 +1965,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.adc_chn1_filter_ctl[7].max_v.qe),
- .q (reg2hw.adc_chn1_filter_ctl[7].max_v.q ),
+ .q (reg2hw.adc_chn1_filter_ctl[7].max_v.q),
// to register interface (read)
.qs (adc_chn1_filter_ctl_7_max_v_7_qs)
@@ -1987,15 +1987,16 @@
.SWACCESS("RO"),
.RESVAL (2'h0)
) u_adc_chn_val_0_adc_chn_value_ext_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.adc_chn_val[0].adc_chn_value_ext.de),
- .d (hw2reg.adc_chn_val[0].adc_chn_value_ext.d ),
+ .d (hw2reg.adc_chn_val[0].adc_chn_value_ext.d),
// to internal hardware
.qe (),
@@ -2012,15 +2013,16 @@
.SWACCESS("RO"),
.RESVAL (10'h0)
) u_adc_chn_val_0_adc_chn_value_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.adc_chn_val[0].adc_chn_value.de),
- .d (hw2reg.adc_chn_val[0].adc_chn_value.d ),
+ .d (hw2reg.adc_chn_val[0].adc_chn_value.d),
// to internal hardware
.qe (),
@@ -2037,15 +2039,16 @@
.SWACCESS("RO"),
.RESVAL (2'h0)
) u_adc_chn_val_0_adc_chn_value_intr_ext_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.adc_chn_val[0].adc_chn_value_intr_ext.de),
- .d (hw2reg.adc_chn_val[0].adc_chn_value_intr_ext.d ),
+ .d (hw2reg.adc_chn_val[0].adc_chn_value_intr_ext.d),
// to internal hardware
.qe (),
@@ -2062,15 +2065,16 @@
.SWACCESS("RO"),
.RESVAL (10'h0)
) u_adc_chn_val_0_adc_chn_value_intr_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.adc_chn_val[0].adc_chn_value_intr.de),
- .d (hw2reg.adc_chn_val[0].adc_chn_value_intr.d ),
+ .d (hw2reg.adc_chn_val[0].adc_chn_value_intr.d),
// to internal hardware
.qe (),
@@ -2090,15 +2094,16 @@
.SWACCESS("RO"),
.RESVAL (2'h0)
) u_adc_chn_val_1_adc_chn_value_ext_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.adc_chn_val[1].adc_chn_value_ext.de),
- .d (hw2reg.adc_chn_val[1].adc_chn_value_ext.d ),
+ .d (hw2reg.adc_chn_val[1].adc_chn_value_ext.d),
// to internal hardware
.qe (),
@@ -2115,15 +2120,16 @@
.SWACCESS("RO"),
.RESVAL (10'h0)
) u_adc_chn_val_1_adc_chn_value_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.adc_chn_val[1].adc_chn_value.de),
- .d (hw2reg.adc_chn_val[1].adc_chn_value.d ),
+ .d (hw2reg.adc_chn_val[1].adc_chn_value.d),
// to internal hardware
.qe (),
@@ -2140,15 +2146,16 @@
.SWACCESS("RO"),
.RESVAL (2'h0)
) u_adc_chn_val_1_adc_chn_value_intr_ext_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.adc_chn_val[1].adc_chn_value_intr_ext.de),
- .d (hw2reg.adc_chn_val[1].adc_chn_value_intr_ext.d ),
+ .d (hw2reg.adc_chn_val[1].adc_chn_value_intr_ext.d),
// to internal hardware
.qe (),
@@ -2165,15 +2172,16 @@
.SWACCESS("RO"),
.RESVAL (10'h0)
) u_adc_chn_val_1_adc_chn_value_intr_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.adc_chn_val[1].adc_chn_value_intr.de),
- .d (hw2reg.adc_chn_val[1].adc_chn_value_intr.d ),
+ .d (hw2reg.adc_chn_val[1].adc_chn_value_intr.d),
// to internal hardware
.qe (),
@@ -2193,8 +2201,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_wakeup_ctl_chn0_1_filter0_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_ctl_chn0_1_filter0_en_we),
@@ -2202,11 +2210,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_wakeup_ctl.chn0_1_filter0_en.q ),
+ .q (reg2hw.adc_wakeup_ctl.chn0_1_filter0_en.q),
// to register interface (read)
.qs (adc_wakeup_ctl_chn0_1_filter0_en_qs)
@@ -2219,8 +2227,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_wakeup_ctl_chn0_1_filter1_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_ctl_chn0_1_filter1_en_we),
@@ -2228,11 +2236,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_wakeup_ctl.chn0_1_filter1_en.q ),
+ .q (reg2hw.adc_wakeup_ctl.chn0_1_filter1_en.q),
// to register interface (read)
.qs (adc_wakeup_ctl_chn0_1_filter1_en_qs)
@@ -2245,8 +2253,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_wakeup_ctl_chn0_1_filter2_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_ctl_chn0_1_filter2_en_we),
@@ -2254,11 +2262,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_wakeup_ctl.chn0_1_filter2_en.q ),
+ .q (reg2hw.adc_wakeup_ctl.chn0_1_filter2_en.q),
// to register interface (read)
.qs (adc_wakeup_ctl_chn0_1_filter2_en_qs)
@@ -2271,8 +2279,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_wakeup_ctl_chn0_1_filter3_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_ctl_chn0_1_filter3_en_we),
@@ -2280,11 +2288,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_wakeup_ctl.chn0_1_filter3_en.q ),
+ .q (reg2hw.adc_wakeup_ctl.chn0_1_filter3_en.q),
// to register interface (read)
.qs (adc_wakeup_ctl_chn0_1_filter3_en_qs)
@@ -2297,8 +2305,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_wakeup_ctl_chn0_1_filter4_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_ctl_chn0_1_filter4_en_we),
@@ -2306,11 +2314,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_wakeup_ctl.chn0_1_filter4_en.q ),
+ .q (reg2hw.adc_wakeup_ctl.chn0_1_filter4_en.q),
// to register interface (read)
.qs (adc_wakeup_ctl_chn0_1_filter4_en_qs)
@@ -2323,8 +2331,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_wakeup_ctl_chn0_1_filter5_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_ctl_chn0_1_filter5_en_we),
@@ -2332,11 +2340,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_wakeup_ctl.chn0_1_filter5_en.q ),
+ .q (reg2hw.adc_wakeup_ctl.chn0_1_filter5_en.q),
// to register interface (read)
.qs (adc_wakeup_ctl_chn0_1_filter5_en_qs)
@@ -2349,8 +2357,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_wakeup_ctl_chn0_1_filter6_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_ctl_chn0_1_filter6_en_we),
@@ -2358,11 +2366,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_wakeup_ctl.chn0_1_filter6_en.q ),
+ .q (reg2hw.adc_wakeup_ctl.chn0_1_filter6_en.q),
// to register interface (read)
.qs (adc_wakeup_ctl_chn0_1_filter6_en_qs)
@@ -2375,8 +2383,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_wakeup_ctl_chn0_1_filter7_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_ctl_chn0_1_filter7_en_we),
@@ -2384,11 +2392,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_wakeup_ctl.chn0_1_filter7_en.q ),
+ .q (reg2hw.adc_wakeup_ctl.chn0_1_filter7_en.q),
// to register interface (read)
.qs (adc_wakeup_ctl_chn0_1_filter7_en_qs)
@@ -2403,8 +2411,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_wakeup_status_cc_sink_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_status_cc_sink_det_we),
@@ -2412,7 +2420,7 @@
// from internal hardware
.de (hw2reg.adc_wakeup_status.cc_sink_det.de),
- .d (hw2reg.adc_wakeup_status.cc_sink_det.d ),
+ .d (hw2reg.adc_wakeup_status.cc_sink_det.d),
// to internal hardware
.qe (),
@@ -2429,8 +2437,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_wakeup_status_cc_1a5_sink_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_status_cc_1a5_sink_det_we),
@@ -2438,7 +2446,7 @@
// from internal hardware
.de (hw2reg.adc_wakeup_status.cc_1a5_sink_det.de),
- .d (hw2reg.adc_wakeup_status.cc_1a5_sink_det.d ),
+ .d (hw2reg.adc_wakeup_status.cc_1a5_sink_det.d),
// to internal hardware
.qe (),
@@ -2455,8 +2463,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_wakeup_status_cc_3a0_sink_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_status_cc_3a0_sink_det_we),
@@ -2464,7 +2472,7 @@
// from internal hardware
.de (hw2reg.adc_wakeup_status.cc_3a0_sink_det.de),
- .d (hw2reg.adc_wakeup_status.cc_3a0_sink_det.d ),
+ .d (hw2reg.adc_wakeup_status.cc_3a0_sink_det.d),
// to internal hardware
.qe (),
@@ -2481,8 +2489,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_wakeup_status_cc_src_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_status_cc_src_det_we),
@@ -2490,7 +2498,7 @@
// from internal hardware
.de (hw2reg.adc_wakeup_status.cc_src_det.de),
- .d (hw2reg.adc_wakeup_status.cc_src_det.d ),
+ .d (hw2reg.adc_wakeup_status.cc_src_det.d),
// to internal hardware
.qe (),
@@ -2507,8 +2515,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_wakeup_status_cc_1a5_src_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_status_cc_1a5_src_det_we),
@@ -2516,7 +2524,7 @@
// from internal hardware
.de (hw2reg.adc_wakeup_status.cc_1a5_src_det.de),
- .d (hw2reg.adc_wakeup_status.cc_1a5_src_det.d ),
+ .d (hw2reg.adc_wakeup_status.cc_1a5_src_det.d),
// to internal hardware
.qe (),
@@ -2533,8 +2541,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_wakeup_status_cc_src_det_flip (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_status_cc_src_det_flip_we),
@@ -2542,7 +2550,7 @@
// from internal hardware
.de (hw2reg.adc_wakeup_status.cc_src_det_flip.de),
- .d (hw2reg.adc_wakeup_status.cc_src_det_flip.d ),
+ .d (hw2reg.adc_wakeup_status.cc_src_det_flip.d),
// to internal hardware
.qe (),
@@ -2559,8 +2567,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_wakeup_status_cc_1a5_src_det_flip (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_status_cc_1a5_src_det_flip_we),
@@ -2568,7 +2576,7 @@
// from internal hardware
.de (hw2reg.adc_wakeup_status.cc_1a5_src_det_flip.de),
- .d (hw2reg.adc_wakeup_status.cc_1a5_src_det_flip.d ),
+ .d (hw2reg.adc_wakeup_status.cc_1a5_src_det_flip.d),
// to internal hardware
.qe (),
@@ -2585,8 +2593,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_wakeup_status_cc_discon (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_wakeup_status_cc_discon_we),
@@ -2594,7 +2602,7 @@
// from internal hardware
.de (hw2reg.adc_wakeup_status.cc_discon.de),
- .d (hw2reg.adc_wakeup_status.cc_discon.d ),
+ .d (hw2reg.adc_wakeup_status.cc_discon.d),
// to internal hardware
.qe (),
@@ -2613,8 +2621,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_intr_ctl_chn0_1_filter0_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_ctl_chn0_1_filter0_en_we),
@@ -2622,11 +2630,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_intr_ctl.chn0_1_filter0_en.q ),
+ .q (reg2hw.adc_intr_ctl.chn0_1_filter0_en.q),
// to register interface (read)
.qs (adc_intr_ctl_chn0_1_filter0_en_qs)
@@ -2639,8 +2647,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_intr_ctl_chn0_1_filter1_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_ctl_chn0_1_filter1_en_we),
@@ -2648,11 +2656,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_intr_ctl.chn0_1_filter1_en.q ),
+ .q (reg2hw.adc_intr_ctl.chn0_1_filter1_en.q),
// to register interface (read)
.qs (adc_intr_ctl_chn0_1_filter1_en_qs)
@@ -2665,8 +2673,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_intr_ctl_chn0_1_filter2_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_ctl_chn0_1_filter2_en_we),
@@ -2674,11 +2682,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_intr_ctl.chn0_1_filter2_en.q ),
+ .q (reg2hw.adc_intr_ctl.chn0_1_filter2_en.q),
// to register interface (read)
.qs (adc_intr_ctl_chn0_1_filter2_en_qs)
@@ -2691,8 +2699,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_intr_ctl_chn0_1_filter3_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_ctl_chn0_1_filter3_en_we),
@@ -2700,11 +2708,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_intr_ctl.chn0_1_filter3_en.q ),
+ .q (reg2hw.adc_intr_ctl.chn0_1_filter3_en.q),
// to register interface (read)
.qs (adc_intr_ctl_chn0_1_filter3_en_qs)
@@ -2717,8 +2725,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_intr_ctl_chn0_1_filter4_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_ctl_chn0_1_filter4_en_we),
@@ -2726,11 +2734,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_intr_ctl.chn0_1_filter4_en.q ),
+ .q (reg2hw.adc_intr_ctl.chn0_1_filter4_en.q),
// to register interface (read)
.qs (adc_intr_ctl_chn0_1_filter4_en_qs)
@@ -2743,8 +2751,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_intr_ctl_chn0_1_filter5_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_ctl_chn0_1_filter5_en_we),
@@ -2752,11 +2760,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_intr_ctl.chn0_1_filter5_en.q ),
+ .q (reg2hw.adc_intr_ctl.chn0_1_filter5_en.q),
// to register interface (read)
.qs (adc_intr_ctl_chn0_1_filter5_en_qs)
@@ -2769,8 +2777,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_intr_ctl_chn0_1_filter6_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_ctl_chn0_1_filter6_en_we),
@@ -2778,11 +2786,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_intr_ctl.chn0_1_filter6_en.q ),
+ .q (reg2hw.adc_intr_ctl.chn0_1_filter6_en.q),
// to register interface (read)
.qs (adc_intr_ctl_chn0_1_filter6_en_qs)
@@ -2795,8 +2803,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_intr_ctl_chn0_1_filter7_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_ctl_chn0_1_filter7_en_we),
@@ -2804,11 +2812,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_intr_ctl.chn0_1_filter7_en.q ),
+ .q (reg2hw.adc_intr_ctl.chn0_1_filter7_en.q),
// to register interface (read)
.qs (adc_intr_ctl_chn0_1_filter7_en_qs)
@@ -2821,8 +2829,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_adc_intr_ctl_oneshot_intr_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_ctl_oneshot_intr_en_we),
@@ -2830,11 +2838,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.adc_intr_ctl.oneshot_intr_en.q ),
+ .q (reg2hw.adc_intr_ctl.oneshot_intr_en.q),
// to register interface (read)
.qs (adc_intr_ctl_oneshot_intr_en_qs)
@@ -2849,8 +2857,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_intr_status_cc_sink_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_status_cc_sink_det_we),
@@ -2858,7 +2866,7 @@
// from internal hardware
.de (hw2reg.adc_intr_status.cc_sink_det.de),
- .d (hw2reg.adc_intr_status.cc_sink_det.d ),
+ .d (hw2reg.adc_intr_status.cc_sink_det.d),
// to internal hardware
.qe (),
@@ -2875,8 +2883,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_intr_status_cc_1a5_sink_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_status_cc_1a5_sink_det_we),
@@ -2884,7 +2892,7 @@
// from internal hardware
.de (hw2reg.adc_intr_status.cc_1a5_sink_det.de),
- .d (hw2reg.adc_intr_status.cc_1a5_sink_det.d ),
+ .d (hw2reg.adc_intr_status.cc_1a5_sink_det.d),
// to internal hardware
.qe (),
@@ -2901,8 +2909,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_intr_status_cc_3a0_sink_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_status_cc_3a0_sink_det_we),
@@ -2910,7 +2918,7 @@
// from internal hardware
.de (hw2reg.adc_intr_status.cc_3a0_sink_det.de),
- .d (hw2reg.adc_intr_status.cc_3a0_sink_det.d ),
+ .d (hw2reg.adc_intr_status.cc_3a0_sink_det.d),
// to internal hardware
.qe (),
@@ -2927,8 +2935,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_intr_status_cc_src_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_status_cc_src_det_we),
@@ -2936,7 +2944,7 @@
// from internal hardware
.de (hw2reg.adc_intr_status.cc_src_det.de),
- .d (hw2reg.adc_intr_status.cc_src_det.d ),
+ .d (hw2reg.adc_intr_status.cc_src_det.d),
// to internal hardware
.qe (),
@@ -2953,8 +2961,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_intr_status_cc_1a5_src_det (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_status_cc_1a5_src_det_we),
@@ -2962,7 +2970,7 @@
// from internal hardware
.de (hw2reg.adc_intr_status.cc_1a5_src_det.de),
- .d (hw2reg.adc_intr_status.cc_1a5_src_det.d ),
+ .d (hw2reg.adc_intr_status.cc_1a5_src_det.d),
// to internal hardware
.qe (),
@@ -2979,8 +2987,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_intr_status_cc_src_det_flip (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_status_cc_src_det_flip_we),
@@ -2988,7 +2996,7 @@
// from internal hardware
.de (hw2reg.adc_intr_status.cc_src_det_flip.de),
- .d (hw2reg.adc_intr_status.cc_src_det_flip.d ),
+ .d (hw2reg.adc_intr_status.cc_src_det_flip.d),
// to internal hardware
.qe (),
@@ -3005,8 +3013,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_intr_status_cc_1a5_src_det_flip (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_status_cc_1a5_src_det_flip_we),
@@ -3014,7 +3022,7 @@
// from internal hardware
.de (hw2reg.adc_intr_status.cc_1a5_src_det_flip.de),
- .d (hw2reg.adc_intr_status.cc_1a5_src_det_flip.d ),
+ .d (hw2reg.adc_intr_status.cc_1a5_src_det_flip.d),
// to internal hardware
.qe (),
@@ -3031,8 +3039,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_intr_status_cc_discon (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_status_cc_discon_we),
@@ -3040,7 +3048,7 @@
// from internal hardware
.de (hw2reg.adc_intr_status.cc_discon.de),
- .d (hw2reg.adc_intr_status.cc_discon.d ),
+ .d (hw2reg.adc_intr_status.cc_discon.d),
// to internal hardware
.qe (),
@@ -3057,8 +3065,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_adc_intr_status_oneshot (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (adc_intr_status_oneshot_we),
@@ -3066,7 +3074,7 @@
// from internal hardware
.de (hw2reg.adc_intr_status.oneshot.de),
- .d (hw2reg.adc_intr_status.oneshot.d ),
+ .d (hw2reg.adc_intr_status.oneshot.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/aes/rtl/aes_reg_top.sv b/hw/ip/aes/rtl/aes_reg_top.sv
index e3d1c9c..a2702d5 100644
--- a/hw/ip/aes/rtl/aes_reg_top.sv
+++ b/hw/ip/aes/rtl/aes_reg_top.sv
@@ -213,7 +213,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_ctrl_update_err.qe),
- .q (reg2hw.alert_test.recov_ctrl_update_err.q ),
+ .q (reg2hw.alert_test.recov_ctrl_update_err.q),
.qs ()
);
@@ -228,7 +228,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_fault.qe),
- .q (reg2hw.alert_test.fatal_fault.q ),
+ .q (reg2hw.alert_test.fatal_fault.q),
.qs ()
);
@@ -246,7 +246,7 @@
.d (hw2reg.key_share0[0].d),
.qre (),
.qe (reg2hw.key_share0[0].qe),
- .q (reg2hw.key_share0[0].q ),
+ .q (reg2hw.key_share0[0].q),
.qs ()
);
@@ -262,7 +262,7 @@
.d (hw2reg.key_share0[1].d),
.qre (),
.qe (reg2hw.key_share0[1].qe),
- .q (reg2hw.key_share0[1].q ),
+ .q (reg2hw.key_share0[1].q),
.qs ()
);
@@ -278,7 +278,7 @@
.d (hw2reg.key_share0[2].d),
.qre (),
.qe (reg2hw.key_share0[2].qe),
- .q (reg2hw.key_share0[2].q ),
+ .q (reg2hw.key_share0[2].q),
.qs ()
);
@@ -294,7 +294,7 @@
.d (hw2reg.key_share0[3].d),
.qre (),
.qe (reg2hw.key_share0[3].qe),
- .q (reg2hw.key_share0[3].q ),
+ .q (reg2hw.key_share0[3].q),
.qs ()
);
@@ -310,7 +310,7 @@
.d (hw2reg.key_share0[4].d),
.qre (),
.qe (reg2hw.key_share0[4].qe),
- .q (reg2hw.key_share0[4].q ),
+ .q (reg2hw.key_share0[4].q),
.qs ()
);
@@ -326,7 +326,7 @@
.d (hw2reg.key_share0[5].d),
.qre (),
.qe (reg2hw.key_share0[5].qe),
- .q (reg2hw.key_share0[5].q ),
+ .q (reg2hw.key_share0[5].q),
.qs ()
);
@@ -342,7 +342,7 @@
.d (hw2reg.key_share0[6].d),
.qre (),
.qe (reg2hw.key_share0[6].qe),
- .q (reg2hw.key_share0[6].q ),
+ .q (reg2hw.key_share0[6].q),
.qs ()
);
@@ -358,7 +358,7 @@
.d (hw2reg.key_share0[7].d),
.qre (),
.qe (reg2hw.key_share0[7].qe),
- .q (reg2hw.key_share0[7].q ),
+ .q (reg2hw.key_share0[7].q),
.qs ()
);
@@ -376,7 +376,7 @@
.d (hw2reg.key_share1[0].d),
.qre (),
.qe (reg2hw.key_share1[0].qe),
- .q (reg2hw.key_share1[0].q ),
+ .q (reg2hw.key_share1[0].q),
.qs ()
);
@@ -392,7 +392,7 @@
.d (hw2reg.key_share1[1].d),
.qre (),
.qe (reg2hw.key_share1[1].qe),
- .q (reg2hw.key_share1[1].q ),
+ .q (reg2hw.key_share1[1].q),
.qs ()
);
@@ -408,7 +408,7 @@
.d (hw2reg.key_share1[2].d),
.qre (),
.qe (reg2hw.key_share1[2].qe),
- .q (reg2hw.key_share1[2].q ),
+ .q (reg2hw.key_share1[2].q),
.qs ()
);
@@ -424,7 +424,7 @@
.d (hw2reg.key_share1[3].d),
.qre (),
.qe (reg2hw.key_share1[3].qe),
- .q (reg2hw.key_share1[3].q ),
+ .q (reg2hw.key_share1[3].q),
.qs ()
);
@@ -440,7 +440,7 @@
.d (hw2reg.key_share1[4].d),
.qre (),
.qe (reg2hw.key_share1[4].qe),
- .q (reg2hw.key_share1[4].q ),
+ .q (reg2hw.key_share1[4].q),
.qs ()
);
@@ -456,7 +456,7 @@
.d (hw2reg.key_share1[5].d),
.qre (),
.qe (reg2hw.key_share1[5].qe),
- .q (reg2hw.key_share1[5].q ),
+ .q (reg2hw.key_share1[5].q),
.qs ()
);
@@ -472,7 +472,7 @@
.d (hw2reg.key_share1[6].d),
.qre (),
.qe (reg2hw.key_share1[6].qe),
- .q (reg2hw.key_share1[6].q ),
+ .q (reg2hw.key_share1[6].q),
.qs ()
);
@@ -488,7 +488,7 @@
.d (hw2reg.key_share1[7].d),
.qre (),
.qe (reg2hw.key_share1[7].qe),
- .q (reg2hw.key_share1[7].q ),
+ .q (reg2hw.key_share1[7].q),
.qs ()
);
@@ -506,7 +506,7 @@
.d (hw2reg.iv[0].d),
.qre (),
.qe (reg2hw.iv[0].qe),
- .q (reg2hw.iv[0].q ),
+ .q (reg2hw.iv[0].q),
.qs ()
);
@@ -522,7 +522,7 @@
.d (hw2reg.iv[1].d),
.qre (),
.qe (reg2hw.iv[1].qe),
- .q (reg2hw.iv[1].q ),
+ .q (reg2hw.iv[1].q),
.qs ()
);
@@ -538,7 +538,7 @@
.d (hw2reg.iv[2].d),
.qre (),
.qe (reg2hw.iv[2].qe),
- .q (reg2hw.iv[2].q ),
+ .q (reg2hw.iv[2].q),
.qs ()
);
@@ -554,7 +554,7 @@
.d (hw2reg.iv[3].d),
.qre (),
.qe (reg2hw.iv[3].qe),
- .q (reg2hw.iv[3].q ),
+ .q (reg2hw.iv[3].q),
.qs ()
);
@@ -568,8 +568,8 @@
.SWACCESS("WO"),
.RESVAL (32'h0)
) u_data_in_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_in_0_we),
@@ -577,12 +577,13 @@
// from internal hardware
.de (hw2reg.data_in[0].de),
- .d (hw2reg.data_in[0].d ),
+ .d (hw2reg.data_in[0].d),
// to internal hardware
.qe (reg2hw.data_in[0].qe),
- .q (reg2hw.data_in[0].q ),
+ .q (reg2hw.data_in[0].q),
+ // to register interface (read)
.qs ()
);
@@ -594,8 +595,8 @@
.SWACCESS("WO"),
.RESVAL (32'h0)
) u_data_in_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_in_1_we),
@@ -603,12 +604,13 @@
// from internal hardware
.de (hw2reg.data_in[1].de),
- .d (hw2reg.data_in[1].d ),
+ .d (hw2reg.data_in[1].d),
// to internal hardware
.qe (reg2hw.data_in[1].qe),
- .q (reg2hw.data_in[1].q ),
+ .q (reg2hw.data_in[1].q),
+ // to register interface (read)
.qs ()
);
@@ -620,8 +622,8 @@
.SWACCESS("WO"),
.RESVAL (32'h0)
) u_data_in_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_in_2_we),
@@ -629,12 +631,13 @@
// from internal hardware
.de (hw2reg.data_in[2].de),
- .d (hw2reg.data_in[2].d ),
+ .d (hw2reg.data_in[2].d),
// to internal hardware
.qe (reg2hw.data_in[2].qe),
- .q (reg2hw.data_in[2].q ),
+ .q (reg2hw.data_in[2].q),
+ // to register interface (read)
.qs ()
);
@@ -646,8 +649,8 @@
.SWACCESS("WO"),
.RESVAL (32'h0)
) u_data_in_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_in_3_we),
@@ -655,12 +658,13 @@
// from internal hardware
.de (hw2reg.data_in[3].de),
- .d (hw2reg.data_in[3].d ),
+ .d (hw2reg.data_in[3].d),
// to internal hardware
.qe (reg2hw.data_in[3].qe),
- .q (reg2hw.data_in[3].q ),
+ .q (reg2hw.data_in[3].q),
+ // to register interface (read)
.qs ()
);
@@ -678,7 +682,7 @@
.d (hw2reg.data_out[0].d),
.qre (reg2hw.data_out[0].re),
.qe (),
- .q (reg2hw.data_out[0].q ),
+ .q (reg2hw.data_out[0].q),
.qs (data_out_0_qs)
);
@@ -694,7 +698,7 @@
.d (hw2reg.data_out[1].d),
.qre (reg2hw.data_out[1].re),
.qe (),
- .q (reg2hw.data_out[1].q ),
+ .q (reg2hw.data_out[1].q),
.qs (data_out_1_qs)
);
@@ -710,7 +714,7 @@
.d (hw2reg.data_out[2].d),
.qre (reg2hw.data_out[2].re),
.qe (),
- .q (reg2hw.data_out[2].q ),
+ .q (reg2hw.data_out[2].q),
.qs (data_out_2_qs)
);
@@ -726,7 +730,7 @@
.d (hw2reg.data_out[3].d),
.qre (reg2hw.data_out[3].re),
.qe (),
- .q (reg2hw.data_out[3].q ),
+ .q (reg2hw.data_out[3].q),
.qs (data_out_3_qs)
);
@@ -743,7 +747,7 @@
.d (hw2reg.ctrl_shadowed.operation.d),
.qre (reg2hw.ctrl_shadowed.operation.re),
.qe (reg2hw.ctrl_shadowed.operation.qe),
- .q (reg2hw.ctrl_shadowed.operation.q ),
+ .q (reg2hw.ctrl_shadowed.operation.q),
.qs (ctrl_shadowed_operation_qs)
);
@@ -758,7 +762,7 @@
.d (hw2reg.ctrl_shadowed.mode.d),
.qre (reg2hw.ctrl_shadowed.mode.re),
.qe (reg2hw.ctrl_shadowed.mode.qe),
- .q (reg2hw.ctrl_shadowed.mode.q ),
+ .q (reg2hw.ctrl_shadowed.mode.q),
.qs (ctrl_shadowed_mode_qs)
);
@@ -773,7 +777,7 @@
.d (hw2reg.ctrl_shadowed.key_len.d),
.qre (reg2hw.ctrl_shadowed.key_len.re),
.qe (reg2hw.ctrl_shadowed.key_len.qe),
- .q (reg2hw.ctrl_shadowed.key_len.q ),
+ .q (reg2hw.ctrl_shadowed.key_len.q),
.qs (ctrl_shadowed_key_len_qs)
);
@@ -788,7 +792,7 @@
.d (hw2reg.ctrl_shadowed.manual_operation.d),
.qre (reg2hw.ctrl_shadowed.manual_operation.re),
.qe (reg2hw.ctrl_shadowed.manual_operation.qe),
- .q (reg2hw.ctrl_shadowed.manual_operation.q ),
+ .q (reg2hw.ctrl_shadowed.manual_operation.q),
.qs (ctrl_shadowed_manual_operation_qs)
);
@@ -803,7 +807,7 @@
.d (hw2reg.ctrl_shadowed.force_zero_masks.d),
.qre (reg2hw.ctrl_shadowed.force_zero_masks.re),
.qe (reg2hw.ctrl_shadowed.force_zero_masks.qe),
- .q (reg2hw.ctrl_shadowed.force_zero_masks.q ),
+ .q (reg2hw.ctrl_shadowed.force_zero_masks.q),
.qs (ctrl_shadowed_force_zero_masks_qs)
);
@@ -816,8 +820,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_trigger_start (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (trigger_start_we),
@@ -825,12 +829,13 @@
// from internal hardware
.de (hw2reg.trigger.start.de),
- .d (hw2reg.trigger.start.d ),
+ .d (hw2reg.trigger.start.d),
// to internal hardware
.qe (),
- .q (reg2hw.trigger.start.q ),
+ .q (reg2hw.trigger.start.q),
+ // to register interface (read)
.qs ()
);
@@ -841,8 +846,8 @@
.SWACCESS("WO"),
.RESVAL (1'h1)
) u_trigger_key_iv_data_in_clear (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (trigger_key_iv_data_in_clear_we),
@@ -850,12 +855,13 @@
// from internal hardware
.de (hw2reg.trigger.key_iv_data_in_clear.de),
- .d (hw2reg.trigger.key_iv_data_in_clear.d ),
+ .d (hw2reg.trigger.key_iv_data_in_clear.d),
// to internal hardware
.qe (),
- .q (reg2hw.trigger.key_iv_data_in_clear.q ),
+ .q (reg2hw.trigger.key_iv_data_in_clear.q),
+ // to register interface (read)
.qs ()
);
@@ -866,8 +872,8 @@
.SWACCESS("WO"),
.RESVAL (1'h1)
) u_trigger_data_out_clear (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (trigger_data_out_clear_we),
@@ -875,12 +881,13 @@
// from internal hardware
.de (hw2reg.trigger.data_out_clear.de),
- .d (hw2reg.trigger.data_out_clear.d ),
+ .d (hw2reg.trigger.data_out_clear.d),
// to internal hardware
.qe (),
- .q (reg2hw.trigger.data_out_clear.q ),
+ .q (reg2hw.trigger.data_out_clear.q),
+ // to register interface (read)
.qs ()
);
@@ -891,8 +898,8 @@
.SWACCESS("WO"),
.RESVAL (1'h1)
) u_trigger_prng_reseed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (trigger_prng_reseed_we),
@@ -900,12 +907,13 @@
// from internal hardware
.de (hw2reg.trigger.prng_reseed.de),
- .d (hw2reg.trigger.prng_reseed.d ),
+ .d (hw2reg.trigger.prng_reseed.d),
// to internal hardware
.qe (),
- .q (reg2hw.trigger.prng_reseed.q ),
+ .q (reg2hw.trigger.prng_reseed.q),
+ // to register interface (read)
.qs ()
);
@@ -918,15 +926,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_idle (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.idle.de),
- .d (hw2reg.status.idle.d ),
+ .d (hw2reg.status.idle.d),
// to internal hardware
.qe (),
@@ -943,15 +952,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_stall (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.stall.de),
- .d (hw2reg.status.stall.d ),
+ .d (hw2reg.status.stall.d),
// to internal hardware
.qe (),
@@ -968,19 +978,20 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_output_lost (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.output_lost.de),
- .d (hw2reg.status.output_lost.d ),
+ .d (hw2reg.status.output_lost.d),
// to internal hardware
.qe (),
- .q (reg2hw.status.output_lost.q ),
+ .q (reg2hw.status.output_lost.q),
// to register interface (read)
.qs (status_output_lost_qs)
@@ -993,15 +1004,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_output_valid (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.output_valid.de),
- .d (hw2reg.status.output_valid.d ),
+ .d (hw2reg.status.output_valid.d),
// to internal hardware
.qe (),
@@ -1018,15 +1030,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_input_ready (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.input_ready.de),
- .d (hw2reg.status.input_ready.d ),
+ .d (hw2reg.status.input_ready.d),
// to internal hardware
.qe (),
@@ -1043,15 +1056,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_alert_recov_ctrl_update_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.alert_recov_ctrl_update_err.de),
- .d (hw2reg.status.alert_recov_ctrl_update_err.d ),
+ .d (hw2reg.status.alert_recov_ctrl_update_err.d),
// to internal hardware
.qe (),
@@ -1068,15 +1082,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_alert_fatal_fault (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.alert_fatal_fault.de),
- .d (hw2reg.status.alert_fatal_fault.d ),
+ .d (hw2reg.status.alert_fatal_fault.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv b/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv
index 2b51de1..8c8360c 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv
@@ -499,8 +499,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_classa (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_classa_we),
@@ -508,11 +508,11 @@
// from internal hardware
.de (hw2reg.intr_state.classa.de),
- .d (hw2reg.intr_state.classa.d ),
+ .d (hw2reg.intr_state.classa.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.classa.q ),
+ .q (reg2hw.intr_state.classa.q),
// to register interface (read)
.qs (intr_state_classa_qs)
@@ -525,8 +525,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_classb (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_classb_we),
@@ -534,11 +534,11 @@
// from internal hardware
.de (hw2reg.intr_state.classb.de),
- .d (hw2reg.intr_state.classb.d ),
+ .d (hw2reg.intr_state.classb.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.classb.q ),
+ .q (reg2hw.intr_state.classb.q),
// to register interface (read)
.qs (intr_state_classb_qs)
@@ -551,8 +551,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_classc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_classc_we),
@@ -560,11 +560,11 @@
// from internal hardware
.de (hw2reg.intr_state.classc.de),
- .d (hw2reg.intr_state.classc.d ),
+ .d (hw2reg.intr_state.classc.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.classc.q ),
+ .q (reg2hw.intr_state.classc.q),
// to register interface (read)
.qs (intr_state_classc_qs)
@@ -577,8 +577,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_classd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_classd_we),
@@ -586,11 +586,11 @@
// from internal hardware
.de (hw2reg.intr_state.classd.de),
- .d (hw2reg.intr_state.classd.d ),
+ .d (hw2reg.intr_state.classd.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.classd.q ),
+ .q (reg2hw.intr_state.classd.q),
// to register interface (read)
.qs (intr_state_classd_qs)
@@ -605,8 +605,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_classa (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_classa_we),
@@ -614,11 +614,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.classa.q ),
+ .q (reg2hw.intr_enable.classa.q),
// to register interface (read)
.qs (intr_enable_classa_qs)
@@ -631,8 +631,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_classb (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_classb_we),
@@ -640,11 +640,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.classb.q ),
+ .q (reg2hw.intr_enable.classb.q),
// to register interface (read)
.qs (intr_enable_classb_qs)
@@ -657,8 +657,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_classc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_classc_we),
@@ -666,11 +666,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.classc.q ),
+ .q (reg2hw.intr_enable.classc.q),
// to register interface (read)
.qs (intr_enable_classc_qs)
@@ -683,8 +683,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_classd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_classd_we),
@@ -692,11 +692,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.classd.q ),
+ .q (reg2hw.intr_enable.classd.q),
// to register interface (read)
.qs (intr_enable_classd_qs)
@@ -715,7 +715,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.classa.qe),
- .q (reg2hw.intr_test.classa.q ),
+ .q (reg2hw.intr_test.classa.q),
.qs ()
);
@@ -730,7 +730,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.classb.qe),
- .q (reg2hw.intr_test.classb.q ),
+ .q (reg2hw.intr_test.classb.q),
.qs ()
);
@@ -745,7 +745,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.classc.qe),
- .q (reg2hw.intr_test.classc.q ),
+ .q (reg2hw.intr_test.classc.q),
.qs ()
);
@@ -760,7 +760,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.classd.qe),
- .q (reg2hw.intr_test.classd.q ),
+ .q (reg2hw.intr_test.classd.q),
.qs ()
);
@@ -772,8 +772,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_ping_timer_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ping_timer_regwen_we),
@@ -781,7 +781,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -799,20 +799,20 @@
.SWACCESS("RW"),
.RESVAL (24'h20)
) u_ping_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ping_timeout_cyc_we & ping_timer_regwen_qs),
.wd (ping_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ping_timeout_cyc.q ),
+ .q (reg2hw.ping_timeout_cyc.q),
// to register interface (read)
.qs (ping_timeout_cyc_qs)
@@ -826,20 +826,20 @@
.SWACCESS("W1S"),
.RESVAL (1'h0)
) u_ping_timer_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ping_timer_en_we & ping_timer_regwen_qs),
.wd (ping_timer_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ping_timer_en.q ),
+ .q (reg2hw.ping_timer_en.q),
// to register interface (read)
.qs (ping_timer_en_qs)
@@ -855,8 +855,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_0_we),
@@ -864,11 +864,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[0].q ),
+ .q (reg2hw.alert_regwen[0].q),
// to register interface (read)
.qs (alert_regwen_0_qs)
@@ -882,8 +882,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_1_we),
@@ -891,11 +891,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[1].q ),
+ .q (reg2hw.alert_regwen[1].q),
// to register interface (read)
.qs (alert_regwen_1_qs)
@@ -909,8 +909,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_2_we),
@@ -918,11 +918,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[2].q ),
+ .q (reg2hw.alert_regwen[2].q),
// to register interface (read)
.qs (alert_regwen_2_qs)
@@ -936,8 +936,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_3_we),
@@ -945,11 +945,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[3].q ),
+ .q (reg2hw.alert_regwen[3].q),
// to register interface (read)
.qs (alert_regwen_3_qs)
@@ -965,20 +965,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_0_we & alert_regwen_0_qs),
.wd (alert_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[0].q ),
+ .q (reg2hw.alert_en[0].q),
// to register interface (read)
.qs (alert_en_0_qs)
@@ -992,20 +992,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_1_we & alert_regwen_1_qs),
.wd (alert_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[1].q ),
+ .q (reg2hw.alert_en[1].q),
// to register interface (read)
.qs (alert_en_1_qs)
@@ -1019,20 +1019,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_2_we & alert_regwen_2_qs),
.wd (alert_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[2].q ),
+ .q (reg2hw.alert_en[2].q),
// to register interface (read)
.qs (alert_en_2_qs)
@@ -1046,20 +1046,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_3_we & alert_regwen_3_qs),
.wd (alert_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[3].q ),
+ .q (reg2hw.alert_en[3].q),
// to register interface (read)
.qs (alert_en_3_qs)
@@ -1075,20 +1075,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_0_we & alert_regwen_0_qs),
.wd (alert_class_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[0].q ),
+ .q (reg2hw.alert_class[0].q),
// to register interface (read)
.qs (alert_class_0_qs)
@@ -1102,20 +1102,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_1_we & alert_regwen_1_qs),
.wd (alert_class_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[1].q ),
+ .q (reg2hw.alert_class[1].q),
// to register interface (read)
.qs (alert_class_1_qs)
@@ -1129,20 +1129,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_2_we & alert_regwen_2_qs),
.wd (alert_class_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[2].q ),
+ .q (reg2hw.alert_class[2].q),
// to register interface (read)
.qs (alert_class_2_qs)
@@ -1156,20 +1156,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_3_we & alert_regwen_3_qs),
.wd (alert_class_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[3].q ),
+ .q (reg2hw.alert_class[3].q),
// to register interface (read)
.qs (alert_class_3_qs)
@@ -1185,8 +1185,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_0_we),
@@ -1194,11 +1194,11 @@
// from internal hardware
.de (hw2reg.alert_cause[0].de),
- .d (hw2reg.alert_cause[0].d ),
+ .d (hw2reg.alert_cause[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[0].q ),
+ .q (reg2hw.alert_cause[0].q),
// to register interface (read)
.qs (alert_cause_0_qs)
@@ -1212,8 +1212,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_1_we),
@@ -1221,11 +1221,11 @@
// from internal hardware
.de (hw2reg.alert_cause[1].de),
- .d (hw2reg.alert_cause[1].d ),
+ .d (hw2reg.alert_cause[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[1].q ),
+ .q (reg2hw.alert_cause[1].q),
// to register interface (read)
.qs (alert_cause_1_qs)
@@ -1239,8 +1239,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_2_we),
@@ -1248,11 +1248,11 @@
// from internal hardware
.de (hw2reg.alert_cause[2].de),
- .d (hw2reg.alert_cause[2].d ),
+ .d (hw2reg.alert_cause[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[2].q ),
+ .q (reg2hw.alert_cause[2].q),
// to register interface (read)
.qs (alert_cause_2_qs)
@@ -1266,8 +1266,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_3_we),
@@ -1275,11 +1275,11 @@
// from internal hardware
.de (hw2reg.alert_cause[3].de),
- .d (hw2reg.alert_cause[3].d ),
+ .d (hw2reg.alert_cause[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[3].q ),
+ .q (reg2hw.alert_cause[3].q),
// to register interface (read)
.qs (alert_cause_3_qs)
@@ -1295,8 +1295,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_0_we),
@@ -1304,7 +1304,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1322,8 +1322,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_1_we),
@@ -1331,7 +1331,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1349,8 +1349,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_2_we),
@@ -1358,7 +1358,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1376,8 +1376,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_3_we),
@@ -1385,7 +1385,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1405,20 +1405,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_loc_alert_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_en_0_we & loc_alert_regwen_0_qs),
.wd (loc_alert_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_en[0].q ),
+ .q (reg2hw.loc_alert_en[0].q),
// to register interface (read)
.qs (loc_alert_en_0_qs)
@@ -1432,20 +1432,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_loc_alert_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_en_1_we & loc_alert_regwen_1_qs),
.wd (loc_alert_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_en[1].q ),
+ .q (reg2hw.loc_alert_en[1].q),
// to register interface (read)
.qs (loc_alert_en_1_qs)
@@ -1459,20 +1459,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_loc_alert_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_en_2_we & loc_alert_regwen_2_qs),
.wd (loc_alert_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_en[2].q ),
+ .q (reg2hw.loc_alert_en[2].q),
// to register interface (read)
.qs (loc_alert_en_2_qs)
@@ -1486,20 +1486,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_loc_alert_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_en_3_we & loc_alert_regwen_3_qs),
.wd (loc_alert_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_en[3].q ),
+ .q (reg2hw.loc_alert_en[3].q),
// to register interface (read)
.qs (loc_alert_en_3_qs)
@@ -1515,20 +1515,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_loc_alert_class_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_class_0_we & loc_alert_regwen_0_qs),
.wd (loc_alert_class_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_class[0].q ),
+ .q (reg2hw.loc_alert_class[0].q),
// to register interface (read)
.qs (loc_alert_class_0_qs)
@@ -1542,20 +1542,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_loc_alert_class_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_class_1_we & loc_alert_regwen_1_qs),
.wd (loc_alert_class_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_class[1].q ),
+ .q (reg2hw.loc_alert_class[1].q),
// to register interface (read)
.qs (loc_alert_class_1_qs)
@@ -1569,20 +1569,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_loc_alert_class_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_class_2_we & loc_alert_regwen_2_qs),
.wd (loc_alert_class_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_class[2].q ),
+ .q (reg2hw.loc_alert_class[2].q),
// to register interface (read)
.qs (loc_alert_class_2_qs)
@@ -1596,20 +1596,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_loc_alert_class_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_class_3_we & loc_alert_regwen_3_qs),
.wd (loc_alert_class_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_class[3].q ),
+ .q (reg2hw.loc_alert_class[3].q),
// to register interface (read)
.qs (loc_alert_class_3_qs)
@@ -1625,8 +1625,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_loc_alert_cause_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_cause_0_we),
@@ -1634,11 +1634,11 @@
// from internal hardware
.de (hw2reg.loc_alert_cause[0].de),
- .d (hw2reg.loc_alert_cause[0].d ),
+ .d (hw2reg.loc_alert_cause[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_cause[0].q ),
+ .q (reg2hw.loc_alert_cause[0].q),
// to register interface (read)
.qs (loc_alert_cause_0_qs)
@@ -1652,8 +1652,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_loc_alert_cause_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_cause_1_we),
@@ -1661,11 +1661,11 @@
// from internal hardware
.de (hw2reg.loc_alert_cause[1].de),
- .d (hw2reg.loc_alert_cause[1].d ),
+ .d (hw2reg.loc_alert_cause[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_cause[1].q ),
+ .q (reg2hw.loc_alert_cause[1].q),
// to register interface (read)
.qs (loc_alert_cause_1_qs)
@@ -1679,8 +1679,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_loc_alert_cause_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_cause_2_we),
@@ -1688,11 +1688,11 @@
// from internal hardware
.de (hw2reg.loc_alert_cause[2].de),
- .d (hw2reg.loc_alert_cause[2].d ),
+ .d (hw2reg.loc_alert_cause[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_cause[2].q ),
+ .q (reg2hw.loc_alert_cause[2].q),
// to register interface (read)
.qs (loc_alert_cause_2_qs)
@@ -1706,8 +1706,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_loc_alert_cause_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_cause_3_we),
@@ -1715,11 +1715,11 @@
// from internal hardware
.de (hw2reg.loc_alert_cause[3].de),
- .d (hw2reg.loc_alert_cause[3].d ),
+ .d (hw2reg.loc_alert_cause[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_cause[3].q ),
+ .q (reg2hw.loc_alert_cause[3].q),
// to register interface (read)
.qs (loc_alert_cause_3_qs)
@@ -1733,8 +1733,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classa_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classa_regwen_we),
@@ -1742,7 +1742,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1761,20 +1761,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classa_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_we & classa_regwen_qs),
.wd (classa_ctrl_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en.q ),
+ .q (reg2hw.classa_ctrl.en.q),
// to register interface (read)
.qs (classa_ctrl_en_qs)
@@ -1787,20 +1787,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classa_ctrl_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_lock_we & classa_regwen_qs),
.wd (classa_ctrl_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.lock.q ),
+ .q (reg2hw.classa_ctrl.lock.q),
// to register interface (read)
.qs (classa_ctrl_lock_qs)
@@ -1813,20 +1813,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classa_ctrl_en_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_e0_we & classa_regwen_qs),
.wd (classa_ctrl_en_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en_e0.q ),
+ .q (reg2hw.classa_ctrl.en_e0.q),
// to register interface (read)
.qs (classa_ctrl_en_e0_qs)
@@ -1839,20 +1839,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classa_ctrl_en_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_e1_we & classa_regwen_qs),
.wd (classa_ctrl_en_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en_e1.q ),
+ .q (reg2hw.classa_ctrl.en_e1.q),
// to register interface (read)
.qs (classa_ctrl_en_e1_qs)
@@ -1865,20 +1865,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classa_ctrl_en_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_e2_we & classa_regwen_qs),
.wd (classa_ctrl_en_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en_e2.q ),
+ .q (reg2hw.classa_ctrl.en_e2.q),
// to register interface (read)
.qs (classa_ctrl_en_e2_qs)
@@ -1891,20 +1891,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classa_ctrl_en_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_e3_we & classa_regwen_qs),
.wd (classa_ctrl_en_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en_e3.q ),
+ .q (reg2hw.classa_ctrl.en_e3.q),
// to register interface (read)
.qs (classa_ctrl_en_e3_qs)
@@ -1917,20 +1917,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_classa_ctrl_map_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_map_e0_we & classa_regwen_qs),
.wd (classa_ctrl_map_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.map_e0.q ),
+ .q (reg2hw.classa_ctrl.map_e0.q),
// to register interface (read)
.qs (classa_ctrl_map_e0_qs)
@@ -1943,20 +1943,20 @@
.SWACCESS("RW"),
.RESVAL (2'h1)
) u_classa_ctrl_map_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_map_e1_we & classa_regwen_qs),
.wd (classa_ctrl_map_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.map_e1.q ),
+ .q (reg2hw.classa_ctrl.map_e1.q),
// to register interface (read)
.qs (classa_ctrl_map_e1_qs)
@@ -1969,20 +1969,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_classa_ctrl_map_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_map_e2_we & classa_regwen_qs),
.wd (classa_ctrl_map_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.map_e2.q ),
+ .q (reg2hw.classa_ctrl.map_e2.q),
// to register interface (read)
.qs (classa_ctrl_map_e2_qs)
@@ -1995,20 +1995,20 @@
.SWACCESS("RW"),
.RESVAL (2'h3)
) u_classa_ctrl_map_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_map_e3_we & classa_regwen_qs),
.wd (classa_ctrl_map_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.map_e3.q ),
+ .q (reg2hw.classa_ctrl.map_e3.q),
// to register interface (read)
.qs (classa_ctrl_map_e3_qs)
@@ -2022,8 +2022,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classa_clr_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classa_clr_regwen_we),
@@ -2031,7 +2031,7 @@
// from internal hardware
.de (hw2reg.classa_clr_regwen.de),
- .d (hw2reg.classa_clr_regwen.d ),
+ .d (hw2reg.classa_clr_regwen.d),
// to internal hardware
.qe (),
@@ -2049,21 +2049,22 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_classa_clr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_clr_we & classa_clr_regwen_qs),
.wd (classa_clr_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.classa_clr.qe),
- .q (reg2hw.classa_clr.q ),
+ .q (reg2hw.classa_clr.q),
+ // to register interface (read)
.qs ()
);
@@ -2091,20 +2092,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_classa_accum_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_accum_thresh_we & classa_regwen_qs),
.wd (classa_accum_thresh_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_accum_thresh.q ),
+ .q (reg2hw.classa_accum_thresh.q),
// to register interface (read)
.qs (classa_accum_thresh_qs)
@@ -2118,20 +2119,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_timeout_cyc_we & classa_regwen_qs),
.wd (classa_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_timeout_cyc.q ),
+ .q (reg2hw.classa_timeout_cyc.q),
// to register interface (read)
.qs (classa_timeout_cyc_qs)
@@ -2145,20 +2146,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_phase0_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_phase0_cyc_we & classa_regwen_qs),
.wd (classa_phase0_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_phase0_cyc.q ),
+ .q (reg2hw.classa_phase0_cyc.q),
// to register interface (read)
.qs (classa_phase0_cyc_qs)
@@ -2172,20 +2173,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_phase1_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_phase1_cyc_we & classa_regwen_qs),
.wd (classa_phase1_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_phase1_cyc.q ),
+ .q (reg2hw.classa_phase1_cyc.q),
// to register interface (read)
.qs (classa_phase1_cyc_qs)
@@ -2199,20 +2200,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_phase2_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_phase2_cyc_we & classa_regwen_qs),
.wd (classa_phase2_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_phase2_cyc.q ),
+ .q (reg2hw.classa_phase2_cyc.q),
// to register interface (read)
.qs (classa_phase2_cyc_qs)
@@ -2226,20 +2227,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_phase3_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_phase3_cyc_we & classa_regwen_qs),
.wd (classa_phase3_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_phase3_cyc.q ),
+ .q (reg2hw.classa_phase3_cyc.q),
// to register interface (read)
.qs (classa_phase3_cyc_qs)
@@ -2285,8 +2286,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classb_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classb_regwen_we),
@@ -2294,7 +2295,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2313,20 +2314,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classb_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_we & classb_regwen_qs),
.wd (classb_ctrl_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en.q ),
+ .q (reg2hw.classb_ctrl.en.q),
// to register interface (read)
.qs (classb_ctrl_en_qs)
@@ -2339,20 +2340,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classb_ctrl_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_lock_we & classb_regwen_qs),
.wd (classb_ctrl_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.lock.q ),
+ .q (reg2hw.classb_ctrl.lock.q),
// to register interface (read)
.qs (classb_ctrl_lock_qs)
@@ -2365,20 +2366,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classb_ctrl_en_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_e0_we & classb_regwen_qs),
.wd (classb_ctrl_en_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en_e0.q ),
+ .q (reg2hw.classb_ctrl.en_e0.q),
// to register interface (read)
.qs (classb_ctrl_en_e0_qs)
@@ -2391,20 +2392,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classb_ctrl_en_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_e1_we & classb_regwen_qs),
.wd (classb_ctrl_en_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en_e1.q ),
+ .q (reg2hw.classb_ctrl.en_e1.q),
// to register interface (read)
.qs (classb_ctrl_en_e1_qs)
@@ -2417,20 +2418,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classb_ctrl_en_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_e2_we & classb_regwen_qs),
.wd (classb_ctrl_en_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en_e2.q ),
+ .q (reg2hw.classb_ctrl.en_e2.q),
// to register interface (read)
.qs (classb_ctrl_en_e2_qs)
@@ -2443,20 +2444,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classb_ctrl_en_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_e3_we & classb_regwen_qs),
.wd (classb_ctrl_en_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en_e3.q ),
+ .q (reg2hw.classb_ctrl.en_e3.q),
// to register interface (read)
.qs (classb_ctrl_en_e3_qs)
@@ -2469,20 +2470,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_classb_ctrl_map_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_map_e0_we & classb_regwen_qs),
.wd (classb_ctrl_map_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.map_e0.q ),
+ .q (reg2hw.classb_ctrl.map_e0.q),
// to register interface (read)
.qs (classb_ctrl_map_e0_qs)
@@ -2495,20 +2496,20 @@
.SWACCESS("RW"),
.RESVAL (2'h1)
) u_classb_ctrl_map_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_map_e1_we & classb_regwen_qs),
.wd (classb_ctrl_map_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.map_e1.q ),
+ .q (reg2hw.classb_ctrl.map_e1.q),
// to register interface (read)
.qs (classb_ctrl_map_e1_qs)
@@ -2521,20 +2522,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_classb_ctrl_map_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_map_e2_we & classb_regwen_qs),
.wd (classb_ctrl_map_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.map_e2.q ),
+ .q (reg2hw.classb_ctrl.map_e2.q),
// to register interface (read)
.qs (classb_ctrl_map_e2_qs)
@@ -2547,20 +2548,20 @@
.SWACCESS("RW"),
.RESVAL (2'h3)
) u_classb_ctrl_map_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_map_e3_we & classb_regwen_qs),
.wd (classb_ctrl_map_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.map_e3.q ),
+ .q (reg2hw.classb_ctrl.map_e3.q),
// to register interface (read)
.qs (classb_ctrl_map_e3_qs)
@@ -2574,8 +2575,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classb_clr_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classb_clr_regwen_we),
@@ -2583,7 +2584,7 @@
// from internal hardware
.de (hw2reg.classb_clr_regwen.de),
- .d (hw2reg.classb_clr_regwen.d ),
+ .d (hw2reg.classb_clr_regwen.d),
// to internal hardware
.qe (),
@@ -2601,21 +2602,22 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_classb_clr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_clr_we & classb_clr_regwen_qs),
.wd (classb_clr_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.classb_clr.qe),
- .q (reg2hw.classb_clr.q ),
+ .q (reg2hw.classb_clr.q),
+ // to register interface (read)
.qs ()
);
@@ -2643,20 +2645,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_classb_accum_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_accum_thresh_we & classb_regwen_qs),
.wd (classb_accum_thresh_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_accum_thresh.q ),
+ .q (reg2hw.classb_accum_thresh.q),
// to register interface (read)
.qs (classb_accum_thresh_qs)
@@ -2670,20 +2672,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_timeout_cyc_we & classb_regwen_qs),
.wd (classb_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_timeout_cyc.q ),
+ .q (reg2hw.classb_timeout_cyc.q),
// to register interface (read)
.qs (classb_timeout_cyc_qs)
@@ -2697,20 +2699,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_phase0_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_phase0_cyc_we & classb_regwen_qs),
.wd (classb_phase0_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_phase0_cyc.q ),
+ .q (reg2hw.classb_phase0_cyc.q),
// to register interface (read)
.qs (classb_phase0_cyc_qs)
@@ -2724,20 +2726,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_phase1_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_phase1_cyc_we & classb_regwen_qs),
.wd (classb_phase1_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_phase1_cyc.q ),
+ .q (reg2hw.classb_phase1_cyc.q),
// to register interface (read)
.qs (classb_phase1_cyc_qs)
@@ -2751,20 +2753,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_phase2_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_phase2_cyc_we & classb_regwen_qs),
.wd (classb_phase2_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_phase2_cyc.q ),
+ .q (reg2hw.classb_phase2_cyc.q),
// to register interface (read)
.qs (classb_phase2_cyc_qs)
@@ -2778,20 +2780,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_phase3_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_phase3_cyc_we & classb_regwen_qs),
.wd (classb_phase3_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_phase3_cyc.q ),
+ .q (reg2hw.classb_phase3_cyc.q),
// to register interface (read)
.qs (classb_phase3_cyc_qs)
@@ -2837,8 +2839,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classc_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classc_regwen_we),
@@ -2846,7 +2848,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2865,20 +2867,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classc_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_we & classc_regwen_qs),
.wd (classc_ctrl_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en.q ),
+ .q (reg2hw.classc_ctrl.en.q),
// to register interface (read)
.qs (classc_ctrl_en_qs)
@@ -2891,20 +2893,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classc_ctrl_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_lock_we & classc_regwen_qs),
.wd (classc_ctrl_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.lock.q ),
+ .q (reg2hw.classc_ctrl.lock.q),
// to register interface (read)
.qs (classc_ctrl_lock_qs)
@@ -2917,20 +2919,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classc_ctrl_en_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_e0_we & classc_regwen_qs),
.wd (classc_ctrl_en_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en_e0.q ),
+ .q (reg2hw.classc_ctrl.en_e0.q),
// to register interface (read)
.qs (classc_ctrl_en_e0_qs)
@@ -2943,20 +2945,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classc_ctrl_en_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_e1_we & classc_regwen_qs),
.wd (classc_ctrl_en_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en_e1.q ),
+ .q (reg2hw.classc_ctrl.en_e1.q),
// to register interface (read)
.qs (classc_ctrl_en_e1_qs)
@@ -2969,20 +2971,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classc_ctrl_en_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_e2_we & classc_regwen_qs),
.wd (classc_ctrl_en_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en_e2.q ),
+ .q (reg2hw.classc_ctrl.en_e2.q),
// to register interface (read)
.qs (classc_ctrl_en_e2_qs)
@@ -2995,20 +2997,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classc_ctrl_en_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_e3_we & classc_regwen_qs),
.wd (classc_ctrl_en_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en_e3.q ),
+ .q (reg2hw.classc_ctrl.en_e3.q),
// to register interface (read)
.qs (classc_ctrl_en_e3_qs)
@@ -3021,20 +3023,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_classc_ctrl_map_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_map_e0_we & classc_regwen_qs),
.wd (classc_ctrl_map_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.map_e0.q ),
+ .q (reg2hw.classc_ctrl.map_e0.q),
// to register interface (read)
.qs (classc_ctrl_map_e0_qs)
@@ -3047,20 +3049,20 @@
.SWACCESS("RW"),
.RESVAL (2'h1)
) u_classc_ctrl_map_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_map_e1_we & classc_regwen_qs),
.wd (classc_ctrl_map_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.map_e1.q ),
+ .q (reg2hw.classc_ctrl.map_e1.q),
// to register interface (read)
.qs (classc_ctrl_map_e1_qs)
@@ -3073,20 +3075,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_classc_ctrl_map_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_map_e2_we & classc_regwen_qs),
.wd (classc_ctrl_map_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.map_e2.q ),
+ .q (reg2hw.classc_ctrl.map_e2.q),
// to register interface (read)
.qs (classc_ctrl_map_e2_qs)
@@ -3099,20 +3101,20 @@
.SWACCESS("RW"),
.RESVAL (2'h3)
) u_classc_ctrl_map_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_map_e3_we & classc_regwen_qs),
.wd (classc_ctrl_map_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.map_e3.q ),
+ .q (reg2hw.classc_ctrl.map_e3.q),
// to register interface (read)
.qs (classc_ctrl_map_e3_qs)
@@ -3126,8 +3128,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classc_clr_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classc_clr_regwen_we),
@@ -3135,7 +3137,7 @@
// from internal hardware
.de (hw2reg.classc_clr_regwen.de),
- .d (hw2reg.classc_clr_regwen.d ),
+ .d (hw2reg.classc_clr_regwen.d),
// to internal hardware
.qe (),
@@ -3153,21 +3155,22 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_classc_clr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_clr_we & classc_clr_regwen_qs),
.wd (classc_clr_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.classc_clr.qe),
- .q (reg2hw.classc_clr.q ),
+ .q (reg2hw.classc_clr.q),
+ // to register interface (read)
.qs ()
);
@@ -3195,20 +3198,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_classc_accum_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_accum_thresh_we & classc_regwen_qs),
.wd (classc_accum_thresh_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_accum_thresh.q ),
+ .q (reg2hw.classc_accum_thresh.q),
// to register interface (read)
.qs (classc_accum_thresh_qs)
@@ -3222,20 +3225,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_timeout_cyc_we & classc_regwen_qs),
.wd (classc_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_timeout_cyc.q ),
+ .q (reg2hw.classc_timeout_cyc.q),
// to register interface (read)
.qs (classc_timeout_cyc_qs)
@@ -3249,20 +3252,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_phase0_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_phase0_cyc_we & classc_regwen_qs),
.wd (classc_phase0_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_phase0_cyc.q ),
+ .q (reg2hw.classc_phase0_cyc.q),
// to register interface (read)
.qs (classc_phase0_cyc_qs)
@@ -3276,20 +3279,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_phase1_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_phase1_cyc_we & classc_regwen_qs),
.wd (classc_phase1_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_phase1_cyc.q ),
+ .q (reg2hw.classc_phase1_cyc.q),
// to register interface (read)
.qs (classc_phase1_cyc_qs)
@@ -3303,20 +3306,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_phase2_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_phase2_cyc_we & classc_regwen_qs),
.wd (classc_phase2_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_phase2_cyc.q ),
+ .q (reg2hw.classc_phase2_cyc.q),
// to register interface (read)
.qs (classc_phase2_cyc_qs)
@@ -3330,20 +3333,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_phase3_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_phase3_cyc_we & classc_regwen_qs),
.wd (classc_phase3_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_phase3_cyc.q ),
+ .q (reg2hw.classc_phase3_cyc.q),
// to register interface (read)
.qs (classc_phase3_cyc_qs)
@@ -3389,8 +3392,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classd_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classd_regwen_we),
@@ -3398,7 +3401,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3417,20 +3420,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classd_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_we & classd_regwen_qs),
.wd (classd_ctrl_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en.q ),
+ .q (reg2hw.classd_ctrl.en.q),
// to register interface (read)
.qs (classd_ctrl_en_qs)
@@ -3443,20 +3446,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classd_ctrl_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_lock_we & classd_regwen_qs),
.wd (classd_ctrl_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.lock.q ),
+ .q (reg2hw.classd_ctrl.lock.q),
// to register interface (read)
.qs (classd_ctrl_lock_qs)
@@ -3469,20 +3472,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classd_ctrl_en_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_e0_we & classd_regwen_qs),
.wd (classd_ctrl_en_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en_e0.q ),
+ .q (reg2hw.classd_ctrl.en_e0.q),
// to register interface (read)
.qs (classd_ctrl_en_e0_qs)
@@ -3495,20 +3498,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classd_ctrl_en_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_e1_we & classd_regwen_qs),
.wd (classd_ctrl_en_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en_e1.q ),
+ .q (reg2hw.classd_ctrl.en_e1.q),
// to register interface (read)
.qs (classd_ctrl_en_e1_qs)
@@ -3521,20 +3524,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classd_ctrl_en_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_e2_we & classd_regwen_qs),
.wd (classd_ctrl_en_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en_e2.q ),
+ .q (reg2hw.classd_ctrl.en_e2.q),
// to register interface (read)
.qs (classd_ctrl_en_e2_qs)
@@ -3547,20 +3550,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classd_ctrl_en_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_e3_we & classd_regwen_qs),
.wd (classd_ctrl_en_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en_e3.q ),
+ .q (reg2hw.classd_ctrl.en_e3.q),
// to register interface (read)
.qs (classd_ctrl_en_e3_qs)
@@ -3573,20 +3576,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_classd_ctrl_map_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_map_e0_we & classd_regwen_qs),
.wd (classd_ctrl_map_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.map_e0.q ),
+ .q (reg2hw.classd_ctrl.map_e0.q),
// to register interface (read)
.qs (classd_ctrl_map_e0_qs)
@@ -3599,20 +3602,20 @@
.SWACCESS("RW"),
.RESVAL (2'h1)
) u_classd_ctrl_map_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_map_e1_we & classd_regwen_qs),
.wd (classd_ctrl_map_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.map_e1.q ),
+ .q (reg2hw.classd_ctrl.map_e1.q),
// to register interface (read)
.qs (classd_ctrl_map_e1_qs)
@@ -3625,20 +3628,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_classd_ctrl_map_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_map_e2_we & classd_regwen_qs),
.wd (classd_ctrl_map_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.map_e2.q ),
+ .q (reg2hw.classd_ctrl.map_e2.q),
// to register interface (read)
.qs (classd_ctrl_map_e2_qs)
@@ -3651,20 +3654,20 @@
.SWACCESS("RW"),
.RESVAL (2'h3)
) u_classd_ctrl_map_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_map_e3_we & classd_regwen_qs),
.wd (classd_ctrl_map_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.map_e3.q ),
+ .q (reg2hw.classd_ctrl.map_e3.q),
// to register interface (read)
.qs (classd_ctrl_map_e3_qs)
@@ -3678,8 +3681,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classd_clr_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classd_clr_regwen_we),
@@ -3687,7 +3690,7 @@
// from internal hardware
.de (hw2reg.classd_clr_regwen.de),
- .d (hw2reg.classd_clr_regwen.d ),
+ .d (hw2reg.classd_clr_regwen.d),
// to internal hardware
.qe (),
@@ -3705,21 +3708,22 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_classd_clr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_clr_we & classd_clr_regwen_qs),
.wd (classd_clr_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.classd_clr.qe),
- .q (reg2hw.classd_clr.q ),
+ .q (reg2hw.classd_clr.q),
+ // to register interface (read)
.qs ()
);
@@ -3747,20 +3751,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_classd_accum_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_accum_thresh_we & classd_regwen_qs),
.wd (classd_accum_thresh_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_accum_thresh.q ),
+ .q (reg2hw.classd_accum_thresh.q),
// to register interface (read)
.qs (classd_accum_thresh_qs)
@@ -3774,20 +3778,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_timeout_cyc_we & classd_regwen_qs),
.wd (classd_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_timeout_cyc.q ),
+ .q (reg2hw.classd_timeout_cyc.q),
// to register interface (read)
.qs (classd_timeout_cyc_qs)
@@ -3801,20 +3805,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_phase0_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_phase0_cyc_we & classd_regwen_qs),
.wd (classd_phase0_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_phase0_cyc.q ),
+ .q (reg2hw.classd_phase0_cyc.q),
// to register interface (read)
.qs (classd_phase0_cyc_qs)
@@ -3828,20 +3832,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_phase1_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_phase1_cyc_we & classd_regwen_qs),
.wd (classd_phase1_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_phase1_cyc.q ),
+ .q (reg2hw.classd_phase1_cyc.q),
// to register interface (read)
.qs (classd_phase1_cyc_qs)
@@ -3855,20 +3859,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_phase2_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_phase2_cyc_we & classd_regwen_qs),
.wd (classd_phase2_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_phase2_cyc.q ),
+ .q (reg2hw.classd_phase2_cyc.q),
// to register interface (read)
.qs (classd_phase2_cyc_qs)
@@ -3882,20 +3886,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_phase3_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_phase3_cyc_we & classd_regwen_qs),
.wd (classd_phase3_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_phase3_cyc.q ),
+ .q (reg2hw.classd_phase3_cyc.q),
// to register interface (read)
.qs (classd_phase3_cyc_qs)
diff --git a/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv b/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
index fc4b9f4..1e9a147 100644
--- a/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
+++ b/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
@@ -171,7 +171,7 @@
.d (hw2reg.wkup_ctrl.enable.d),
.qre (),
.qe (reg2hw.wkup_ctrl.enable.qe),
- .q (reg2hw.wkup_ctrl.enable.q ),
+ .q (reg2hw.wkup_ctrl.enable.q),
.qs (wkup_ctrl_enable_qs)
);
@@ -186,7 +186,7 @@
.d (hw2reg.wkup_ctrl.prescaler.d),
.qre (),
.qe (reg2hw.wkup_ctrl.prescaler.qe),
- .q (reg2hw.wkup_ctrl.prescaler.q ),
+ .q (reg2hw.wkup_ctrl.prescaler.q),
.qs (wkup_ctrl_prescaler_qs)
);
@@ -202,7 +202,7 @@
.d (hw2reg.wkup_thold.d),
.qre (),
.qe (reg2hw.wkup_thold.qe),
- .q (reg2hw.wkup_thold.q ),
+ .q (reg2hw.wkup_thold.q),
.qs (wkup_thold_qs)
);
@@ -218,7 +218,7 @@
.d (hw2reg.wkup_count.d),
.qre (),
.qe (reg2hw.wkup_count.qe),
- .q (reg2hw.wkup_count.q ),
+ .q (reg2hw.wkup_count.q),
.qs (wkup_count_qs)
);
@@ -230,8 +230,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wdog_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wdog_regwen_we),
@@ -239,7 +239,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -257,13 +257,12 @@
.DW (1)
) u_wdog_ctrl_enable (
.re (wdog_ctrl_enable_re),
- // qualified with register enable
.we (wdog_ctrl_enable_we & wdog_regwen_qs),
.wd (wdog_ctrl_enable_wd),
.d (hw2reg.wdog_ctrl.enable.d),
.qre (),
.qe (reg2hw.wdog_ctrl.enable.qe),
- .q (reg2hw.wdog_ctrl.enable.q ),
+ .q (reg2hw.wdog_ctrl.enable.q),
.qs (wdog_ctrl_enable_qs)
);
@@ -273,13 +272,12 @@
.DW (1)
) u_wdog_ctrl_pause_in_sleep (
.re (wdog_ctrl_pause_in_sleep_re),
- // qualified with register enable
.we (wdog_ctrl_pause_in_sleep_we & wdog_regwen_qs),
.wd (wdog_ctrl_pause_in_sleep_wd),
.d (hw2reg.wdog_ctrl.pause_in_sleep.d),
.qre (),
.qe (reg2hw.wdog_ctrl.pause_in_sleep.qe),
- .q (reg2hw.wdog_ctrl.pause_in_sleep.q ),
+ .q (reg2hw.wdog_ctrl.pause_in_sleep.q),
.qs (wdog_ctrl_pause_in_sleep_qs)
);
@@ -290,13 +288,12 @@
.DW (32)
) u_wdog_bark_thold (
.re (wdog_bark_thold_re),
- // qualified with register enable
.we (wdog_bark_thold_we & wdog_regwen_qs),
.wd (wdog_bark_thold_wd),
.d (hw2reg.wdog_bark_thold.d),
.qre (),
.qe (reg2hw.wdog_bark_thold.qe),
- .q (reg2hw.wdog_bark_thold.q ),
+ .q (reg2hw.wdog_bark_thold.q),
.qs (wdog_bark_thold_qs)
);
@@ -307,13 +304,12 @@
.DW (32)
) u_wdog_bite_thold (
.re (wdog_bite_thold_re),
- // qualified with register enable
.we (wdog_bite_thold_we & wdog_regwen_qs),
.wd (wdog_bite_thold_wd),
.d (hw2reg.wdog_bite_thold.d),
.qre (),
.qe (reg2hw.wdog_bite_thold.qe),
- .q (reg2hw.wdog_bite_thold.q ),
+ .q (reg2hw.wdog_bite_thold.q),
.qs (wdog_bite_thold_qs)
);
@@ -329,7 +325,7 @@
.d (hw2reg.wdog_count.d),
.qre (),
.qe (reg2hw.wdog_count.qe),
- .q (reg2hw.wdog_count.q ),
+ .q (reg2hw.wdog_count.q),
.qs (wdog_count_qs)
);
@@ -342,8 +338,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_wkup_timer_expired (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_wkup_timer_expired_we),
@@ -351,11 +347,11 @@
// from internal hardware
.de (hw2reg.intr_state.wkup_timer_expired.de),
- .d (hw2reg.intr_state.wkup_timer_expired.d ),
+ .d (hw2reg.intr_state.wkup_timer_expired.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.wkup_timer_expired.q ),
+ .q (reg2hw.intr_state.wkup_timer_expired.q),
// to register interface (read)
.qs (intr_state_wkup_timer_expired_qs)
@@ -368,8 +364,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_wdog_timer_expired (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_wdog_timer_expired_we),
@@ -377,11 +373,11 @@
// from internal hardware
.de (hw2reg.intr_state.wdog_timer_expired.de),
- .d (hw2reg.intr_state.wdog_timer_expired.d ),
+ .d (hw2reg.intr_state.wdog_timer_expired.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.wdog_timer_expired.q ),
+ .q (reg2hw.intr_state.wdog_timer_expired.q),
// to register interface (read)
.qs (intr_state_wdog_timer_expired_qs)
@@ -400,7 +396,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.wkup_timer_expired.qe),
- .q (reg2hw.intr_test.wkup_timer_expired.q ),
+ .q (reg2hw.intr_test.wkup_timer_expired.q),
.qs ()
);
@@ -415,7 +411,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.wdog_timer_expired.qe),
- .q (reg2hw.intr_test.wdog_timer_expired.q ),
+ .q (reg2hw.intr_test.wdog_timer_expired.q),
.qs ()
);
@@ -431,7 +427,7 @@
.d (hw2reg.wkup_cause.d),
.qre (),
.qe (reg2hw.wkup_cause.qe),
- .q (reg2hw.wkup_cause.q ),
+ .q (reg2hw.wkup_cause.q),
.qs (wkup_cause_qs)
);
diff --git a/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv b/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv
index 07b7d9d..7379da6 100644
--- a/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv
+++ b/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv
@@ -128,8 +128,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_enables_clk_fixed_peri_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_enables_clk_fixed_peri_en_we),
@@ -137,11 +137,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_enables.clk_fixed_peri_en.q ),
+ .q (reg2hw.clk_enables.clk_fixed_peri_en.q),
// to register interface (read)
.qs (clk_enables_clk_fixed_peri_en_qs)
@@ -154,8 +154,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_enables_clk_usb_48mhz_peri_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_enables_clk_usb_48mhz_peri_en_we),
@@ -163,11 +163,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_enables.clk_usb_48mhz_peri_en.q ),
+ .q (reg2hw.clk_enables.clk_usb_48mhz_peri_en.q),
// to register interface (read)
.qs (clk_enables_clk_usb_48mhz_peri_en_qs)
@@ -182,8 +182,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_hints_clk_main_aes_hint (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_hints_clk_main_aes_hint_we),
@@ -191,11 +191,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_hints.clk_main_aes_hint.q ),
+ .q (reg2hw.clk_hints.clk_main_aes_hint.q),
// to register interface (read)
.qs (clk_hints_clk_main_aes_hint_qs)
@@ -208,8 +208,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_hints_clk_main_hmac_hint (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_hints_clk_main_hmac_hint_we),
@@ -217,11 +217,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_hints.clk_main_hmac_hint.q ),
+ .q (reg2hw.clk_hints.clk_main_hmac_hint.q),
// to register interface (read)
.qs (clk_hints_clk_main_hmac_hint_qs)
@@ -236,15 +236,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_clk_hints_status_clk_main_aes_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.clk_hints_status.clk_main_aes_val.de),
- .d (hw2reg.clk_hints_status.clk_main_aes_val.d ),
+ .d (hw2reg.clk_hints_status.clk_main_aes_val.d),
// to internal hardware
.qe (),
@@ -261,15 +262,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_clk_hints_status_clk_main_hmac_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.clk_hints_status.clk_main_hmac_val.de),
- .d (hw2reg.clk_hints_status.clk_main_hmac_val.d ),
+ .d (hw2reg.clk_hints_status.clk_main_hmac_val.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/csrng/rtl/csrng_reg_top.sv b/hw/ip/csrng/rtl/csrng_reg_top.sv
index 12bd7e3..e5f9604 100644
--- a/hw/ip/csrng/rtl/csrng_reg_top.sv
+++ b/hw/ip/csrng/rtl/csrng_reg_top.sv
@@ -212,8 +212,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_cs_cmd_req_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_cs_cmd_req_done_we),
@@ -221,11 +221,11 @@
// from internal hardware
.de (hw2reg.intr_state.cs_cmd_req_done.de),
- .d (hw2reg.intr_state.cs_cmd_req_done.d ),
+ .d (hw2reg.intr_state.cs_cmd_req_done.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.cs_cmd_req_done.q ),
+ .q (reg2hw.intr_state.cs_cmd_req_done.q),
// to register interface (read)
.qs (intr_state_cs_cmd_req_done_qs)
@@ -238,8 +238,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_cs_entropy_req (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_cs_entropy_req_we),
@@ -247,11 +247,11 @@
// from internal hardware
.de (hw2reg.intr_state.cs_entropy_req.de),
- .d (hw2reg.intr_state.cs_entropy_req.d ),
+ .d (hw2reg.intr_state.cs_entropy_req.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.cs_entropy_req.q ),
+ .q (reg2hw.intr_state.cs_entropy_req.q),
// to register interface (read)
.qs (intr_state_cs_entropy_req_qs)
@@ -264,8 +264,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_cs_hw_inst_exc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_cs_hw_inst_exc_we),
@@ -273,11 +273,11 @@
// from internal hardware
.de (hw2reg.intr_state.cs_hw_inst_exc.de),
- .d (hw2reg.intr_state.cs_hw_inst_exc.d ),
+ .d (hw2reg.intr_state.cs_hw_inst_exc.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.cs_hw_inst_exc.q ),
+ .q (reg2hw.intr_state.cs_hw_inst_exc.q),
// to register interface (read)
.qs (intr_state_cs_hw_inst_exc_qs)
@@ -290,8 +290,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_cs_fatal_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_cs_fatal_err_we),
@@ -299,11 +299,11 @@
// from internal hardware
.de (hw2reg.intr_state.cs_fatal_err.de),
- .d (hw2reg.intr_state.cs_fatal_err.d ),
+ .d (hw2reg.intr_state.cs_fatal_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.cs_fatal_err.q ),
+ .q (reg2hw.intr_state.cs_fatal_err.q),
// to register interface (read)
.qs (intr_state_cs_fatal_err_qs)
@@ -318,8 +318,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_cs_cmd_req_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_cs_cmd_req_done_we),
@@ -327,11 +327,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.cs_cmd_req_done.q ),
+ .q (reg2hw.intr_enable.cs_cmd_req_done.q),
// to register interface (read)
.qs (intr_enable_cs_cmd_req_done_qs)
@@ -344,8 +344,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_cs_entropy_req (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_cs_entropy_req_we),
@@ -353,11 +353,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.cs_entropy_req.q ),
+ .q (reg2hw.intr_enable.cs_entropy_req.q),
// to register interface (read)
.qs (intr_enable_cs_entropy_req_qs)
@@ -370,8 +370,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_cs_hw_inst_exc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_cs_hw_inst_exc_we),
@@ -379,11 +379,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.cs_hw_inst_exc.q ),
+ .q (reg2hw.intr_enable.cs_hw_inst_exc.q),
// to register interface (read)
.qs (intr_enable_cs_hw_inst_exc_qs)
@@ -396,8 +396,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_cs_fatal_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_cs_fatal_err_we),
@@ -405,11 +405,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.cs_fatal_err.q ),
+ .q (reg2hw.intr_enable.cs_fatal_err.q),
// to register interface (read)
.qs (intr_enable_cs_fatal_err_qs)
@@ -428,7 +428,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.cs_cmd_req_done.qe),
- .q (reg2hw.intr_test.cs_cmd_req_done.q ),
+ .q (reg2hw.intr_test.cs_cmd_req_done.q),
.qs ()
);
@@ -443,7 +443,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.cs_entropy_req.qe),
- .q (reg2hw.intr_test.cs_entropy_req.q ),
+ .q (reg2hw.intr_test.cs_entropy_req.q),
.qs ()
);
@@ -458,7 +458,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.cs_hw_inst_exc.qe),
- .q (reg2hw.intr_test.cs_hw_inst_exc.q ),
+ .q (reg2hw.intr_test.cs_hw_inst_exc.q),
.qs ()
);
@@ -473,7 +473,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.cs_fatal_err.qe),
- .q (reg2hw.intr_test.cs_fatal_err.q ),
+ .q (reg2hw.intr_test.cs_fatal_err.q),
.qs ()
);
@@ -489,7 +489,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.qe),
- .q (reg2hw.alert_test.q ),
+ .q (reg2hw.alert_test.q),
.qs ()
);
@@ -518,8 +518,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_enable_we),
@@ -527,11 +527,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.enable.q ),
+ .q (reg2hw.ctrl.enable.q),
// to register interface (read)
.qs (ctrl_enable_qs)
@@ -544,8 +544,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_aes_cipher_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_aes_cipher_disable_we),
@@ -553,11 +553,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.aes_cipher_disable.q ),
+ .q (reg2hw.ctrl.aes_cipher_disable.q),
// to register interface (read)
.qs (ctrl_aes_cipher_disable_qs)
@@ -570,8 +570,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_ctrl_fifo_depth_sts_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_fifo_depth_sts_sel_we),
@@ -579,11 +579,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.fifo_depth_sts_sel.q ),
+ .q (reg2hw.ctrl.fifo_depth_sts_sel.q),
// to register interface (read)
.qs (ctrl_fifo_depth_sts_sel_qs)
@@ -597,15 +597,16 @@
.SWACCESS("RO"),
.RESVAL (24'h0)
) u_sum_sts (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.sum_sts.de),
- .d (hw2reg.sum_sts.d ),
+ .d (hw2reg.sum_sts.d),
// to internal hardware
.qe (),
@@ -623,8 +624,8 @@
.SWACCESS("WO"),
.RESVAL (32'h0)
) u_cmd_req (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_req_we),
@@ -632,12 +633,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.cmd_req.qe),
- .q (reg2hw.cmd_req.q ),
+ .q (reg2hw.cmd_req.q),
+ // to register interface (read)
.qs ()
);
@@ -650,15 +652,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_sw_cmd_sts_cmd_rdy (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.sw_cmd_sts.cmd_rdy.de),
- .d (hw2reg.sw_cmd_sts.cmd_rdy.d ),
+ .d (hw2reg.sw_cmd_sts.cmd_rdy.d),
// to internal hardware
.qe (),
@@ -675,15 +678,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_sw_cmd_sts_cmd_sts (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.sw_cmd_sts.cmd_sts.de),
- .d (hw2reg.sw_cmd_sts.cmd_sts.d ),
+ .d (hw2reg.sw_cmd_sts.cmd_sts.d),
// to internal hardware
.qe (),
@@ -737,7 +741,7 @@
.d (hw2reg.genbits.d),
.qre (reg2hw.genbits.re),
.qe (),
- .q (reg2hw.genbits.q ),
+ .q (reg2hw.genbits.q),
.qs (genbits_qs)
);
@@ -749,8 +753,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_halt_main_sm (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (halt_main_sm_we),
@@ -758,12 +762,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.halt_main_sm.q ),
+ .q (reg2hw.halt_main_sm.q),
+ // to register interface (read)
.qs ()
);
@@ -775,15 +780,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_main_sm_sts (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.main_sm_sts.de),
- .d (hw2reg.main_sm_sts.d ),
+ .d (hw2reg.main_sm_sts.d),
// to internal hardware
.qe (),
@@ -801,8 +807,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_int_state_num (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (int_state_num_we),
@@ -810,11 +816,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.int_state_num.qe),
- .q (reg2hw.int_state_num.q ),
+ .q (reg2hw.int_state_num.q),
// to register interface (read)
.qs (int_state_num_qs)
@@ -832,7 +838,7 @@
.d (hw2reg.int_state_val.d),
.qre (reg2hw.int_state_val.re),
.qe (),
- .q (reg2hw.int_state_val.q ),
+ .q (reg2hw.int_state_val.q),
.qs (int_state_val_qs)
);
@@ -844,8 +850,8 @@
.SWACCESS("RW"),
.RESVAL (15'h0)
) u_hw_exc_sts (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (hw_exc_sts_we),
@@ -853,7 +859,7 @@
// from internal hardware
.de (hw2reg.hw_exc_sts.de),
- .d (hw2reg.hw_exc_sts.d ),
+ .d (hw2reg.hw_exc_sts.d),
// to internal hardware
.qe (),
@@ -872,15 +878,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_cmd_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_cmd_err.de),
- .d (hw2reg.err_code.sfifo_cmd_err.d ),
+ .d (hw2reg.err_code.sfifo_cmd_err.d),
// to internal hardware
.qe (),
@@ -897,15 +904,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_genbits_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_genbits_err.de),
- .d (hw2reg.err_code.sfifo_genbits_err.d ),
+ .d (hw2reg.err_code.sfifo_genbits_err.d),
// to internal hardware
.qe (),
@@ -922,15 +930,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_cmdreq_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_cmdreq_err.de),
- .d (hw2reg.err_code.sfifo_cmdreq_err.d ),
+ .d (hw2reg.err_code.sfifo_cmdreq_err.d),
// to internal hardware
.qe (),
@@ -947,15 +956,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_rcstage_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_rcstage_err.de),
- .d (hw2reg.err_code.sfifo_rcstage_err.d ),
+ .d (hw2reg.err_code.sfifo_rcstage_err.d),
// to internal hardware
.qe (),
@@ -972,15 +982,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_keyvrc_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_keyvrc_err.de),
- .d (hw2reg.err_code.sfifo_keyvrc_err.d ),
+ .d (hw2reg.err_code.sfifo_keyvrc_err.d),
// to internal hardware
.qe (),
@@ -997,15 +1008,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_updreq_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_updreq_err.de),
- .d (hw2reg.err_code.sfifo_updreq_err.d ),
+ .d (hw2reg.err_code.sfifo_updreq_err.d),
// to internal hardware
.qe (),
@@ -1022,15 +1034,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_bencreq_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_bencreq_err.de),
- .d (hw2reg.err_code.sfifo_bencreq_err.d ),
+ .d (hw2reg.err_code.sfifo_bencreq_err.d),
// to internal hardware
.qe (),
@@ -1047,15 +1060,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_bencack_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_bencack_err.de),
- .d (hw2reg.err_code.sfifo_bencack_err.d ),
+ .d (hw2reg.err_code.sfifo_bencack_err.d),
// to internal hardware
.qe (),
@@ -1072,15 +1086,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_pdata_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_pdata_err.de),
- .d (hw2reg.err_code.sfifo_pdata_err.d ),
+ .d (hw2reg.err_code.sfifo_pdata_err.d),
// to internal hardware
.qe (),
@@ -1097,15 +1112,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_final_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_final_err.de),
- .d (hw2reg.err_code.sfifo_final_err.d ),
+ .d (hw2reg.err_code.sfifo_final_err.d),
// to internal hardware
.qe (),
@@ -1122,15 +1138,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_gbencack_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_gbencack_err.de),
- .d (hw2reg.err_code.sfifo_gbencack_err.d ),
+ .d (hw2reg.err_code.sfifo_gbencack_err.d),
// to internal hardware
.qe (),
@@ -1147,15 +1164,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_grcstage_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_grcstage_err.de),
- .d (hw2reg.err_code.sfifo_grcstage_err.d ),
+ .d (hw2reg.err_code.sfifo_grcstage_err.d),
// to internal hardware
.qe (),
@@ -1172,15 +1190,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_ggenreq_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_ggenreq_err.de),
- .d (hw2reg.err_code.sfifo_ggenreq_err.d ),
+ .d (hw2reg.err_code.sfifo_ggenreq_err.d),
// to internal hardware
.qe (),
@@ -1197,15 +1216,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_gadstage_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_gadstage_err.de),
- .d (hw2reg.err_code.sfifo_gadstage_err.d ),
+ .d (hw2reg.err_code.sfifo_gadstage_err.d),
// to internal hardware
.qe (),
@@ -1222,15 +1242,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_ggenbits_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_ggenbits_err.de),
- .d (hw2reg.err_code.sfifo_ggenbits_err.d ),
+ .d (hw2reg.err_code.sfifo_ggenbits_err.d),
// to internal hardware
.qe (),
@@ -1247,15 +1268,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_blkenc_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_blkenc_err.de),
- .d (hw2reg.err_code.sfifo_blkenc_err.d ),
+ .d (hw2reg.err_code.sfifo_blkenc_err.d),
// to internal hardware
.qe (),
@@ -1272,15 +1294,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_cmd_stage_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.cmd_stage_sm_err.de),
- .d (hw2reg.err_code.cmd_stage_sm_err.d ),
+ .d (hw2reg.err_code.cmd_stage_sm_err.d),
// to internal hardware
.qe (),
@@ -1297,15 +1320,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_main_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.main_sm_err.de),
- .d (hw2reg.err_code.main_sm_err.d ),
+ .d (hw2reg.err_code.main_sm_err.d),
// to internal hardware
.qe (),
@@ -1322,15 +1346,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_drbg_gen_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.drbg_gen_sm_err.de),
- .d (hw2reg.err_code.drbg_gen_sm_err.d ),
+ .d (hw2reg.err_code.drbg_gen_sm_err.d),
// to internal hardware
.qe (),
@@ -1347,15 +1372,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_drbg_updbe_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.drbg_updbe_sm_err.de),
- .d (hw2reg.err_code.drbg_updbe_sm_err.d ),
+ .d (hw2reg.err_code.drbg_updbe_sm_err.d),
// to internal hardware
.qe (),
@@ -1372,15 +1398,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_drbg_updob_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.drbg_updob_sm_err.de),
- .d (hw2reg.err_code.drbg_updob_sm_err.d ),
+ .d (hw2reg.err_code.drbg_updob_sm_err.d),
// to internal hardware
.qe (),
@@ -1397,15 +1424,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_aes_cipher_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.aes_cipher_sm_err.de),
- .d (hw2reg.err_code.aes_cipher_sm_err.d ),
+ .d (hw2reg.err_code.aes_cipher_sm_err.d),
// to internal hardware
.qe (),
@@ -1422,15 +1450,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_write_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_write_err.de),
- .d (hw2reg.err_code.fifo_write_err.d ),
+ .d (hw2reg.err_code.fifo_write_err.d),
// to internal hardware
.qe (),
@@ -1447,15 +1476,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_read_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_read_err.de),
- .d (hw2reg.err_code.fifo_read_err.d ),
+ .d (hw2reg.err_code.fifo_read_err.d),
// to internal hardware
.qe (),
@@ -1472,15 +1502,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_state_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_state_err.de),
- .d (hw2reg.err_code.fifo_state_err.d ),
+ .d (hw2reg.err_code.fifo_state_err.d),
// to internal hardware
.qe (),
@@ -1498,20 +1529,20 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_err_code_test (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (err_code_test_we & regwen_qs),
.wd (err_code_test_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.err_code_test.qe),
- .q (reg2hw.err_code_test.q ),
+ .q (reg2hw.err_code_test.q),
// to register interface (read)
.qs (err_code_test_qs)
@@ -1525,8 +1556,8 @@
.SWACCESS("WO"),
.RESVAL (2'h0)
) u_sel_tracking_sm (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sel_tracking_sm_we),
@@ -1534,12 +1565,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sel_tracking_sm.q ),
+ .q (reg2hw.sel_tracking_sm.q),
+ // to register interface (read)
.qs ()
);
@@ -1551,15 +1583,16 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_tracking_sm_obs (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.tracking_sm_obs.de),
- .d (hw2reg.tracking_sm_obs.d ),
+ .d (hw2reg.tracking_sm_obs.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/edn/rtl/edn_reg_top.sv b/hw/ip/edn/rtl/edn_reg_top.sv
index 73d306f..9f76649 100644
--- a/hw/ip/edn/rtl/edn_reg_top.sv
+++ b/hw/ip/edn/rtl/edn_reg_top.sv
@@ -171,8 +171,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_edn_cmd_req_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_edn_cmd_req_done_we),
@@ -180,11 +180,11 @@
// from internal hardware
.de (hw2reg.intr_state.edn_cmd_req_done.de),
- .d (hw2reg.intr_state.edn_cmd_req_done.d ),
+ .d (hw2reg.intr_state.edn_cmd_req_done.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.edn_cmd_req_done.q ),
+ .q (reg2hw.intr_state.edn_cmd_req_done.q),
// to register interface (read)
.qs (intr_state_edn_cmd_req_done_qs)
@@ -197,8 +197,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_edn_fatal_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_edn_fatal_err_we),
@@ -206,11 +206,11 @@
// from internal hardware
.de (hw2reg.intr_state.edn_fatal_err.de),
- .d (hw2reg.intr_state.edn_fatal_err.d ),
+ .d (hw2reg.intr_state.edn_fatal_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.edn_fatal_err.q ),
+ .q (reg2hw.intr_state.edn_fatal_err.q),
// to register interface (read)
.qs (intr_state_edn_fatal_err_qs)
@@ -225,8 +225,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_edn_cmd_req_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_edn_cmd_req_done_we),
@@ -234,11 +234,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.edn_cmd_req_done.q ),
+ .q (reg2hw.intr_enable.edn_cmd_req_done.q),
// to register interface (read)
.qs (intr_enable_edn_cmd_req_done_qs)
@@ -251,8 +251,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_edn_fatal_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_edn_fatal_err_we),
@@ -260,11 +260,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.edn_fatal_err.q ),
+ .q (reg2hw.intr_enable.edn_fatal_err.q),
// to register interface (read)
.qs (intr_enable_edn_fatal_err_qs)
@@ -283,7 +283,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.edn_cmd_req_done.qe),
- .q (reg2hw.intr_test.edn_cmd_req_done.q ),
+ .q (reg2hw.intr_test.edn_cmd_req_done.q),
.qs ()
);
@@ -298,7 +298,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.edn_fatal_err.qe),
- .q (reg2hw.intr_test.edn_fatal_err.q ),
+ .q (reg2hw.intr_test.edn_fatal_err.q),
.qs ()
);
@@ -314,7 +314,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.qe),
- .q (reg2hw.alert_test.q ),
+ .q (reg2hw.alert_test.q),
.qs ()
);
@@ -326,8 +326,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regwen_we),
@@ -335,11 +335,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.regwen.q ),
+ .q (reg2hw.regwen.q),
// to register interface (read)
.qs (regwen_qs)
@@ -354,8 +354,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_edn_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_edn_enable_we),
@@ -363,11 +363,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.edn_enable.q ),
+ .q (reg2hw.ctrl.edn_enable.q),
// to register interface (read)
.qs (ctrl_edn_enable_qs)
@@ -380,8 +380,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_cmd_fifo_rst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_cmd_fifo_rst_we),
@@ -389,11 +389,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.cmd_fifo_rst.q ),
+ .q (reg2hw.ctrl.cmd_fifo_rst.q),
// to register interface (read)
.qs (ctrl_cmd_fifo_rst_qs)
@@ -406,8 +406,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ctrl_hw_req_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_hw_req_mode_we),
@@ -415,11 +415,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.hw_req_mode.q ),
+ .q (reg2hw.ctrl.hw_req_mode.q),
// to register interface (read)
.qs (ctrl_hw_req_mode_qs)
@@ -434,8 +434,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_sum_sts_req_mode_sm_sts (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sum_sts_req_mode_sm_sts_we),
@@ -443,7 +443,7 @@
// from internal hardware
.de (hw2reg.sum_sts.req_mode_sm_sts.de),
- .d (hw2reg.sum_sts.req_mode_sm_sts.d ),
+ .d (hw2reg.sum_sts.req_mode_sm_sts.d),
// to internal hardware
.qe (),
@@ -460,8 +460,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_sum_sts_boot_inst_ack (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sum_sts_boot_inst_ack_we),
@@ -469,7 +469,7 @@
// from internal hardware
.de (hw2reg.sum_sts.boot_inst_ack.de),
- .d (hw2reg.sum_sts.boot_inst_ack.d ),
+ .d (hw2reg.sum_sts.boot_inst_ack.d),
// to internal hardware
.qe (),
@@ -486,13 +486,12 @@
.DW (32)
) u_sw_cmd_req (
.re (1'b0),
- // qualified with register enable
.we (sw_cmd_req_we & regwen_qs),
.wd (sw_cmd_req_wd),
.d ('0),
.qre (),
.qe (reg2hw.sw_cmd_req.qe),
- .q (reg2hw.sw_cmd_req.q ),
+ .q (reg2hw.sw_cmd_req.q),
.qs ()
);
@@ -505,15 +504,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_sw_cmd_sts_cmd_rdy (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.sw_cmd_sts.cmd_rdy.de),
- .d (hw2reg.sw_cmd_sts.cmd_rdy.d ),
+ .d (hw2reg.sw_cmd_sts.cmd_rdy.d),
// to internal hardware
.qe (),
@@ -530,15 +530,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_sw_cmd_sts_cmd_sts (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.sw_cmd_sts.cmd_sts.de),
- .d (hw2reg.sw_cmd_sts.cmd_sts.d ),
+ .d (hw2reg.sw_cmd_sts.cmd_sts.d),
// to internal hardware
.qe (),
@@ -555,13 +556,12 @@
.DW (32)
) u_reseed_cmd (
.re (1'b0),
- // qualified with register enable
.we (reseed_cmd_we & regwen_qs),
.wd (reseed_cmd_wd),
.d ('0),
.qre (),
.qe (reg2hw.reseed_cmd.qe),
- .q (reg2hw.reseed_cmd.q ),
+ .q (reg2hw.reseed_cmd.q),
.qs ()
);
@@ -572,13 +572,12 @@
.DW (32)
) u_generate_cmd (
.re (1'b0),
- // qualified with register enable
.we (generate_cmd_we & regwen_qs),
.wd (generate_cmd_wd),
.d ('0),
.qre (),
.qe (reg2hw.generate_cmd.qe),
- .q (reg2hw.generate_cmd.q ),
+ .q (reg2hw.generate_cmd.q),
.qs ()
);
@@ -590,8 +589,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_max_num_reqs_between_reseeds (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (max_num_reqs_between_reseeds_we),
@@ -599,11 +598,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.max_num_reqs_between_reseeds.qe),
- .q (reg2hw.max_num_reqs_between_reseeds.q ),
+ .q (reg2hw.max_num_reqs_between_reseeds.q),
// to register interface (read)
.qs (max_num_reqs_between_reseeds_qs)
@@ -618,15 +617,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_rescmd_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_rescmd_err.de),
- .d (hw2reg.err_code.sfifo_rescmd_err.d ),
+ .d (hw2reg.err_code.sfifo_rescmd_err.d),
// to internal hardware
.qe (),
@@ -643,15 +643,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_gencmd_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_gencmd_err.de),
- .d (hw2reg.err_code.sfifo_gencmd_err.d ),
+ .d (hw2reg.err_code.sfifo_gencmd_err.d),
// to internal hardware
.qe (),
@@ -668,15 +669,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_edn_ack_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.edn_ack_sm_err.de),
- .d (hw2reg.err_code.edn_ack_sm_err.d ),
+ .d (hw2reg.err_code.edn_ack_sm_err.d),
// to internal hardware
.qe (),
@@ -693,15 +695,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_edn_main_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.edn_main_sm_err.de),
- .d (hw2reg.err_code.edn_main_sm_err.d ),
+ .d (hw2reg.err_code.edn_main_sm_err.d),
// to internal hardware
.qe (),
@@ -718,15 +721,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_write_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_write_err.de),
- .d (hw2reg.err_code.fifo_write_err.d ),
+ .d (hw2reg.err_code.fifo_write_err.d),
// to internal hardware
.qe (),
@@ -743,15 +747,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_read_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_read_err.de),
- .d (hw2reg.err_code.fifo_read_err.d ),
+ .d (hw2reg.err_code.fifo_read_err.d),
// to internal hardware
.qe (),
@@ -768,15 +773,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_state_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_state_err.de),
- .d (hw2reg.err_code.fifo_state_err.d ),
+ .d (hw2reg.err_code.fifo_state_err.d),
// to internal hardware
.qe (),
@@ -794,20 +800,20 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_err_code_test (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (err_code_test_we & regwen_qs),
.wd (err_code_test_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.err_code_test.qe),
- .q (reg2hw.err_code_test.q ),
+ .q (reg2hw.err_code_test.q),
// to register interface (read)
.qs (err_code_test_qs)
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
index fef1eb4..e836e20 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
@@ -397,8 +397,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_es_entropy_valid (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_es_entropy_valid_we),
@@ -406,11 +406,11 @@
// from internal hardware
.de (hw2reg.intr_state.es_entropy_valid.de),
- .d (hw2reg.intr_state.es_entropy_valid.d ),
+ .d (hw2reg.intr_state.es_entropy_valid.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.es_entropy_valid.q ),
+ .q (reg2hw.intr_state.es_entropy_valid.q),
// to register interface (read)
.qs (intr_state_es_entropy_valid_qs)
@@ -423,8 +423,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_es_health_test_failed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_es_health_test_failed_we),
@@ -432,11 +432,11 @@
// from internal hardware
.de (hw2reg.intr_state.es_health_test_failed.de),
- .d (hw2reg.intr_state.es_health_test_failed.d ),
+ .d (hw2reg.intr_state.es_health_test_failed.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.es_health_test_failed.q ),
+ .q (reg2hw.intr_state.es_health_test_failed.q),
// to register interface (read)
.qs (intr_state_es_health_test_failed_qs)
@@ -449,8 +449,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_es_observe_fifo_ready (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_es_observe_fifo_ready_we),
@@ -458,11 +458,11 @@
// from internal hardware
.de (hw2reg.intr_state.es_observe_fifo_ready.de),
- .d (hw2reg.intr_state.es_observe_fifo_ready.d ),
+ .d (hw2reg.intr_state.es_observe_fifo_ready.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.es_observe_fifo_ready.q ),
+ .q (reg2hw.intr_state.es_observe_fifo_ready.q),
// to register interface (read)
.qs (intr_state_es_observe_fifo_ready_qs)
@@ -475,8 +475,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_es_fatal_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_es_fatal_err_we),
@@ -484,11 +484,11 @@
// from internal hardware
.de (hw2reg.intr_state.es_fatal_err.de),
- .d (hw2reg.intr_state.es_fatal_err.d ),
+ .d (hw2reg.intr_state.es_fatal_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.es_fatal_err.q ),
+ .q (reg2hw.intr_state.es_fatal_err.q),
// to register interface (read)
.qs (intr_state_es_fatal_err_qs)
@@ -503,8 +503,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_es_entropy_valid (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_es_entropy_valid_we),
@@ -512,11 +512,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.es_entropy_valid.q ),
+ .q (reg2hw.intr_enable.es_entropy_valid.q),
// to register interface (read)
.qs (intr_enable_es_entropy_valid_qs)
@@ -529,8 +529,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_es_health_test_failed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_es_health_test_failed_we),
@@ -538,11 +538,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.es_health_test_failed.q ),
+ .q (reg2hw.intr_enable.es_health_test_failed.q),
// to register interface (read)
.qs (intr_enable_es_health_test_failed_qs)
@@ -555,8 +555,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_es_observe_fifo_ready (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_es_observe_fifo_ready_we),
@@ -564,11 +564,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.es_observe_fifo_ready.q ),
+ .q (reg2hw.intr_enable.es_observe_fifo_ready.q),
// to register interface (read)
.qs (intr_enable_es_observe_fifo_ready_qs)
@@ -581,8 +581,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_es_fatal_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_es_fatal_err_we),
@@ -590,11 +590,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.es_fatal_err.q ),
+ .q (reg2hw.intr_enable.es_fatal_err.q),
// to register interface (read)
.qs (intr_enable_es_fatal_err_qs)
@@ -613,7 +613,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.es_entropy_valid.qe),
- .q (reg2hw.intr_test.es_entropy_valid.q ),
+ .q (reg2hw.intr_test.es_entropy_valid.q),
.qs ()
);
@@ -628,7 +628,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.es_health_test_failed.qe),
- .q (reg2hw.intr_test.es_health_test_failed.q ),
+ .q (reg2hw.intr_test.es_health_test_failed.q),
.qs ()
);
@@ -643,7 +643,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.es_observe_fifo_ready.qe),
- .q (reg2hw.intr_test.es_observe_fifo_ready.q ),
+ .q (reg2hw.intr_test.es_observe_fifo_ready.q),
.qs ()
);
@@ -658,7 +658,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.es_fatal_err.qe),
- .q (reg2hw.intr_test.es_fatal_err.q ),
+ .q (reg2hw.intr_test.es_fatal_err.q),
.qs ()
);
@@ -675,7 +675,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_alert.qe),
- .q (reg2hw.alert_test.recov_alert.q ),
+ .q (reg2hw.alert_test.recov_alert.q),
.qs ()
);
@@ -690,7 +690,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_alert.qe),
- .q (reg2hw.alert_test.fatal_alert.q ),
+ .q (reg2hw.alert_test.fatal_alert.q),
.qs ()
);
@@ -736,8 +736,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_conf_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_enable_we),
@@ -745,11 +745,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.enable.q ),
+ .q (reg2hw.conf.enable.q),
// to register interface (read)
.qs (conf_enable_qs)
@@ -762,8 +762,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_conf_boot_bypass_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_boot_bypass_disable_we),
@@ -771,11 +771,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.boot_bypass_disable.q ),
+ .q (reg2hw.conf.boot_bypass_disable.q),
// to register interface (read)
.qs (conf_boot_bypass_disable_qs)
@@ -788,8 +788,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_conf_repcnt_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_repcnt_disable_we),
@@ -797,11 +797,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.repcnt_disable.q ),
+ .q (reg2hw.conf.repcnt_disable.q),
// to register interface (read)
.qs (conf_repcnt_disable_qs)
@@ -814,8 +814,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_conf_adaptp_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_adaptp_disable_we),
@@ -823,11 +823,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.adaptp_disable.q ),
+ .q (reg2hw.conf.adaptp_disable.q),
// to register interface (read)
.qs (conf_adaptp_disable_qs)
@@ -840,8 +840,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_conf_bucket_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_bucket_disable_we),
@@ -849,11 +849,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.bucket_disable.q ),
+ .q (reg2hw.conf.bucket_disable.q),
// to register interface (read)
.qs (conf_bucket_disable_qs)
@@ -866,8 +866,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_conf_markov_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_markov_disable_we),
@@ -875,11 +875,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.markov_disable.q ),
+ .q (reg2hw.conf.markov_disable.q),
// to register interface (read)
.qs (conf_markov_disable_qs)
@@ -892,8 +892,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_conf_health_test_clr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_health_test_clr_we),
@@ -901,11 +901,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.health_test_clr.q ),
+ .q (reg2hw.conf.health_test_clr.q),
// to register interface (read)
.qs (conf_health_test_clr_qs)
@@ -918,8 +918,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_conf_rng_bit_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_rng_bit_en_we),
@@ -927,11 +927,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.rng_bit_en.q ),
+ .q (reg2hw.conf.rng_bit_en.q),
// to register interface (read)
.qs (conf_rng_bit_en_qs)
@@ -944,8 +944,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_conf_rng_bit_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_rng_bit_sel_we),
@@ -953,11 +953,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.rng_bit_sel.q ),
+ .q (reg2hw.conf.rng_bit_sel.q),
// to register interface (read)
.qs (conf_rng_bit_sel_qs)
@@ -970,8 +970,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_conf_extht_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_extht_enable_we),
@@ -979,11 +979,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.extht_enable.q ),
+ .q (reg2hw.conf.extht_enable.q),
// to register interface (read)
.qs (conf_extht_enable_qs)
@@ -996,8 +996,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_conf_repcnts_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (conf_repcnts_disable_we),
@@ -1005,11 +1005,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.conf.repcnts_disable.q ),
+ .q (reg2hw.conf.repcnts_disable.q),
// to register interface (read)
.qs (conf_repcnts_disable_qs)
@@ -1023,8 +1023,8 @@
.SWACCESS("RW"),
.RESVAL (16'h4)
) u_rate (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rate_we),
@@ -1032,11 +1032,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rate.q ),
+ .q (reg2hw.rate.q),
// to register interface (read)
.qs (rate_qs)
@@ -1051,20 +1051,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_entropy_control_es_route (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (entropy_control_es_route_we & regwen_qs),
.wd (entropy_control_es_route_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.entropy_control.es_route.q ),
+ .q (reg2hw.entropy_control.es_route.q),
// to register interface (read)
.qs (entropy_control_es_route_qs)
@@ -1077,20 +1077,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_entropy_control_es_type (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (entropy_control_es_type_we & regwen_qs),
.wd (entropy_control_es_type_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.entropy_control.es_type.q ),
+ .q (reg2hw.entropy_control.es_type.q),
// to register interface (read)
.qs (entropy_control_es_type_qs)
@@ -1108,7 +1108,7 @@
.d (hw2reg.entropy_data.d),
.qre (reg2hw.entropy_data.re),
.qe (),
- .q (reg2hw.entropy_data.q ),
+ .q (reg2hw.entropy_data.q),
.qs (entropy_data_qs)
);
@@ -1121,20 +1121,20 @@
.SWACCESS("RW"),
.RESVAL (16'h200)
) u_health_test_windows_fips_window (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (health_test_windows_fips_window_we & regwen_qs),
.wd (health_test_windows_fips_window_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.health_test_windows.fips_window.q ),
+ .q (reg2hw.health_test_windows.fips_window.q),
// to register interface (read)
.qs (health_test_windows_fips_window_qs)
@@ -1147,20 +1147,20 @@
.SWACCESS("RW"),
.RESVAL (16'h60)
) u_health_test_windows_bypass_window (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (health_test_windows_bypass_window_we & regwen_qs),
.wd (health_test_windows_bypass_window_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.health_test_windows.bypass_window.q ),
+ .q (reg2hw.health_test_windows.bypass_window.q),
// to register interface (read)
.qs (health_test_windows_bypass_window_qs)
@@ -1174,13 +1174,12 @@
.DW (16)
) u_repcnt_thresholds_fips_thresh (
.re (repcnt_thresholds_fips_thresh_re),
- // qualified with register enable
.we (repcnt_thresholds_fips_thresh_we & regwen_qs),
.wd (repcnt_thresholds_fips_thresh_wd),
.d (hw2reg.repcnt_thresholds.fips_thresh.d),
.qre (),
.qe (reg2hw.repcnt_thresholds.fips_thresh.qe),
- .q (reg2hw.repcnt_thresholds.fips_thresh.q ),
+ .q (reg2hw.repcnt_thresholds.fips_thresh.q),
.qs (repcnt_thresholds_fips_thresh_qs)
);
@@ -1190,13 +1189,12 @@
.DW (16)
) u_repcnt_thresholds_bypass_thresh (
.re (repcnt_thresholds_bypass_thresh_re),
- // qualified with register enable
.we (repcnt_thresholds_bypass_thresh_we & regwen_qs),
.wd (repcnt_thresholds_bypass_thresh_wd),
.d (hw2reg.repcnt_thresholds.bypass_thresh.d),
.qre (),
.qe (reg2hw.repcnt_thresholds.bypass_thresh.qe),
- .q (reg2hw.repcnt_thresholds.bypass_thresh.q ),
+ .q (reg2hw.repcnt_thresholds.bypass_thresh.q),
.qs (repcnt_thresholds_bypass_thresh_qs)
);
@@ -1208,13 +1206,12 @@
.DW (16)
) u_repcnts_thresholds_fips_thresh (
.re (repcnts_thresholds_fips_thresh_re),
- // qualified with register enable
.we (repcnts_thresholds_fips_thresh_we & regwen_qs),
.wd (repcnts_thresholds_fips_thresh_wd),
.d (hw2reg.repcnts_thresholds.fips_thresh.d),
.qre (),
.qe (reg2hw.repcnts_thresholds.fips_thresh.qe),
- .q (reg2hw.repcnts_thresholds.fips_thresh.q ),
+ .q (reg2hw.repcnts_thresholds.fips_thresh.q),
.qs (repcnts_thresholds_fips_thresh_qs)
);
@@ -1224,13 +1221,12 @@
.DW (16)
) u_repcnts_thresholds_bypass_thresh (
.re (repcnts_thresholds_bypass_thresh_re),
- // qualified with register enable
.we (repcnts_thresholds_bypass_thresh_we & regwen_qs),
.wd (repcnts_thresholds_bypass_thresh_wd),
.d (hw2reg.repcnts_thresholds.bypass_thresh.d),
.qre (),
.qe (reg2hw.repcnts_thresholds.bypass_thresh.qe),
- .q (reg2hw.repcnts_thresholds.bypass_thresh.q ),
+ .q (reg2hw.repcnts_thresholds.bypass_thresh.q),
.qs (repcnts_thresholds_bypass_thresh_qs)
);
@@ -1242,13 +1238,12 @@
.DW (16)
) u_adaptp_hi_thresholds_fips_thresh (
.re (adaptp_hi_thresholds_fips_thresh_re),
- // qualified with register enable
.we (adaptp_hi_thresholds_fips_thresh_we & regwen_qs),
.wd (adaptp_hi_thresholds_fips_thresh_wd),
.d (hw2reg.adaptp_hi_thresholds.fips_thresh.d),
.qre (),
.qe (reg2hw.adaptp_hi_thresholds.fips_thresh.qe),
- .q (reg2hw.adaptp_hi_thresholds.fips_thresh.q ),
+ .q (reg2hw.adaptp_hi_thresholds.fips_thresh.q),
.qs (adaptp_hi_thresholds_fips_thresh_qs)
);
@@ -1258,13 +1253,12 @@
.DW (16)
) u_adaptp_hi_thresholds_bypass_thresh (
.re (adaptp_hi_thresholds_bypass_thresh_re),
- // qualified with register enable
.we (adaptp_hi_thresholds_bypass_thresh_we & regwen_qs),
.wd (adaptp_hi_thresholds_bypass_thresh_wd),
.d (hw2reg.adaptp_hi_thresholds.bypass_thresh.d),
.qre (),
.qe (reg2hw.adaptp_hi_thresholds.bypass_thresh.qe),
- .q (reg2hw.adaptp_hi_thresholds.bypass_thresh.q ),
+ .q (reg2hw.adaptp_hi_thresholds.bypass_thresh.q),
.qs (adaptp_hi_thresholds_bypass_thresh_qs)
);
@@ -1276,13 +1270,12 @@
.DW (16)
) u_adaptp_lo_thresholds_fips_thresh (
.re (adaptp_lo_thresholds_fips_thresh_re),
- // qualified with register enable
.we (adaptp_lo_thresholds_fips_thresh_we & regwen_qs),
.wd (adaptp_lo_thresholds_fips_thresh_wd),
.d (hw2reg.adaptp_lo_thresholds.fips_thresh.d),
.qre (),
.qe (reg2hw.adaptp_lo_thresholds.fips_thresh.qe),
- .q (reg2hw.adaptp_lo_thresholds.fips_thresh.q ),
+ .q (reg2hw.adaptp_lo_thresholds.fips_thresh.q),
.qs (adaptp_lo_thresholds_fips_thresh_qs)
);
@@ -1292,13 +1285,12 @@
.DW (16)
) u_adaptp_lo_thresholds_bypass_thresh (
.re (adaptp_lo_thresholds_bypass_thresh_re),
- // qualified with register enable
.we (adaptp_lo_thresholds_bypass_thresh_we & regwen_qs),
.wd (adaptp_lo_thresholds_bypass_thresh_wd),
.d (hw2reg.adaptp_lo_thresholds.bypass_thresh.d),
.qre (),
.qe (reg2hw.adaptp_lo_thresholds.bypass_thresh.qe),
- .q (reg2hw.adaptp_lo_thresholds.bypass_thresh.q ),
+ .q (reg2hw.adaptp_lo_thresholds.bypass_thresh.q),
.qs (adaptp_lo_thresholds_bypass_thresh_qs)
);
@@ -1310,13 +1302,12 @@
.DW (16)
) u_bucket_thresholds_fips_thresh (
.re (bucket_thresholds_fips_thresh_re),
- // qualified with register enable
.we (bucket_thresholds_fips_thresh_we & regwen_qs),
.wd (bucket_thresholds_fips_thresh_wd),
.d (hw2reg.bucket_thresholds.fips_thresh.d),
.qre (),
.qe (reg2hw.bucket_thresholds.fips_thresh.qe),
- .q (reg2hw.bucket_thresholds.fips_thresh.q ),
+ .q (reg2hw.bucket_thresholds.fips_thresh.q),
.qs (bucket_thresholds_fips_thresh_qs)
);
@@ -1326,13 +1317,12 @@
.DW (16)
) u_bucket_thresholds_bypass_thresh (
.re (bucket_thresholds_bypass_thresh_re),
- // qualified with register enable
.we (bucket_thresholds_bypass_thresh_we & regwen_qs),
.wd (bucket_thresholds_bypass_thresh_wd),
.d (hw2reg.bucket_thresholds.bypass_thresh.d),
.qre (),
.qe (reg2hw.bucket_thresholds.bypass_thresh.qe),
- .q (reg2hw.bucket_thresholds.bypass_thresh.q ),
+ .q (reg2hw.bucket_thresholds.bypass_thresh.q),
.qs (bucket_thresholds_bypass_thresh_qs)
);
@@ -1344,13 +1334,12 @@
.DW (16)
) u_markov_hi_thresholds_fips_thresh (
.re (markov_hi_thresholds_fips_thresh_re),
- // qualified with register enable
.we (markov_hi_thresholds_fips_thresh_we & regwen_qs),
.wd (markov_hi_thresholds_fips_thresh_wd),
.d (hw2reg.markov_hi_thresholds.fips_thresh.d),
.qre (),
.qe (reg2hw.markov_hi_thresholds.fips_thresh.qe),
- .q (reg2hw.markov_hi_thresholds.fips_thresh.q ),
+ .q (reg2hw.markov_hi_thresholds.fips_thresh.q),
.qs (markov_hi_thresholds_fips_thresh_qs)
);
@@ -1360,13 +1349,12 @@
.DW (16)
) u_markov_hi_thresholds_bypass_thresh (
.re (markov_hi_thresholds_bypass_thresh_re),
- // qualified with register enable
.we (markov_hi_thresholds_bypass_thresh_we & regwen_qs),
.wd (markov_hi_thresholds_bypass_thresh_wd),
.d (hw2reg.markov_hi_thresholds.bypass_thresh.d),
.qre (),
.qe (reg2hw.markov_hi_thresholds.bypass_thresh.qe),
- .q (reg2hw.markov_hi_thresholds.bypass_thresh.q ),
+ .q (reg2hw.markov_hi_thresholds.bypass_thresh.q),
.qs (markov_hi_thresholds_bypass_thresh_qs)
);
@@ -1378,13 +1366,12 @@
.DW (16)
) u_markov_lo_thresholds_fips_thresh (
.re (markov_lo_thresholds_fips_thresh_re),
- // qualified with register enable
.we (markov_lo_thresholds_fips_thresh_we & regwen_qs),
.wd (markov_lo_thresholds_fips_thresh_wd),
.d (hw2reg.markov_lo_thresholds.fips_thresh.d),
.qre (),
.qe (reg2hw.markov_lo_thresholds.fips_thresh.qe),
- .q (reg2hw.markov_lo_thresholds.fips_thresh.q ),
+ .q (reg2hw.markov_lo_thresholds.fips_thresh.q),
.qs (markov_lo_thresholds_fips_thresh_qs)
);
@@ -1394,13 +1381,12 @@
.DW (16)
) u_markov_lo_thresholds_bypass_thresh (
.re (markov_lo_thresholds_bypass_thresh_re),
- // qualified with register enable
.we (markov_lo_thresholds_bypass_thresh_we & regwen_qs),
.wd (markov_lo_thresholds_bypass_thresh_wd),
.d (hw2reg.markov_lo_thresholds.bypass_thresh.d),
.qre (),
.qe (reg2hw.markov_lo_thresholds.bypass_thresh.qe),
- .q (reg2hw.markov_lo_thresholds.bypass_thresh.q ),
+ .q (reg2hw.markov_lo_thresholds.bypass_thresh.q),
.qs (markov_lo_thresholds_bypass_thresh_qs)
);
@@ -1412,13 +1398,12 @@
.DW (16)
) u_extht_hi_thresholds_fips_thresh (
.re (extht_hi_thresholds_fips_thresh_re),
- // qualified with register enable
.we (extht_hi_thresholds_fips_thresh_we & regwen_qs),
.wd (extht_hi_thresholds_fips_thresh_wd),
.d (hw2reg.extht_hi_thresholds.fips_thresh.d),
.qre (),
.qe (reg2hw.extht_hi_thresholds.fips_thresh.qe),
- .q (reg2hw.extht_hi_thresholds.fips_thresh.q ),
+ .q (reg2hw.extht_hi_thresholds.fips_thresh.q),
.qs (extht_hi_thresholds_fips_thresh_qs)
);
@@ -1428,13 +1413,12 @@
.DW (16)
) u_extht_hi_thresholds_bypass_thresh (
.re (extht_hi_thresholds_bypass_thresh_re),
- // qualified with register enable
.we (extht_hi_thresholds_bypass_thresh_we & regwen_qs),
.wd (extht_hi_thresholds_bypass_thresh_wd),
.d (hw2reg.extht_hi_thresholds.bypass_thresh.d),
.qre (),
.qe (reg2hw.extht_hi_thresholds.bypass_thresh.qe),
- .q (reg2hw.extht_hi_thresholds.bypass_thresh.q ),
+ .q (reg2hw.extht_hi_thresholds.bypass_thresh.q),
.qs (extht_hi_thresholds_bypass_thresh_qs)
);
@@ -1446,13 +1430,12 @@
.DW (16)
) u_extht_lo_thresholds_fips_thresh (
.re (extht_lo_thresholds_fips_thresh_re),
- // qualified with register enable
.we (extht_lo_thresholds_fips_thresh_we & regwen_qs),
.wd (extht_lo_thresholds_fips_thresh_wd),
.d (hw2reg.extht_lo_thresholds.fips_thresh.d),
.qre (),
.qe (reg2hw.extht_lo_thresholds.fips_thresh.qe),
- .q (reg2hw.extht_lo_thresholds.fips_thresh.q ),
+ .q (reg2hw.extht_lo_thresholds.fips_thresh.q),
.qs (extht_lo_thresholds_fips_thresh_qs)
);
@@ -1462,13 +1445,12 @@
.DW (16)
) u_extht_lo_thresholds_bypass_thresh (
.re (extht_lo_thresholds_bypass_thresh_re),
- // qualified with register enable
.we (extht_lo_thresholds_bypass_thresh_we & regwen_qs),
.wd (extht_lo_thresholds_bypass_thresh_wd),
.d (hw2reg.extht_lo_thresholds.bypass_thresh.d),
.qre (),
.qe (reg2hw.extht_lo_thresholds.bypass_thresh.qe),
- .q (reg2hw.extht_lo_thresholds.bypass_thresh.q ),
+ .q (reg2hw.extht_lo_thresholds.bypass_thresh.q),
.qs (extht_lo_thresholds_bypass_thresh_qs)
);
@@ -1912,20 +1894,20 @@
.SWACCESS("RW"),
.RESVAL (32'h2)
) u_alert_threshold (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_threshold_we & regwen_qs),
.wd (alert_threshold_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_threshold.q ),
+ .q (reg2hw.alert_threshold.q),
// to register interface (read)
.qs (alert_threshold_qs)
@@ -2095,20 +2077,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_fw_ov_control_fw_ov_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (fw_ov_control_fw_ov_mode_we & regwen_qs),
.wd (fw_ov_control_fw_ov_mode_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fw_ov_control.fw_ov_mode.q ),
+ .q (reg2hw.fw_ov_control.fw_ov_mode.q),
// to register interface (read)
.qs (fw_ov_control_fw_ov_mode_qs)
@@ -2121,20 +2103,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_fw_ov_control_fw_ov_entropy_insert (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (fw_ov_control_fw_ov_entropy_insert_we & regwen_qs),
.wd (fw_ov_control_fw_ov_entropy_insert_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fw_ov_control.fw_ov_entropy_insert.q ),
+ .q (reg2hw.fw_ov_control.fw_ov_entropy_insert.q),
// to register interface (read)
.qs (fw_ov_control_fw_ov_entropy_insert_qs)
@@ -2152,7 +2134,7 @@
.d (hw2reg.fw_ov_rd_data.d),
.qre (reg2hw.fw_ov_rd_data.re),
.qe (),
- .q (reg2hw.fw_ov_rd_data.q ),
+ .q (reg2hw.fw_ov_rd_data.q),
.qs (fw_ov_rd_data_qs)
);
@@ -2168,7 +2150,7 @@
.d ('0),
.qre (),
.qe (reg2hw.fw_ov_wr_data.qe),
- .q (reg2hw.fw_ov_wr_data.q ),
+ .q (reg2hw.fw_ov_wr_data.q),
.qs ()
);
@@ -2180,20 +2162,20 @@
.SWACCESS("RW"),
.RESVAL (7'h20)
) u_observe_fifo_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (observe_fifo_thresh_we & regwen_qs),
.wd (observe_fifo_thresh_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.observe_fifo_thresh.q ),
+ .q (reg2hw.observe_fifo_thresh.q),
// to register interface (read)
.qs (observe_fifo_thresh_qs)
@@ -2329,20 +2311,20 @@
.SWACCESS("RW"),
.RESVAL (4'hb)
) u_seed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (seed_we & regwen_qs),
.wd (seed_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.seed.q ),
+ .q (reg2hw.seed.q),
// to register interface (read)
.qs (seed_qs)
@@ -2357,15 +2339,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_esrng_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_esrng_err.de),
- .d (hw2reg.err_code.sfifo_esrng_err.d ),
+ .d (hw2reg.err_code.sfifo_esrng_err.d),
// to internal hardware
.qe (),
@@ -2382,15 +2365,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_observe_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_observe_err.de),
- .d (hw2reg.err_code.sfifo_observe_err.d ),
+ .d (hw2reg.err_code.sfifo_observe_err.d),
// to internal hardware
.qe (),
@@ -2407,15 +2391,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_esfinal_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.sfifo_esfinal_err.de),
- .d (hw2reg.err_code.sfifo_esfinal_err.d ),
+ .d (hw2reg.err_code.sfifo_esfinal_err.d),
// to internal hardware
.qe (),
@@ -2432,15 +2417,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_es_ack_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.es_ack_sm_err.de),
- .d (hw2reg.err_code.es_ack_sm_err.d ),
+ .d (hw2reg.err_code.es_ack_sm_err.d),
// to internal hardware
.qe (),
@@ -2457,15 +2443,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_es_main_sm_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.es_main_sm_err.de),
- .d (hw2reg.err_code.es_main_sm_err.d ),
+ .d (hw2reg.err_code.es_main_sm_err.d),
// to internal hardware
.qe (),
@@ -2482,15 +2469,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_write_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_write_err.de),
- .d (hw2reg.err_code.fifo_write_err.d ),
+ .d (hw2reg.err_code.fifo_write_err.d),
// to internal hardware
.qe (),
@@ -2507,15 +2495,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_read_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_read_err.de),
- .d (hw2reg.err_code.fifo_read_err.d ),
+ .d (hw2reg.err_code.fifo_read_err.d),
// to internal hardware
.qe (),
@@ -2532,15 +2521,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_state_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.fifo_state_err.de),
- .d (hw2reg.err_code.fifo_state_err.d ),
+ .d (hw2reg.err_code.fifo_state_err.d),
// to internal hardware
.qe (),
@@ -2558,20 +2548,20 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_err_code_test (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (err_code_test_we & regwen_qs),
.wd (err_code_test_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.err_code_test.qe),
- .q (reg2hw.err_code_test.q ),
+ .q (reg2hw.err_code_test.q),
// to register interface (read)
.qs (err_code_test_qs)
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
index 333f380..ec67358 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_core_reg_top.sv
@@ -1231,8 +1231,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_prog_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_prog_empty_we),
@@ -1240,11 +1240,11 @@
// from internal hardware
.de (hw2reg.intr_state.prog_empty.de),
- .d (hw2reg.intr_state.prog_empty.d ),
+ .d (hw2reg.intr_state.prog_empty.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.prog_empty.q ),
+ .q (reg2hw.intr_state.prog_empty.q),
// to register interface (read)
.qs (intr_state_prog_empty_qs)
@@ -1257,8 +1257,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_prog_lvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_prog_lvl_we),
@@ -1266,11 +1266,11 @@
// from internal hardware
.de (hw2reg.intr_state.prog_lvl.de),
- .d (hw2reg.intr_state.prog_lvl.d ),
+ .d (hw2reg.intr_state.prog_lvl.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.prog_lvl.q ),
+ .q (reg2hw.intr_state.prog_lvl.q),
// to register interface (read)
.qs (intr_state_prog_lvl_qs)
@@ -1283,8 +1283,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rd_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rd_full_we),
@@ -1292,11 +1292,11 @@
// from internal hardware
.de (hw2reg.intr_state.rd_full.de),
- .d (hw2reg.intr_state.rd_full.d ),
+ .d (hw2reg.intr_state.rd_full.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rd_full.q ),
+ .q (reg2hw.intr_state.rd_full.q),
// to register interface (read)
.qs (intr_state_rd_full_qs)
@@ -1309,8 +1309,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rd_lvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rd_lvl_we),
@@ -1318,11 +1318,11 @@
// from internal hardware
.de (hw2reg.intr_state.rd_lvl.de),
- .d (hw2reg.intr_state.rd_lvl.d ),
+ .d (hw2reg.intr_state.rd_lvl.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rd_lvl.q ),
+ .q (reg2hw.intr_state.rd_lvl.q),
// to register interface (read)
.qs (intr_state_rd_lvl_qs)
@@ -1335,8 +1335,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_op_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_op_done_we),
@@ -1344,11 +1344,11 @@
// from internal hardware
.de (hw2reg.intr_state.op_done.de),
- .d (hw2reg.intr_state.op_done.d ),
+ .d (hw2reg.intr_state.op_done.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.op_done.q ),
+ .q (reg2hw.intr_state.op_done.q),
// to register interface (read)
.qs (intr_state_op_done_qs)
@@ -1361,8 +1361,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_err_we),
@@ -1370,11 +1370,11 @@
// from internal hardware
.de (hw2reg.intr_state.err.de),
- .d (hw2reg.intr_state.err.d ),
+ .d (hw2reg.intr_state.err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.err.q ),
+ .q (reg2hw.intr_state.err.q),
// to register interface (read)
.qs (intr_state_err_qs)
@@ -1389,8 +1389,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_prog_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_prog_empty_we),
@@ -1398,11 +1398,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.prog_empty.q ),
+ .q (reg2hw.intr_enable.prog_empty.q),
// to register interface (read)
.qs (intr_enable_prog_empty_qs)
@@ -1415,8 +1415,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_prog_lvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_prog_lvl_we),
@@ -1424,11 +1424,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.prog_lvl.q ),
+ .q (reg2hw.intr_enable.prog_lvl.q),
// to register interface (read)
.qs (intr_enable_prog_lvl_qs)
@@ -1441,8 +1441,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rd_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rd_full_we),
@@ -1450,11 +1450,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rd_full.q ),
+ .q (reg2hw.intr_enable.rd_full.q),
// to register interface (read)
.qs (intr_enable_rd_full_qs)
@@ -1467,8 +1467,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rd_lvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rd_lvl_we),
@@ -1476,11 +1476,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rd_lvl.q ),
+ .q (reg2hw.intr_enable.rd_lvl.q),
// to register interface (read)
.qs (intr_enable_rd_lvl_qs)
@@ -1493,8 +1493,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_op_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_op_done_we),
@@ -1502,11 +1502,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.op_done.q ),
+ .q (reg2hw.intr_enable.op_done.q),
// to register interface (read)
.qs (intr_enable_op_done_qs)
@@ -1519,8 +1519,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_err_we),
@@ -1528,11 +1528,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.err.q ),
+ .q (reg2hw.intr_enable.err.q),
// to register interface (read)
.qs (intr_enable_err_qs)
@@ -1551,7 +1551,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.prog_empty.qe),
- .q (reg2hw.intr_test.prog_empty.q ),
+ .q (reg2hw.intr_test.prog_empty.q),
.qs ()
);
@@ -1566,7 +1566,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.prog_lvl.qe),
- .q (reg2hw.intr_test.prog_lvl.q ),
+ .q (reg2hw.intr_test.prog_lvl.q),
.qs ()
);
@@ -1581,7 +1581,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rd_full.qe),
- .q (reg2hw.intr_test.rd_full.q ),
+ .q (reg2hw.intr_test.rd_full.q),
.qs ()
);
@@ -1596,7 +1596,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rd_lvl.qe),
- .q (reg2hw.intr_test.rd_lvl.q ),
+ .q (reg2hw.intr_test.rd_lvl.q),
.qs ()
);
@@ -1611,7 +1611,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.op_done.qe),
- .q (reg2hw.intr_test.op_done.q ),
+ .q (reg2hw.intr_test.op_done.q),
.qs ()
);
@@ -1626,7 +1626,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.err.qe),
- .q (reg2hw.intr_test.err.q ),
+ .q (reg2hw.intr_test.err.q),
.qs ()
);
@@ -1643,7 +1643,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_err.qe),
- .q (reg2hw.alert_test.recov_err.q ),
+ .q (reg2hw.alert_test.recov_err.q),
.qs ()
);
@@ -1658,7 +1658,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_mp_err.qe),
- .q (reg2hw.alert_test.recov_mp_err.q ),
+ .q (reg2hw.alert_test.recov_mp_err.q),
.qs ()
);
@@ -1673,7 +1673,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_ecc_err.qe),
- .q (reg2hw.alert_test.recov_ecc_err.q ),
+ .q (reg2hw.alert_test.recov_ecc_err.q),
.qs ()
);
@@ -1688,7 +1688,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_intg_err.qe),
- .q (reg2hw.alert_test.fatal_intg_err.q ),
+ .q (reg2hw.alert_test.fatal_intg_err.q),
.qs ()
);
@@ -1700,8 +1700,8 @@
.SWACCESS("W1S"),
.RESVAL (1'h0)
) u_init (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (init_we),
@@ -1709,11 +1709,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.init.q ),
+ .q (reg2hw.init.q),
// to register interface (read)
.qs (init_qs)
@@ -1744,20 +1744,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_start (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_start_we & ctrl_regwen_qs),
.wd (control_start_wd),
// from internal hardware
.de (hw2reg.control.start.de),
- .d (hw2reg.control.start.d ),
+ .d (hw2reg.control.start.d),
// to internal hardware
.qe (),
- .q (reg2hw.control.start.q ),
+ .q (reg2hw.control.start.q),
// to register interface (read)
.qs (control_start_qs)
@@ -1770,20 +1770,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_control_op (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_op_we & ctrl_regwen_qs),
.wd (control_op_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.op.q ),
+ .q (reg2hw.control.op.q),
// to register interface (read)
.qs (control_op_qs)
@@ -1796,20 +1796,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_prog_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_prog_sel_we & ctrl_regwen_qs),
.wd (control_prog_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.prog_sel.q ),
+ .q (reg2hw.control.prog_sel.q),
// to register interface (read)
.qs (control_prog_sel_qs)
@@ -1822,20 +1822,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_erase_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_erase_sel_we & ctrl_regwen_qs),
.wd (control_erase_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.erase_sel.q ),
+ .q (reg2hw.control.erase_sel.q),
// to register interface (read)
.qs (control_erase_sel_qs)
@@ -1848,20 +1848,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_partition_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_partition_sel_we & ctrl_regwen_qs),
.wd (control_partition_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.partition_sel.q ),
+ .q (reg2hw.control.partition_sel.q),
// to register interface (read)
.qs (control_partition_sel_qs)
@@ -1874,20 +1874,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_control_info_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_info_sel_we & ctrl_regwen_qs),
.wd (control_info_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.info_sel.q ),
+ .q (reg2hw.control.info_sel.q),
// to register interface (read)
.qs (control_info_sel_qs)
@@ -1900,20 +1900,20 @@
.SWACCESS("RW"),
.RESVAL (12'h0)
) u_control_num (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_num_we & ctrl_regwen_qs),
.wd (control_num_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.num.q ),
+ .q (reg2hw.control.num.q),
// to register interface (read)
.qs (control_num_qs)
@@ -1927,8 +1927,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_addr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (addr_we),
@@ -1936,11 +1936,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.addr.q ),
+ .q (reg2hw.addr.q),
// to register interface (read)
.qs (addr_qs)
@@ -1955,8 +1955,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_prog_type_en_normal (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prog_type_en_normal_we),
@@ -1964,11 +1964,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prog_type_en.normal.q ),
+ .q (reg2hw.prog_type_en.normal.q),
// to register interface (read)
.qs (prog_type_en_normal_qs)
@@ -1981,8 +1981,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_prog_type_en_repair (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prog_type_en_repair_we),
@@ -1990,11 +1990,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prog_type_en.repair.q ),
+ .q (reg2hw.prog_type_en.repair.q),
// to register interface (read)
.qs (prog_type_en_repair_qs)
@@ -2008,8 +2008,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_erase_suspend (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (erase_suspend_we),
@@ -2017,11 +2017,11 @@
// from internal hardware
.de (hw2reg.erase_suspend.de),
- .d (hw2reg.erase_suspend.d ),
+ .d (hw2reg.erase_suspend.d),
// to internal hardware
.qe (),
- .q (reg2hw.erase_suspend.q ),
+ .q (reg2hw.erase_suspend.q),
// to register interface (read)
.qs (erase_suspend_qs)
@@ -2037,8 +2037,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_0_we),
@@ -2046,7 +2046,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2064,8 +2064,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_1_we),
@@ -2073,7 +2073,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2091,8 +2091,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_2_we),
@@ -2100,7 +2100,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2118,8 +2118,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_3_we),
@@ -2127,7 +2127,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2145,8 +2145,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_4_we),
@@ -2154,7 +2154,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2172,8 +2172,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_5_we),
@@ -2181,7 +2181,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2199,8 +2199,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_6_we),
@@ -2208,7 +2208,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2226,8 +2226,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_7_we),
@@ -2235,7 +2235,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2256,20 +2256,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].en.q ),
+ .q (reg2hw.mp_region_cfg[0].en.q),
// to register interface (read)
.qs (mp_region_cfg_0_en_0_qs)
@@ -2282,20 +2282,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_rd_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[0].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_rd_en_0_qs)
@@ -2308,20 +2308,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_prog_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[0].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_prog_en_0_qs)
@@ -2334,20 +2334,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_erase_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[0].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_erase_en_0_qs)
@@ -2360,20 +2360,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_scramble_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[0].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_scramble_en_0_qs)
@@ -2386,20 +2386,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_ecc_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[0].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_ecc_en_0_qs)
@@ -2412,20 +2412,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_he_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].he_en.q ),
+ .q (reg2hw.mp_region_cfg[0].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_he_en_0_qs)
@@ -2438,20 +2438,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_0_base_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_base_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_base_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].base.q ),
+ .q (reg2hw.mp_region_cfg[0].base.q),
// to register interface (read)
.qs (mp_region_cfg_0_base_0_qs)
@@ -2464,20 +2464,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_0_size_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_size_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_size_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].size.q ),
+ .q (reg2hw.mp_region_cfg[0].size.q),
// to register interface (read)
.qs (mp_region_cfg_0_size_0_qs)
@@ -2493,20 +2493,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].en.q ),
+ .q (reg2hw.mp_region_cfg[1].en.q),
// to register interface (read)
.qs (mp_region_cfg_1_en_1_qs)
@@ -2519,20 +2519,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_rd_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[1].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_rd_en_1_qs)
@@ -2545,20 +2545,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_prog_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[1].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_prog_en_1_qs)
@@ -2571,20 +2571,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_erase_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[1].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_erase_en_1_qs)
@@ -2597,20 +2597,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_scramble_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[1].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_scramble_en_1_qs)
@@ -2623,20 +2623,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_ecc_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[1].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_ecc_en_1_qs)
@@ -2649,20 +2649,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_he_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].he_en.q ),
+ .q (reg2hw.mp_region_cfg[1].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_he_en_1_qs)
@@ -2675,20 +2675,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_1_base_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_base_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_base_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].base.q ),
+ .q (reg2hw.mp_region_cfg[1].base.q),
// to register interface (read)
.qs (mp_region_cfg_1_base_1_qs)
@@ -2701,20 +2701,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_1_size_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_size_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_size_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].size.q ),
+ .q (reg2hw.mp_region_cfg[1].size.q),
// to register interface (read)
.qs (mp_region_cfg_1_size_1_qs)
@@ -2730,20 +2730,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].en.q ),
+ .q (reg2hw.mp_region_cfg[2].en.q),
// to register interface (read)
.qs (mp_region_cfg_2_en_2_qs)
@@ -2756,20 +2756,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_rd_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_rd_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_rd_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[2].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_rd_en_2_qs)
@@ -2782,20 +2782,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_prog_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_prog_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_prog_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[2].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_prog_en_2_qs)
@@ -2808,20 +2808,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_erase_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_erase_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_erase_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[2].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_erase_en_2_qs)
@@ -2834,20 +2834,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_scramble_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_scramble_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_scramble_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[2].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_scramble_en_2_qs)
@@ -2860,20 +2860,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_ecc_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_ecc_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_ecc_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[2].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_ecc_en_2_qs)
@@ -2886,20 +2886,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_he_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_he_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_he_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].he_en.q ),
+ .q (reg2hw.mp_region_cfg[2].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_he_en_2_qs)
@@ -2912,20 +2912,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_2_base_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_base_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_base_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].base.q ),
+ .q (reg2hw.mp_region_cfg[2].base.q),
// to register interface (read)
.qs (mp_region_cfg_2_base_2_qs)
@@ -2938,20 +2938,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_2_size_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_size_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_size_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].size.q ),
+ .q (reg2hw.mp_region_cfg[2].size.q),
// to register interface (read)
.qs (mp_region_cfg_2_size_2_qs)
@@ -2967,20 +2967,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].en.q ),
+ .q (reg2hw.mp_region_cfg[3].en.q),
// to register interface (read)
.qs (mp_region_cfg_3_en_3_qs)
@@ -2993,20 +2993,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_rd_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_rd_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_rd_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[3].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_rd_en_3_qs)
@@ -3019,20 +3019,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_prog_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_prog_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_prog_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[3].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_prog_en_3_qs)
@@ -3045,20 +3045,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_erase_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_erase_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_erase_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[3].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_erase_en_3_qs)
@@ -3071,20 +3071,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_scramble_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_scramble_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_scramble_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[3].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_scramble_en_3_qs)
@@ -3097,20 +3097,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_ecc_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_ecc_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_ecc_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[3].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_ecc_en_3_qs)
@@ -3123,20 +3123,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_he_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_he_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_he_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].he_en.q ),
+ .q (reg2hw.mp_region_cfg[3].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_he_en_3_qs)
@@ -3149,20 +3149,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_3_base_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_base_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_base_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].base.q ),
+ .q (reg2hw.mp_region_cfg[3].base.q),
// to register interface (read)
.qs (mp_region_cfg_3_base_3_qs)
@@ -3175,20 +3175,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_3_size_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_size_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_size_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].size.q ),
+ .q (reg2hw.mp_region_cfg[3].size.q),
// to register interface (read)
.qs (mp_region_cfg_3_size_3_qs)
@@ -3204,20 +3204,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].en.q ),
+ .q (reg2hw.mp_region_cfg[4].en.q),
// to register interface (read)
.qs (mp_region_cfg_4_en_4_qs)
@@ -3230,20 +3230,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_rd_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_rd_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_rd_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[4].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_rd_en_4_qs)
@@ -3256,20 +3256,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_prog_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_prog_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_prog_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[4].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_prog_en_4_qs)
@@ -3282,20 +3282,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_erase_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_erase_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_erase_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[4].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_erase_en_4_qs)
@@ -3308,20 +3308,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_scramble_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_scramble_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_scramble_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[4].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_scramble_en_4_qs)
@@ -3334,20 +3334,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_ecc_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_ecc_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_ecc_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[4].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_ecc_en_4_qs)
@@ -3360,20 +3360,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_he_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_he_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_he_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].he_en.q ),
+ .q (reg2hw.mp_region_cfg[4].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_he_en_4_qs)
@@ -3386,20 +3386,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_4_base_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_base_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_base_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].base.q ),
+ .q (reg2hw.mp_region_cfg[4].base.q),
// to register interface (read)
.qs (mp_region_cfg_4_base_4_qs)
@@ -3412,20 +3412,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_4_size_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_size_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_size_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].size.q ),
+ .q (reg2hw.mp_region_cfg[4].size.q),
// to register interface (read)
.qs (mp_region_cfg_4_size_4_qs)
@@ -3441,20 +3441,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].en.q ),
+ .q (reg2hw.mp_region_cfg[5].en.q),
// to register interface (read)
.qs (mp_region_cfg_5_en_5_qs)
@@ -3467,20 +3467,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_rd_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_rd_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_rd_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[5].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_rd_en_5_qs)
@@ -3493,20 +3493,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_prog_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_prog_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_prog_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[5].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_prog_en_5_qs)
@@ -3519,20 +3519,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_erase_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_erase_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_erase_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[5].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_erase_en_5_qs)
@@ -3545,20 +3545,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_scramble_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_scramble_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_scramble_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[5].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_scramble_en_5_qs)
@@ -3571,20 +3571,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_ecc_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_ecc_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_ecc_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[5].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_ecc_en_5_qs)
@@ -3597,20 +3597,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_he_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_he_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_he_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].he_en.q ),
+ .q (reg2hw.mp_region_cfg[5].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_he_en_5_qs)
@@ -3623,20 +3623,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_5_base_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_base_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_base_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].base.q ),
+ .q (reg2hw.mp_region_cfg[5].base.q),
// to register interface (read)
.qs (mp_region_cfg_5_base_5_qs)
@@ -3649,20 +3649,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_5_size_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_size_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_size_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].size.q ),
+ .q (reg2hw.mp_region_cfg[5].size.q),
// to register interface (read)
.qs (mp_region_cfg_5_size_5_qs)
@@ -3678,20 +3678,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].en.q ),
+ .q (reg2hw.mp_region_cfg[6].en.q),
// to register interface (read)
.qs (mp_region_cfg_6_en_6_qs)
@@ -3704,20 +3704,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_rd_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_rd_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_rd_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[6].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_rd_en_6_qs)
@@ -3730,20 +3730,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_prog_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_prog_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_prog_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[6].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_prog_en_6_qs)
@@ -3756,20 +3756,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_erase_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_erase_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_erase_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[6].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_erase_en_6_qs)
@@ -3782,20 +3782,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_scramble_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_scramble_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_scramble_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[6].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_scramble_en_6_qs)
@@ -3808,20 +3808,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_ecc_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_ecc_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_ecc_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[6].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_ecc_en_6_qs)
@@ -3834,20 +3834,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_he_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_he_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_he_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].he_en.q ),
+ .q (reg2hw.mp_region_cfg[6].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_he_en_6_qs)
@@ -3860,20 +3860,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_6_base_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_base_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_base_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].base.q ),
+ .q (reg2hw.mp_region_cfg[6].base.q),
// to register interface (read)
.qs (mp_region_cfg_6_base_6_qs)
@@ -3886,20 +3886,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_6_size_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_size_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_size_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].size.q ),
+ .q (reg2hw.mp_region_cfg[6].size.q),
// to register interface (read)
.qs (mp_region_cfg_6_size_6_qs)
@@ -3915,20 +3915,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].en.q ),
+ .q (reg2hw.mp_region_cfg[7].en.q),
// to register interface (read)
.qs (mp_region_cfg_7_en_7_qs)
@@ -3941,20 +3941,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_rd_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_rd_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_rd_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[7].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_rd_en_7_qs)
@@ -3967,20 +3967,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_prog_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_prog_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_prog_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[7].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_prog_en_7_qs)
@@ -3993,20 +3993,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_erase_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_erase_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_erase_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[7].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_erase_en_7_qs)
@@ -4019,20 +4019,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_scramble_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_scramble_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_scramble_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[7].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_scramble_en_7_qs)
@@ -4045,20 +4045,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_ecc_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_ecc_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_ecc_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[7].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_ecc_en_7_qs)
@@ -4071,20 +4071,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_he_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_he_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_he_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].he_en.q ),
+ .q (reg2hw.mp_region_cfg[7].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_he_en_7_qs)
@@ -4097,20 +4097,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_7_base_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_base_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_base_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].base.q ),
+ .q (reg2hw.mp_region_cfg[7].base.q),
// to register interface (read)
.qs (mp_region_cfg_7_base_7_qs)
@@ -4123,20 +4123,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_7_size_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_size_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_size_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].size.q ),
+ .q (reg2hw.mp_region_cfg[7].size.q),
// to register interface (read)
.qs (mp_region_cfg_7_size_7_qs)
@@ -4152,8 +4152,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_rd_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_rd_en_we),
@@ -4161,11 +4161,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.rd_en.q ),
+ .q (reg2hw.default_region.rd_en.q),
// to register interface (read)
.qs (default_region_rd_en_qs)
@@ -4178,8 +4178,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_prog_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_prog_en_we),
@@ -4187,11 +4187,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.prog_en.q ),
+ .q (reg2hw.default_region.prog_en.q),
// to register interface (read)
.qs (default_region_prog_en_qs)
@@ -4204,8 +4204,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_erase_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_erase_en_we),
@@ -4213,11 +4213,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.erase_en.q ),
+ .q (reg2hw.default_region.erase_en.q),
// to register interface (read)
.qs (default_region_erase_en_qs)
@@ -4230,8 +4230,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_scramble_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_scramble_en_we),
@@ -4239,11 +4239,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.scramble_en.q ),
+ .q (reg2hw.default_region.scramble_en.q),
// to register interface (read)
.qs (default_region_scramble_en_qs)
@@ -4256,8 +4256,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_ecc_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_ecc_en_we),
@@ -4265,11 +4265,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.ecc_en.q ),
+ .q (reg2hw.default_region.ecc_en.q),
// to register interface (read)
.qs (default_region_ecc_en_qs)
@@ -4282,8 +4282,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_he_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_he_en_we),
@@ -4291,11 +4291,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.he_en.q ),
+ .q (reg2hw.default_region.he_en.q),
// to register interface (read)
.qs (default_region_he_en_qs)
@@ -4311,8 +4311,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_0_we),
@@ -4320,7 +4320,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4338,8 +4338,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_1_we),
@@ -4347,7 +4347,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4365,8 +4365,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_2_we),
@@ -4374,7 +4374,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4392,8 +4392,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_3_we),
@@ -4401,7 +4401,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4419,8 +4419,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_4_we),
@@ -4428,7 +4428,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4446,8 +4446,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_5_we),
@@ -4455,7 +4455,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4473,8 +4473,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_6_we),
@@ -4482,7 +4482,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4500,8 +4500,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_7_we),
@@ -4509,7 +4509,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4527,8 +4527,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_8_we),
@@ -4536,7 +4536,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4554,8 +4554,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_9_we),
@@ -4563,7 +4563,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4584,20 +4584,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_en_0_qs)
@@ -4610,20 +4610,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_rd_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_rd_en_0_qs)
@@ -4636,20 +4636,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_prog_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_prog_en_0_qs)
@@ -4662,20 +4662,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_erase_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_erase_en_0_qs)
@@ -4688,20 +4688,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_scramble_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_scramble_en_0_qs)
@@ -4714,20 +4714,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_ecc_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_ecc_en_0_qs)
@@ -4740,20 +4740,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_he_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_he_en_0_qs)
@@ -4769,20 +4769,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_en_1_qs)
@@ -4795,20 +4795,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_rd_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_rd_en_1_qs)
@@ -4821,20 +4821,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_prog_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_prog_en_1_qs)
@@ -4847,20 +4847,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_erase_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_erase_en_1_qs)
@@ -4873,20 +4873,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_scramble_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_scramble_en_1_qs)
@@ -4899,20 +4899,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_ecc_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_ecc_en_1_qs)
@@ -4925,20 +4925,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_he_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_he_en_1_qs)
@@ -4954,20 +4954,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_en_2_qs)
@@ -4980,20 +4980,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_rd_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_rd_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_rd_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_rd_en_2_qs)
@@ -5006,20 +5006,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_prog_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_prog_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_prog_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_prog_en_2_qs)
@@ -5032,20 +5032,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_erase_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_erase_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_erase_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_erase_en_2_qs)
@@ -5058,20 +5058,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_scramble_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_scramble_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_scramble_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_scramble_en_2_qs)
@@ -5084,20 +5084,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_ecc_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_ecc_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_ecc_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_ecc_en_2_qs)
@@ -5110,20 +5110,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_he_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_he_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_he_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_he_en_2_qs)
@@ -5139,20 +5139,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_en_3_qs)
@@ -5165,20 +5165,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_rd_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_rd_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_rd_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_rd_en_3_qs)
@@ -5191,20 +5191,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_prog_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_prog_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_prog_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_prog_en_3_qs)
@@ -5217,20 +5217,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_erase_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_erase_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_erase_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_erase_en_3_qs)
@@ -5243,20 +5243,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_scramble_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_scramble_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_scramble_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_scramble_en_3_qs)
@@ -5269,20 +5269,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_ecc_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_ecc_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_ecc_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_ecc_en_3_qs)
@@ -5295,20 +5295,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_he_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_he_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_he_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_he_en_3_qs)
@@ -5324,20 +5324,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_en_4_qs)
@@ -5350,20 +5350,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_rd_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_rd_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_rd_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_rd_en_4_qs)
@@ -5376,20 +5376,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_prog_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_prog_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_prog_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_prog_en_4_qs)
@@ -5402,20 +5402,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_erase_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_erase_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_erase_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_erase_en_4_qs)
@@ -5428,20 +5428,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_scramble_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_scramble_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_scramble_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_scramble_en_4_qs)
@@ -5454,20 +5454,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_ecc_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_ecc_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_ecc_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_ecc_en_4_qs)
@@ -5480,20 +5480,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_he_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_he_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_he_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_he_en_4_qs)
@@ -5509,20 +5509,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_en_5_qs)
@@ -5535,20 +5535,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_rd_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_rd_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_rd_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_rd_en_5_qs)
@@ -5561,20 +5561,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_prog_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_prog_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_prog_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_prog_en_5_qs)
@@ -5587,20 +5587,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_erase_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_erase_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_erase_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_erase_en_5_qs)
@@ -5613,20 +5613,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_scramble_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_scramble_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_scramble_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_scramble_en_5_qs)
@@ -5639,20 +5639,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_ecc_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_ecc_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_ecc_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_ecc_en_5_qs)
@@ -5665,20 +5665,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_he_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_he_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_he_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_he_en_5_qs)
@@ -5694,20 +5694,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_en_6_qs)
@@ -5720,20 +5720,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_rd_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_rd_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_rd_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_rd_en_6_qs)
@@ -5746,20 +5746,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_prog_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_prog_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_prog_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_prog_en_6_qs)
@@ -5772,20 +5772,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_erase_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_erase_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_erase_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_erase_en_6_qs)
@@ -5798,20 +5798,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_scramble_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_scramble_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_scramble_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_scramble_en_6_qs)
@@ -5824,20 +5824,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_ecc_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_ecc_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_ecc_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_ecc_en_6_qs)
@@ -5850,20 +5850,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_he_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_he_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_he_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_he_en_6_qs)
@@ -5879,20 +5879,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_en_7_qs)
@@ -5905,20 +5905,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_rd_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_rd_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_rd_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_rd_en_7_qs)
@@ -5931,20 +5931,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_prog_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_prog_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_prog_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_prog_en_7_qs)
@@ -5957,20 +5957,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_erase_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_erase_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_erase_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_erase_en_7_qs)
@@ -5983,20 +5983,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_scramble_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_scramble_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_scramble_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_scramble_en_7_qs)
@@ -6009,20 +6009,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_ecc_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_ecc_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_ecc_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_ecc_en_7_qs)
@@ -6035,20 +6035,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_he_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_he_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_he_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_he_en_7_qs)
@@ -6064,20 +6064,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_en_8_qs)
@@ -6090,20 +6090,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_rd_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_rd_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_rd_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_rd_en_8_qs)
@@ -6116,20 +6116,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_prog_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_prog_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_prog_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_prog_en_8_qs)
@@ -6142,20 +6142,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_erase_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_erase_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_erase_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_erase_en_8_qs)
@@ -6168,20 +6168,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_scramble_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_scramble_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_scramble_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_scramble_en_8_qs)
@@ -6194,20 +6194,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_ecc_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_ecc_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_ecc_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_ecc_en_8_qs)
@@ -6220,20 +6220,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_he_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_he_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_he_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_he_en_8_qs)
@@ -6249,20 +6249,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_en_9_qs)
@@ -6275,20 +6275,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_rd_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_rd_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_rd_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_rd_en_9_qs)
@@ -6301,20 +6301,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_prog_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_prog_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_prog_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_prog_en_9_qs)
@@ -6327,20 +6327,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_erase_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_erase_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_erase_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_erase_en_9_qs)
@@ -6353,20 +6353,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_scramble_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_scramble_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_scramble_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_scramble_en_9_qs)
@@ -6379,20 +6379,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_ecc_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_ecc_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_ecc_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_ecc_en_9_qs)
@@ -6405,20 +6405,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_he_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_he_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_he_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_he_en_9_qs)
@@ -6435,8 +6435,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info1_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info1_regwen_we),
@@ -6444,7 +6444,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6465,20 +6465,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_en_0_qs)
@@ -6491,20 +6491,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_rd_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_rd_en_0_qs)
@@ -6517,20 +6517,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_prog_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_prog_en_0_qs)
@@ -6543,20 +6543,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_erase_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_erase_en_0_qs)
@@ -6569,20 +6569,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_scramble_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_scramble_en_0_qs)
@@ -6595,20 +6595,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_ecc_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_ecc_en_0_qs)
@@ -6621,20 +6621,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_he_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_he_en_0_qs)
@@ -6651,8 +6651,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info2_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info2_regwen_0_we),
@@ -6660,7 +6660,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6678,8 +6678,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info2_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info2_regwen_1_we),
@@ -6687,7 +6687,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6708,20 +6708,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_en_0_qs)
@@ -6734,20 +6734,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_rd_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_rd_en_0_qs)
@@ -6760,20 +6760,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_prog_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_prog_en_0_qs)
@@ -6786,20 +6786,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_erase_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_erase_en_0_qs)
@@ -6812,20 +6812,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_scramble_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_scramble_en_0_qs)
@@ -6838,20 +6838,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_ecc_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_ecc_en_0_qs)
@@ -6864,20 +6864,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_he_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_he_en_0_qs)
@@ -6893,20 +6893,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_en_1_qs)
@@ -6919,20 +6919,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_rd_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].rd_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].rd_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_rd_en_1_qs)
@@ -6945,20 +6945,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_prog_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].prog_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].prog_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_prog_en_1_qs)
@@ -6971,20 +6971,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_erase_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].erase_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].erase_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_erase_en_1_qs)
@@ -6997,20 +6997,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_scramble_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].scramble_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].scramble_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_scramble_en_1_qs)
@@ -7023,20 +7023,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_ecc_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].ecc_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].ecc_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_ecc_en_1_qs)
@@ -7049,20 +7049,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_he_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].he_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].he_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_he_en_1_qs)
@@ -7079,8 +7079,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_0_we),
@@ -7088,7 +7088,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7106,8 +7106,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_1_we),
@@ -7115,7 +7115,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7133,8 +7133,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_2_we),
@@ -7142,7 +7142,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7160,8 +7160,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_3_we),
@@ -7169,7 +7169,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7187,8 +7187,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_4_we),
@@ -7196,7 +7196,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7214,8 +7214,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_5_we),
@@ -7223,7 +7223,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7241,8 +7241,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_6_we),
@@ -7250,7 +7250,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7268,8 +7268,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_7_we),
@@ -7277,7 +7277,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7295,8 +7295,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_8_we),
@@ -7304,7 +7304,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7322,8 +7322,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_9_we),
@@ -7331,7 +7331,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7352,20 +7352,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_en_0_qs)
@@ -7378,20 +7378,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_rd_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_rd_en_0_qs)
@@ -7404,20 +7404,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_prog_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_prog_en_0_qs)
@@ -7430,20 +7430,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_erase_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_erase_en_0_qs)
@@ -7456,20 +7456,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_scramble_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_scramble_en_0_qs)
@@ -7482,20 +7482,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_ecc_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_ecc_en_0_qs)
@@ -7508,20 +7508,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_he_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_he_en_0_qs)
@@ -7537,20 +7537,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_en_1_qs)
@@ -7563,20 +7563,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_rd_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_rd_en_1_qs)
@@ -7589,20 +7589,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_prog_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_prog_en_1_qs)
@@ -7615,20 +7615,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_erase_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_erase_en_1_qs)
@@ -7641,20 +7641,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_scramble_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_scramble_en_1_qs)
@@ -7667,20 +7667,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_ecc_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_ecc_en_1_qs)
@@ -7693,20 +7693,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_he_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_he_en_1_qs)
@@ -7722,20 +7722,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_en_2_qs)
@@ -7748,20 +7748,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_rd_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_rd_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_rd_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_rd_en_2_qs)
@@ -7774,20 +7774,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_prog_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_prog_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_prog_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_prog_en_2_qs)
@@ -7800,20 +7800,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_erase_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_erase_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_erase_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_erase_en_2_qs)
@@ -7826,20 +7826,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_scramble_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_scramble_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_scramble_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_scramble_en_2_qs)
@@ -7852,20 +7852,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_ecc_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_ecc_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_ecc_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_ecc_en_2_qs)
@@ -7878,20 +7878,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_he_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_he_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_he_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_he_en_2_qs)
@@ -7907,20 +7907,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_en_3_qs)
@@ -7933,20 +7933,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_rd_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_rd_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_rd_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_rd_en_3_qs)
@@ -7959,20 +7959,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_prog_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_prog_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_prog_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_prog_en_3_qs)
@@ -7985,20 +7985,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_erase_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_erase_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_erase_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_erase_en_3_qs)
@@ -8011,20 +8011,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_scramble_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_scramble_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_scramble_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_scramble_en_3_qs)
@@ -8037,20 +8037,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_ecc_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_ecc_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_ecc_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_ecc_en_3_qs)
@@ -8063,20 +8063,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_he_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_he_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_he_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_he_en_3_qs)
@@ -8092,20 +8092,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_en_4_qs)
@@ -8118,20 +8118,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_rd_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_rd_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_rd_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_rd_en_4_qs)
@@ -8144,20 +8144,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_prog_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_prog_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_prog_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_prog_en_4_qs)
@@ -8170,20 +8170,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_erase_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_erase_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_erase_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_erase_en_4_qs)
@@ -8196,20 +8196,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_scramble_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_scramble_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_scramble_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_scramble_en_4_qs)
@@ -8222,20 +8222,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_ecc_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_ecc_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_ecc_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_ecc_en_4_qs)
@@ -8248,20 +8248,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_he_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_he_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_he_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_he_en_4_qs)
@@ -8277,20 +8277,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_en_5_qs)
@@ -8303,20 +8303,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_rd_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_rd_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_rd_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_rd_en_5_qs)
@@ -8329,20 +8329,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_prog_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_prog_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_prog_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_prog_en_5_qs)
@@ -8355,20 +8355,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_erase_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_erase_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_erase_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_erase_en_5_qs)
@@ -8381,20 +8381,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_scramble_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_scramble_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_scramble_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_scramble_en_5_qs)
@@ -8407,20 +8407,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_ecc_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_ecc_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_ecc_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_ecc_en_5_qs)
@@ -8433,20 +8433,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_he_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_he_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_he_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_he_en_5_qs)
@@ -8462,20 +8462,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_en_6_qs)
@@ -8488,20 +8488,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_rd_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_rd_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_rd_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_rd_en_6_qs)
@@ -8514,20 +8514,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_prog_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_prog_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_prog_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_prog_en_6_qs)
@@ -8540,20 +8540,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_erase_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_erase_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_erase_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_erase_en_6_qs)
@@ -8566,20 +8566,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_scramble_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_scramble_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_scramble_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_scramble_en_6_qs)
@@ -8592,20 +8592,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_ecc_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_ecc_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_ecc_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_ecc_en_6_qs)
@@ -8618,20 +8618,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_he_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_he_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_he_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_he_en_6_qs)
@@ -8647,20 +8647,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_en_7_qs)
@@ -8673,20 +8673,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_rd_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_rd_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_rd_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_rd_en_7_qs)
@@ -8699,20 +8699,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_prog_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_prog_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_prog_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_prog_en_7_qs)
@@ -8725,20 +8725,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_erase_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_erase_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_erase_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_erase_en_7_qs)
@@ -8751,20 +8751,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_scramble_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_scramble_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_scramble_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_scramble_en_7_qs)
@@ -8777,20 +8777,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_ecc_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_ecc_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_ecc_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_ecc_en_7_qs)
@@ -8803,20 +8803,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_he_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_he_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_he_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_he_en_7_qs)
@@ -8832,20 +8832,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_en_8_qs)
@@ -8858,20 +8858,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_rd_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_rd_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_rd_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_rd_en_8_qs)
@@ -8884,20 +8884,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_prog_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_prog_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_prog_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_prog_en_8_qs)
@@ -8910,20 +8910,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_erase_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_erase_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_erase_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_erase_en_8_qs)
@@ -8936,20 +8936,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_scramble_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_scramble_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_scramble_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_scramble_en_8_qs)
@@ -8962,20 +8962,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_ecc_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_ecc_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_ecc_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_ecc_en_8_qs)
@@ -8988,20 +8988,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_he_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_he_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_he_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_he_en_8_qs)
@@ -9017,20 +9017,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_en_9_qs)
@@ -9043,20 +9043,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_rd_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_rd_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_rd_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_rd_en_9_qs)
@@ -9069,20 +9069,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_prog_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_prog_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_prog_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_prog_en_9_qs)
@@ -9095,20 +9095,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_erase_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_erase_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_erase_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_erase_en_9_qs)
@@ -9121,20 +9121,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_scramble_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_scramble_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_scramble_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_scramble_en_9_qs)
@@ -9147,20 +9147,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_ecc_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_ecc_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_ecc_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_ecc_en_9_qs)
@@ -9173,20 +9173,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_he_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_he_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_he_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_he_en_9_qs)
@@ -9203,8 +9203,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info1_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info1_regwen_we),
@@ -9212,7 +9212,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9233,20 +9233,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_en_0_qs)
@@ -9259,20 +9259,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_rd_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_rd_en_0_qs)
@@ -9285,20 +9285,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_prog_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_prog_en_0_qs)
@@ -9311,20 +9311,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_erase_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_erase_en_0_qs)
@@ -9337,20 +9337,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_scramble_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_scramble_en_0_qs)
@@ -9363,20 +9363,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_ecc_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_ecc_en_0_qs)
@@ -9389,20 +9389,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_he_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_he_en_0_qs)
@@ -9419,8 +9419,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info2_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info2_regwen_0_we),
@@ -9428,7 +9428,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9446,8 +9446,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info2_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info2_regwen_1_we),
@@ -9455,7 +9455,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9476,20 +9476,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_en_0_qs)
@@ -9502,20 +9502,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_rd_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_rd_en_0_qs)
@@ -9528,20 +9528,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_prog_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_prog_en_0_qs)
@@ -9554,20 +9554,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_erase_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_erase_en_0_qs)
@@ -9580,20 +9580,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_scramble_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_scramble_en_0_qs)
@@ -9606,20 +9606,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_ecc_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_ecc_en_0_qs)
@@ -9632,20 +9632,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_he_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_he_en_0_qs)
@@ -9661,20 +9661,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_en_1_qs)
@@ -9687,20 +9687,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_rd_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].rd_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].rd_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_rd_en_1_qs)
@@ -9713,20 +9713,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_prog_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].prog_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].prog_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_prog_en_1_qs)
@@ -9739,20 +9739,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_erase_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].erase_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].erase_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_erase_en_1_qs)
@@ -9765,20 +9765,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_scramble_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].scramble_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].scramble_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_scramble_en_1_qs)
@@ -9791,20 +9791,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_ecc_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].ecc_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].ecc_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_ecc_en_1_qs)
@@ -9817,20 +9817,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_he_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].he_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].he_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_he_en_1_qs)
@@ -9845,8 +9845,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank_cfg_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank_cfg_regwen_we),
@@ -9854,7 +9854,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9875,20 +9875,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_bank_cfg_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_bank_cfg_erase_en_0_we & bank_cfg_regwen_qs),
.wd (mp_bank_cfg_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_bank_cfg[0].q ),
+ .q (reg2hw.mp_bank_cfg[0].q),
// to register interface (read)
.qs (mp_bank_cfg_erase_en_0_qs)
@@ -9901,20 +9901,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_bank_cfg_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_bank_cfg_erase_en_1_we & bank_cfg_regwen_qs),
.wd (mp_bank_cfg_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_bank_cfg[1].q ),
+ .q (reg2hw.mp_bank_cfg[1].q),
// to register interface (read)
.qs (mp_bank_cfg_erase_en_1_qs)
@@ -9930,8 +9930,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_op_status_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (op_status_done_we),
@@ -9939,7 +9939,7 @@
// from internal hardware
.de (hw2reg.op_status.done.de),
- .d (hw2reg.op_status.done.d ),
+ .d (hw2reg.op_status.done.d),
// to internal hardware
.qe (),
@@ -9956,8 +9956,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_op_status_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (op_status_err_we),
@@ -9965,7 +9965,7 @@
// from internal hardware
.de (hw2reg.op_status.err.de),
- .d (hw2reg.op_status.err.d ),
+ .d (hw2reg.op_status.err.d),
// to internal hardware
.qe (),
@@ -9984,15 +9984,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_rd_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.rd_full.de),
- .d (hw2reg.status.rd_full.d ),
+ .d (hw2reg.status.rd_full.d),
// to internal hardware
.qe (),
@@ -10009,15 +10010,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_status_rd_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.rd_empty.de),
- .d (hw2reg.status.rd_empty.d ),
+ .d (hw2reg.status.rd_empty.d),
// to internal hardware
.qe (),
@@ -10034,15 +10036,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_prog_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.prog_full.de),
- .d (hw2reg.status.prog_full.d ),
+ .d (hw2reg.status.prog_full.d),
// to internal hardware
.qe (),
@@ -10059,15 +10062,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_status_prog_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.prog_empty.de),
- .d (hw2reg.status.prog_empty.d ),
+ .d (hw2reg.status.prog_empty.d),
// to internal hardware
.qe (),
@@ -10084,15 +10088,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_init_wip (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.init_wip.de),
- .d (hw2reg.status.init_wip.d ),
+ .d (hw2reg.status.init_wip.d),
// to internal hardware
.qe (),
@@ -10111,8 +10116,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_flash_err_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_flash_err_en_we),
@@ -10120,11 +10125,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.flash_err_en.q ),
+ .q (reg2hw.err_code_intr_en.flash_err_en.q),
// to register interface (read)
.qs (err_code_intr_en_flash_err_en_qs)
@@ -10137,8 +10142,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_flash_alert_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_flash_alert_en_we),
@@ -10146,11 +10151,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.flash_alert_en.q ),
+ .q (reg2hw.err_code_intr_en.flash_alert_en.q),
// to register interface (read)
.qs (err_code_intr_en_flash_alert_en_qs)
@@ -10163,8 +10168,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_mp_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_mp_err_we),
@@ -10172,11 +10177,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.mp_err.q ),
+ .q (reg2hw.err_code_intr_en.mp_err.q),
// to register interface (read)
.qs (err_code_intr_en_mp_err_qs)
@@ -10189,8 +10194,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_ecc_single_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_ecc_single_err_we),
@@ -10198,11 +10203,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.ecc_single_err.q ),
+ .q (reg2hw.err_code_intr_en.ecc_single_err.q),
// to register interface (read)
.qs (err_code_intr_en_ecc_single_err_qs)
@@ -10215,8 +10220,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_ecc_multi_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_ecc_multi_err_we),
@@ -10224,11 +10229,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.ecc_multi_err.q ),
+ .q (reg2hw.err_code_intr_en.ecc_multi_err.q),
// to register interface (read)
.qs (err_code_intr_en_ecc_multi_err_qs)
@@ -10243,8 +10248,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_flash_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_flash_err_we),
@@ -10252,11 +10257,11 @@
// from internal hardware
.de (hw2reg.err_code.flash_err.de),
- .d (hw2reg.err_code.flash_err.d ),
+ .d (hw2reg.err_code.flash_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.flash_err.q ),
+ .q (reg2hw.err_code.flash_err.q),
// to register interface (read)
.qs (err_code_flash_err_qs)
@@ -10269,8 +10274,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_flash_alert (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_flash_alert_we),
@@ -10278,11 +10283,11 @@
// from internal hardware
.de (hw2reg.err_code.flash_alert.de),
- .d (hw2reg.err_code.flash_alert.d ),
+ .d (hw2reg.err_code.flash_alert.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.flash_alert.q ),
+ .q (reg2hw.err_code.flash_alert.q),
// to register interface (read)
.qs (err_code_flash_alert_qs)
@@ -10295,8 +10300,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_mp_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_mp_err_we),
@@ -10304,11 +10309,11 @@
// from internal hardware
.de (hw2reg.err_code.mp_err.de),
- .d (hw2reg.err_code.mp_err.d ),
+ .d (hw2reg.err_code.mp_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.mp_err.q ),
+ .q (reg2hw.err_code.mp_err.q),
// to register interface (read)
.qs (err_code_mp_err_qs)
@@ -10321,8 +10326,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_ecc_single_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_ecc_single_err_we),
@@ -10330,11 +10335,11 @@
// from internal hardware
.de (hw2reg.err_code.ecc_single_err.de),
- .d (hw2reg.err_code.ecc_single_err.d ),
+ .d (hw2reg.err_code.ecc_single_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.ecc_single_err.q ),
+ .q (reg2hw.err_code.ecc_single_err.q),
// to register interface (read)
.qs (err_code_ecc_single_err_qs)
@@ -10347,8 +10352,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_ecc_multi_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_ecc_multi_err_we),
@@ -10356,11 +10361,11 @@
// from internal hardware
.de (hw2reg.err_code.ecc_multi_err.de),
- .d (hw2reg.err_code.ecc_multi_err.d ),
+ .d (hw2reg.err_code.ecc_multi_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.ecc_multi_err.q ),
+ .q (reg2hw.err_code.ecc_multi_err.q),
// to register interface (read)
.qs (err_code_ecc_multi_err_qs)
@@ -10374,15 +10379,16 @@
.SWACCESS("RO"),
.RESVAL (9'h0)
) u_err_addr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_addr.de),
- .d (hw2reg.err_addr.d ),
+ .d (hw2reg.err_addr.d),
// to internal hardware
.qe (),
@@ -10400,8 +10406,8 @@
.SWACCESS("W1C"),
.RESVAL (8'h0)
) u_ecc_single_err_cnt (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ecc_single_err_cnt_we),
@@ -10409,11 +10415,11 @@
// from internal hardware
.de (hw2reg.ecc_single_err_cnt.de),
- .d (hw2reg.ecc_single_err_cnt.d ),
+ .d (hw2reg.ecc_single_err_cnt.d),
// to internal hardware
.qe (),
- .q (reg2hw.ecc_single_err_cnt.q ),
+ .q (reg2hw.ecc_single_err_cnt.q),
// to register interface (read)
.qs (ecc_single_err_cnt_qs)
@@ -10429,15 +10435,16 @@
.SWACCESS("RO"),
.RESVAL (20'h0)
) u_ecc_single_err_addr_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ecc_single_err_addr[0].de),
- .d (hw2reg.ecc_single_err_addr[0].d ),
+ .d (hw2reg.ecc_single_err_addr[0].d),
// to internal hardware
.qe (),
@@ -10455,15 +10462,16 @@
.SWACCESS("RO"),
.RESVAL (20'h0)
) u_ecc_single_err_addr_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ecc_single_err_addr[1].de),
- .d (hw2reg.ecc_single_err_addr[1].d ),
+ .d (hw2reg.ecc_single_err_addr[1].d),
// to internal hardware
.qe (),
@@ -10481,8 +10489,8 @@
.SWACCESS("W1C"),
.RESVAL (8'h0)
) u_ecc_multi_err_cnt (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ecc_multi_err_cnt_we),
@@ -10490,11 +10498,11 @@
// from internal hardware
.de (hw2reg.ecc_multi_err_cnt.de),
- .d (hw2reg.ecc_multi_err_cnt.d ),
+ .d (hw2reg.ecc_multi_err_cnt.d),
// to internal hardware
.qe (),
- .q (reg2hw.ecc_multi_err_cnt.q ),
+ .q (reg2hw.ecc_multi_err_cnt.q),
// to register interface (read)
.qs (ecc_multi_err_cnt_qs)
@@ -10510,15 +10518,16 @@
.SWACCESS("RO"),
.RESVAL (20'h0)
) u_ecc_multi_err_addr_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ecc_multi_err_addr[0].de),
- .d (hw2reg.ecc_multi_err_addr[0].d ),
+ .d (hw2reg.ecc_multi_err_addr[0].d),
// to internal hardware
.qe (),
@@ -10536,15 +10545,16 @@
.SWACCESS("RO"),
.RESVAL (20'h0)
) u_ecc_multi_err_addr_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ecc_multi_err_addr[1].de),
- .d (hw2reg.ecc_multi_err_addr[1].d ),
+ .d (hw2reg.ecc_multi_err_addr[1].d),
// to internal hardware
.qe (),
@@ -10562,8 +10572,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_phy_err_cfg_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_err_cfg_regwen_we),
@@ -10571,7 +10581,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10589,20 +10599,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_err_cfg (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (phy_err_cfg_we & phy_err_cfg_regwen_qs),
.wd (phy_err_cfg_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_err_cfg.q ),
+ .q (reg2hw.phy_err_cfg.q),
// to register interface (read)
.qs (phy_err_cfg_qs)
@@ -10617,8 +10627,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_alert_cfg_alert_ack (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_alert_cfg_alert_ack_we),
@@ -10626,11 +10636,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_alert_cfg.alert_ack.q ),
+ .q (reg2hw.phy_alert_cfg.alert_ack.q),
// to register interface (read)
.qs (phy_alert_cfg_alert_ack_qs)
@@ -10643,8 +10653,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_alert_cfg_alert_trig (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_alert_cfg_alert_trig_we),
@@ -10652,11 +10662,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_alert_cfg.alert_trig.q ),
+ .q (reg2hw.phy_alert_cfg.alert_trig.q),
// to register interface (read)
.qs (phy_alert_cfg_alert_trig_qs)
@@ -10671,15 +10681,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_phy_status_init_wip (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.phy_status.init_wip.de),
- .d (hw2reg.phy_status.init_wip.d ),
+ .d (hw2reg.phy_status.init_wip.d),
// to internal hardware
.qe (),
@@ -10696,15 +10707,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_phy_status_prog_normal_avail (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.phy_status.prog_normal_avail.de),
- .d (hw2reg.phy_status.prog_normal_avail.d ),
+ .d (hw2reg.phy_status.prog_normal_avail.d),
// to internal hardware
.qe (),
@@ -10721,15 +10733,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_phy_status_prog_repair_avail (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.phy_status.prog_repair_avail.de),
- .d (hw2reg.phy_status.prog_repair_avail.d ),
+ .d (hw2reg.phy_status.prog_repair_avail.d),
// to internal hardware
.qe (),
@@ -10747,8 +10760,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_scratch (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (scratch_we),
@@ -10756,11 +10769,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.scratch.q ),
+ .q (reg2hw.scratch.q),
// to register interface (read)
.qs (scratch_qs)
@@ -10775,8 +10788,8 @@
.SWACCESS("RW"),
.RESVAL (5'hf)
) u_fifo_lvl_prog (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_lvl_prog_we),
@@ -10784,11 +10797,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fifo_lvl.prog.q ),
+ .q (reg2hw.fifo_lvl.prog.q),
// to register interface (read)
.qs (fifo_lvl_prog_qs)
@@ -10801,8 +10814,8 @@
.SWACCESS("RW"),
.RESVAL (5'hf)
) u_fifo_lvl_rd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_lvl_rd_we),
@@ -10810,11 +10823,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fifo_lvl.rd.q ),
+ .q (reg2hw.fifo_lvl.rd.q),
// to register interface (read)
.qs (fifo_lvl_rd_qs)
@@ -10828,8 +10841,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_fifo_rst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_rst_we),
@@ -10837,11 +10850,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fifo_rst.q ),
+ .q (reg2hw.fifo_rst.q),
// to register interface (read)
.qs (fifo_rst_qs)
diff --git a/hw/ip/gpio/rtl/gpio_reg_top.sv b/hw/ip/gpio/rtl/gpio_reg_top.sv
index a5ac0db..4fd2cc8 100644
--- a/hw/ip/gpio/rtl/gpio_reg_top.sv
+++ b/hw/ip/gpio/rtl/gpio_reg_top.sv
@@ -173,8 +173,8 @@
.SWACCESS("W1C"),
.RESVAL (32'h0)
) u_intr_state (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
@@ -182,11 +182,11 @@
// from internal hardware
.de (hw2reg.intr_state.de),
- .d (hw2reg.intr_state.d ),
+ .d (hw2reg.intr_state.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.q ),
+ .q (reg2hw.intr_state.q),
// to register interface (read)
.qs (intr_state_qs)
@@ -200,8 +200,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_intr_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
@@ -209,11 +209,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.q ),
+ .q (reg2hw.intr_enable.q),
// to register interface (read)
.qs (intr_enable_qs)
@@ -231,7 +231,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.qe),
- .q (reg2hw.intr_test.q ),
+ .q (reg2hw.intr_test.q),
.qs ()
);
@@ -243,15 +243,16 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_data_in (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.data_in.de),
- .d (hw2reg.data_in.d ),
+ .d (hw2reg.data_in.d),
// to internal hardware
.qe (),
@@ -273,7 +274,7 @@
.d (hw2reg.direct_out.d),
.qre (),
.qe (reg2hw.direct_out.qe),
- .q (reg2hw.direct_out.q ),
+ .q (reg2hw.direct_out.q),
.qs (direct_out_qs)
);
@@ -290,7 +291,7 @@
.d (hw2reg.masked_out_lower.data.d),
.qre (),
.qe (reg2hw.masked_out_lower.data.qe),
- .q (reg2hw.masked_out_lower.data.q ),
+ .q (reg2hw.masked_out_lower.data.q),
.qs (masked_out_lower_data_qs)
);
@@ -305,7 +306,7 @@
.d (hw2reg.masked_out_lower.mask.d),
.qre (),
.qe (reg2hw.masked_out_lower.mask.qe),
- .q (reg2hw.masked_out_lower.mask.q ),
+ .q (reg2hw.masked_out_lower.mask.q),
.qs ()
);
@@ -322,7 +323,7 @@
.d (hw2reg.masked_out_upper.data.d),
.qre (),
.qe (reg2hw.masked_out_upper.data.qe),
- .q (reg2hw.masked_out_upper.data.q ),
+ .q (reg2hw.masked_out_upper.data.q),
.qs (masked_out_upper_data_qs)
);
@@ -337,7 +338,7 @@
.d (hw2reg.masked_out_upper.mask.d),
.qre (),
.qe (reg2hw.masked_out_upper.mask.qe),
- .q (reg2hw.masked_out_upper.mask.q ),
+ .q (reg2hw.masked_out_upper.mask.q),
.qs ()
);
@@ -353,7 +354,7 @@
.d (hw2reg.direct_oe.d),
.qre (),
.qe (reg2hw.direct_oe.qe),
- .q (reg2hw.direct_oe.q ),
+ .q (reg2hw.direct_oe.q),
.qs (direct_oe_qs)
);
@@ -370,7 +371,7 @@
.d (hw2reg.masked_oe_lower.data.d),
.qre (),
.qe (reg2hw.masked_oe_lower.data.qe),
- .q (reg2hw.masked_oe_lower.data.q ),
+ .q (reg2hw.masked_oe_lower.data.q),
.qs (masked_oe_lower_data_qs)
);
@@ -385,7 +386,7 @@
.d (hw2reg.masked_oe_lower.mask.d),
.qre (),
.qe (reg2hw.masked_oe_lower.mask.qe),
- .q (reg2hw.masked_oe_lower.mask.q ),
+ .q (reg2hw.masked_oe_lower.mask.q),
.qs (masked_oe_lower_mask_qs)
);
@@ -402,7 +403,7 @@
.d (hw2reg.masked_oe_upper.data.d),
.qre (),
.qe (reg2hw.masked_oe_upper.data.qe),
- .q (reg2hw.masked_oe_upper.data.q ),
+ .q (reg2hw.masked_oe_upper.data.q),
.qs (masked_oe_upper_data_qs)
);
@@ -417,7 +418,7 @@
.d (hw2reg.masked_oe_upper.mask.d),
.qre (),
.qe (reg2hw.masked_oe_upper.mask.qe),
- .q (reg2hw.masked_oe_upper.mask.q ),
+ .q (reg2hw.masked_oe_upper.mask.q),
.qs (masked_oe_upper_mask_qs)
);
@@ -429,8 +430,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_intr_ctrl_en_rising (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_ctrl_en_rising_we),
@@ -438,11 +439,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_ctrl_en_rising.q ),
+ .q (reg2hw.intr_ctrl_en_rising.q),
// to register interface (read)
.qs (intr_ctrl_en_rising_qs)
@@ -456,8 +457,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_intr_ctrl_en_falling (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_ctrl_en_falling_we),
@@ -465,11 +466,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_ctrl_en_falling.q ),
+ .q (reg2hw.intr_ctrl_en_falling.q),
// to register interface (read)
.qs (intr_ctrl_en_falling_qs)
@@ -483,8 +484,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_intr_ctrl_en_lvlhigh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_ctrl_en_lvlhigh_we),
@@ -492,11 +493,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_ctrl_en_lvlhigh.q ),
+ .q (reg2hw.intr_ctrl_en_lvlhigh.q),
// to register interface (read)
.qs (intr_ctrl_en_lvlhigh_qs)
@@ -510,8 +511,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_intr_ctrl_en_lvllow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_ctrl_en_lvllow_we),
@@ -519,11 +520,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_ctrl_en_lvllow.q ),
+ .q (reg2hw.intr_ctrl_en_lvllow.q),
// to register interface (read)
.qs (intr_ctrl_en_lvllow_qs)
@@ -537,8 +538,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_ctrl_en_input_filter (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_en_input_filter_we),
@@ -546,11 +547,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl_en_input_filter.q ),
+ .q (reg2hw.ctrl_en_input_filter.q),
// to register interface (read)
.qs (ctrl_en_input_filter_qs)
diff --git a/hw/ip/hmac/rtl/hmac_reg_top.sv b/hw/ip/hmac/rtl/hmac_reg_top.sv
index 03e4c62..bbce5b8 100644
--- a/hw/ip/hmac/rtl/hmac_reg_top.sv
+++ b/hw/ip/hmac/rtl/hmac_reg_top.sv
@@ -251,8 +251,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_hmac_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_hmac_done_we),
@@ -260,11 +260,11 @@
// from internal hardware
.de (hw2reg.intr_state.hmac_done.de),
- .d (hw2reg.intr_state.hmac_done.d ),
+ .d (hw2reg.intr_state.hmac_done.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.hmac_done.q ),
+ .q (reg2hw.intr_state.hmac_done.q),
// to register interface (read)
.qs (intr_state_hmac_done_qs)
@@ -277,8 +277,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_fifo_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_fifo_empty_we),
@@ -286,11 +286,11 @@
// from internal hardware
.de (hw2reg.intr_state.fifo_empty.de),
- .d (hw2reg.intr_state.fifo_empty.d ),
+ .d (hw2reg.intr_state.fifo_empty.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.fifo_empty.q ),
+ .q (reg2hw.intr_state.fifo_empty.q),
// to register interface (read)
.qs (intr_state_fifo_empty_qs)
@@ -303,8 +303,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_hmac_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_hmac_err_we),
@@ -312,11 +312,11 @@
// from internal hardware
.de (hw2reg.intr_state.hmac_err.de),
- .d (hw2reg.intr_state.hmac_err.d ),
+ .d (hw2reg.intr_state.hmac_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.hmac_err.q ),
+ .q (reg2hw.intr_state.hmac_err.q),
// to register interface (read)
.qs (intr_state_hmac_err_qs)
@@ -331,8 +331,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_hmac_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_hmac_done_we),
@@ -340,11 +340,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.hmac_done.q ),
+ .q (reg2hw.intr_enable.hmac_done.q),
// to register interface (read)
.qs (intr_enable_hmac_done_qs)
@@ -357,8 +357,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_fifo_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_fifo_empty_we),
@@ -366,11 +366,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.fifo_empty.q ),
+ .q (reg2hw.intr_enable.fifo_empty.q),
// to register interface (read)
.qs (intr_enable_fifo_empty_qs)
@@ -383,8 +383,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_hmac_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_hmac_err_we),
@@ -392,11 +392,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.hmac_err.q ),
+ .q (reg2hw.intr_enable.hmac_err.q),
// to register interface (read)
.qs (intr_enable_hmac_err_qs)
@@ -415,7 +415,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.hmac_done.qe),
- .q (reg2hw.intr_test.hmac_done.q ),
+ .q (reg2hw.intr_test.hmac_done.q),
.qs ()
);
@@ -430,7 +430,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.fifo_empty.qe),
- .q (reg2hw.intr_test.fifo_empty.q ),
+ .q (reg2hw.intr_test.fifo_empty.q),
.qs ()
);
@@ -445,7 +445,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.hmac_err.qe),
- .q (reg2hw.intr_test.hmac_err.q ),
+ .q (reg2hw.intr_test.hmac_err.q),
.qs ()
);
@@ -461,7 +461,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.qe),
- .q (reg2hw.alert_test.q ),
+ .q (reg2hw.alert_test.q),
.qs ()
);
@@ -478,7 +478,7 @@
.d (hw2reg.cfg.hmac_en.d),
.qre (),
.qe (reg2hw.cfg.hmac_en.qe),
- .q (reg2hw.cfg.hmac_en.q ),
+ .q (reg2hw.cfg.hmac_en.q),
.qs (cfg_hmac_en_qs)
);
@@ -493,7 +493,7 @@
.d (hw2reg.cfg.sha_en.d),
.qre (),
.qe (reg2hw.cfg.sha_en.qe),
- .q (reg2hw.cfg.sha_en.q ),
+ .q (reg2hw.cfg.sha_en.q),
.qs (cfg_sha_en_qs)
);
@@ -508,7 +508,7 @@
.d (hw2reg.cfg.endian_swap.d),
.qre (),
.qe (reg2hw.cfg.endian_swap.qe),
- .q (reg2hw.cfg.endian_swap.q ),
+ .q (reg2hw.cfg.endian_swap.q),
.qs (cfg_endian_swap_qs)
);
@@ -523,7 +523,7 @@
.d (hw2reg.cfg.digest_swap.d),
.qre (),
.qe (reg2hw.cfg.digest_swap.qe),
- .q (reg2hw.cfg.digest_swap.q ),
+ .q (reg2hw.cfg.digest_swap.q),
.qs (cfg_digest_swap_qs)
);
@@ -540,7 +540,7 @@
.d ('0),
.qre (),
.qe (reg2hw.cmd.hash_start.qe),
- .q (reg2hw.cmd.hash_start.q ),
+ .q (reg2hw.cmd.hash_start.q),
.qs ()
);
@@ -555,7 +555,7 @@
.d ('0),
.qre (),
.qe (reg2hw.cmd.hash_process.qe),
- .q (reg2hw.cmd.hash_process.q ),
+ .q (reg2hw.cmd.hash_process.q),
.qs ()
);
@@ -614,15 +614,16 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_err_code (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.de),
- .d (hw2reg.err_code.d ),
+ .d (hw2reg.err_code.d),
// to internal hardware
.qe (),
@@ -644,7 +645,7 @@
.d ('0),
.qre (),
.qe (reg2hw.wipe_secret.qe),
- .q (reg2hw.wipe_secret.q ),
+ .q (reg2hw.wipe_secret.q),
.qs ()
);
@@ -662,7 +663,7 @@
.d (hw2reg.key[0].d),
.qre (),
.qe (reg2hw.key[0].qe),
- .q (reg2hw.key[0].q ),
+ .q (reg2hw.key[0].q),
.qs ()
);
@@ -678,7 +679,7 @@
.d (hw2reg.key[1].d),
.qre (),
.qe (reg2hw.key[1].qe),
- .q (reg2hw.key[1].q ),
+ .q (reg2hw.key[1].q),
.qs ()
);
@@ -694,7 +695,7 @@
.d (hw2reg.key[2].d),
.qre (),
.qe (reg2hw.key[2].qe),
- .q (reg2hw.key[2].q ),
+ .q (reg2hw.key[2].q),
.qs ()
);
@@ -710,7 +711,7 @@
.d (hw2reg.key[3].d),
.qre (),
.qe (reg2hw.key[3].qe),
- .q (reg2hw.key[3].q ),
+ .q (reg2hw.key[3].q),
.qs ()
);
@@ -726,7 +727,7 @@
.d (hw2reg.key[4].d),
.qre (),
.qe (reg2hw.key[4].qe),
- .q (reg2hw.key[4].q ),
+ .q (reg2hw.key[4].q),
.qs ()
);
@@ -742,7 +743,7 @@
.d (hw2reg.key[5].d),
.qre (),
.qe (reg2hw.key[5].qe),
- .q (reg2hw.key[5].q ),
+ .q (reg2hw.key[5].q),
.qs ()
);
@@ -758,7 +759,7 @@
.d (hw2reg.key[6].d),
.qre (),
.qe (reg2hw.key[6].qe),
- .q (reg2hw.key[6].q ),
+ .q (reg2hw.key[6].q),
.qs ()
);
@@ -774,7 +775,7 @@
.d (hw2reg.key[7].d),
.qre (),
.qe (reg2hw.key[7].qe),
- .q (reg2hw.key[7].q ),
+ .q (reg2hw.key[7].q),
.qs ()
);
@@ -916,15 +917,16 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_msg_length_lower (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.msg_length_lower.de),
- .d (hw2reg.msg_length_lower.d ),
+ .d (hw2reg.msg_length_lower.d),
// to internal hardware
.qe (),
@@ -942,15 +944,16 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_msg_length_upper (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.msg_length_upper.de),
- .d (hw2reg.msg_length_upper.d ),
+ .d (hw2reg.msg_length_upper.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/i2c/rtl/i2c_reg_top.sv b/hw/ip/i2c/rtl/i2c_reg_top.sv
index c6f377c..c01e787 100644
--- a/hw/ip/i2c/rtl/i2c_reg_top.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_top.sv
@@ -389,8 +389,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_fmt_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_fmt_watermark_we),
@@ -398,11 +398,11 @@
// from internal hardware
.de (hw2reg.intr_state.fmt_watermark.de),
- .d (hw2reg.intr_state.fmt_watermark.d ),
+ .d (hw2reg.intr_state.fmt_watermark.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.fmt_watermark.q ),
+ .q (reg2hw.intr_state.fmt_watermark.q),
// to register interface (read)
.qs (intr_state_fmt_watermark_qs)
@@ -415,8 +415,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_watermark_we),
@@ -424,11 +424,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_watermark.de),
- .d (hw2reg.intr_state.rx_watermark.d ),
+ .d (hw2reg.intr_state.rx_watermark.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_watermark.q ),
+ .q (reg2hw.intr_state.rx_watermark.q),
// to register interface (read)
.qs (intr_state_rx_watermark_qs)
@@ -441,8 +441,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_fmt_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_fmt_overflow_we),
@@ -450,11 +450,11 @@
// from internal hardware
.de (hw2reg.intr_state.fmt_overflow.de),
- .d (hw2reg.intr_state.fmt_overflow.d ),
+ .d (hw2reg.intr_state.fmt_overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.fmt_overflow.q ),
+ .q (reg2hw.intr_state.fmt_overflow.q),
// to register interface (read)
.qs (intr_state_fmt_overflow_qs)
@@ -467,8 +467,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_overflow_we),
@@ -476,11 +476,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_overflow.de),
- .d (hw2reg.intr_state.rx_overflow.d ),
+ .d (hw2reg.intr_state.rx_overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_overflow.q ),
+ .q (reg2hw.intr_state.rx_overflow.q),
// to register interface (read)
.qs (intr_state_rx_overflow_qs)
@@ -493,8 +493,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_nak (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_nak_we),
@@ -502,11 +502,11 @@
// from internal hardware
.de (hw2reg.intr_state.nak.de),
- .d (hw2reg.intr_state.nak.d ),
+ .d (hw2reg.intr_state.nak.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.nak.q ),
+ .q (reg2hw.intr_state.nak.q),
// to register interface (read)
.qs (intr_state_nak_qs)
@@ -519,8 +519,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_scl_interference (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_scl_interference_we),
@@ -528,11 +528,11 @@
// from internal hardware
.de (hw2reg.intr_state.scl_interference.de),
- .d (hw2reg.intr_state.scl_interference.d ),
+ .d (hw2reg.intr_state.scl_interference.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.scl_interference.q ),
+ .q (reg2hw.intr_state.scl_interference.q),
// to register interface (read)
.qs (intr_state_scl_interference_qs)
@@ -545,8 +545,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_sda_interference (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_sda_interference_we),
@@ -554,11 +554,11 @@
// from internal hardware
.de (hw2reg.intr_state.sda_interference.de),
- .d (hw2reg.intr_state.sda_interference.d ),
+ .d (hw2reg.intr_state.sda_interference.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.sda_interference.q ),
+ .q (reg2hw.intr_state.sda_interference.q),
// to register interface (read)
.qs (intr_state_sda_interference_qs)
@@ -571,8 +571,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_stretch_timeout (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_stretch_timeout_we),
@@ -580,11 +580,11 @@
// from internal hardware
.de (hw2reg.intr_state.stretch_timeout.de),
- .d (hw2reg.intr_state.stretch_timeout.d ),
+ .d (hw2reg.intr_state.stretch_timeout.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.stretch_timeout.q ),
+ .q (reg2hw.intr_state.stretch_timeout.q),
// to register interface (read)
.qs (intr_state_stretch_timeout_qs)
@@ -597,8 +597,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_sda_unstable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_sda_unstable_we),
@@ -606,11 +606,11 @@
// from internal hardware
.de (hw2reg.intr_state.sda_unstable.de),
- .d (hw2reg.intr_state.sda_unstable.d ),
+ .d (hw2reg.intr_state.sda_unstable.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.sda_unstable.q ),
+ .q (reg2hw.intr_state.sda_unstable.q),
// to register interface (read)
.qs (intr_state_sda_unstable_qs)
@@ -623,8 +623,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_trans_complete (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_trans_complete_we),
@@ -632,11 +632,11 @@
// from internal hardware
.de (hw2reg.intr_state.trans_complete.de),
- .d (hw2reg.intr_state.trans_complete.d ),
+ .d (hw2reg.intr_state.trans_complete.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.trans_complete.q ),
+ .q (reg2hw.intr_state.trans_complete.q),
// to register interface (read)
.qs (intr_state_trans_complete_qs)
@@ -649,8 +649,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_tx_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_tx_empty_we),
@@ -658,11 +658,11 @@
// from internal hardware
.de (hw2reg.intr_state.tx_empty.de),
- .d (hw2reg.intr_state.tx_empty.d ),
+ .d (hw2reg.intr_state.tx_empty.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.tx_empty.q ),
+ .q (reg2hw.intr_state.tx_empty.q),
// to register interface (read)
.qs (intr_state_tx_empty_qs)
@@ -675,8 +675,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_tx_nonempty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_tx_nonempty_we),
@@ -684,11 +684,11 @@
// from internal hardware
.de (hw2reg.intr_state.tx_nonempty.de),
- .d (hw2reg.intr_state.tx_nonempty.d ),
+ .d (hw2reg.intr_state.tx_nonempty.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.tx_nonempty.q ),
+ .q (reg2hw.intr_state.tx_nonempty.q),
// to register interface (read)
.qs (intr_state_tx_nonempty_qs)
@@ -701,8 +701,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_tx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_tx_overflow_we),
@@ -710,11 +710,11 @@
// from internal hardware
.de (hw2reg.intr_state.tx_overflow.de),
- .d (hw2reg.intr_state.tx_overflow.d ),
+ .d (hw2reg.intr_state.tx_overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.tx_overflow.q ),
+ .q (reg2hw.intr_state.tx_overflow.q),
// to register interface (read)
.qs (intr_state_tx_overflow_qs)
@@ -727,8 +727,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_acq_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_acq_overflow_we),
@@ -736,11 +736,11 @@
// from internal hardware
.de (hw2reg.intr_state.acq_overflow.de),
- .d (hw2reg.intr_state.acq_overflow.d ),
+ .d (hw2reg.intr_state.acq_overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.acq_overflow.q ),
+ .q (reg2hw.intr_state.acq_overflow.q),
// to register interface (read)
.qs (intr_state_acq_overflow_qs)
@@ -753,8 +753,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_ack_stop (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_ack_stop_we),
@@ -762,11 +762,11 @@
// from internal hardware
.de (hw2reg.intr_state.ack_stop.de),
- .d (hw2reg.intr_state.ack_stop.d ),
+ .d (hw2reg.intr_state.ack_stop.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.ack_stop.q ),
+ .q (reg2hw.intr_state.ack_stop.q),
// to register interface (read)
.qs (intr_state_ack_stop_qs)
@@ -779,8 +779,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_host_timeout (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_host_timeout_we),
@@ -788,11 +788,11 @@
// from internal hardware
.de (hw2reg.intr_state.host_timeout.de),
- .d (hw2reg.intr_state.host_timeout.d ),
+ .d (hw2reg.intr_state.host_timeout.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.host_timeout.q ),
+ .q (reg2hw.intr_state.host_timeout.q),
// to register interface (read)
.qs (intr_state_host_timeout_qs)
@@ -807,8 +807,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_fmt_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_fmt_watermark_we),
@@ -816,11 +816,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.fmt_watermark.q ),
+ .q (reg2hw.intr_enable.fmt_watermark.q),
// to register interface (read)
.qs (intr_enable_fmt_watermark_qs)
@@ -833,8 +833,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_watermark_we),
@@ -842,11 +842,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_watermark.q ),
+ .q (reg2hw.intr_enable.rx_watermark.q),
// to register interface (read)
.qs (intr_enable_rx_watermark_qs)
@@ -859,8 +859,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_fmt_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_fmt_overflow_we),
@@ -868,11 +868,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.fmt_overflow.q ),
+ .q (reg2hw.intr_enable.fmt_overflow.q),
// to register interface (read)
.qs (intr_enable_fmt_overflow_qs)
@@ -885,8 +885,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_overflow_we),
@@ -894,11 +894,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_overflow.q ),
+ .q (reg2hw.intr_enable.rx_overflow.q),
// to register interface (read)
.qs (intr_enable_rx_overflow_qs)
@@ -911,8 +911,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_nak (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_nak_we),
@@ -920,11 +920,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.nak.q ),
+ .q (reg2hw.intr_enable.nak.q),
// to register interface (read)
.qs (intr_enable_nak_qs)
@@ -937,8 +937,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_scl_interference (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_scl_interference_we),
@@ -946,11 +946,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.scl_interference.q ),
+ .q (reg2hw.intr_enable.scl_interference.q),
// to register interface (read)
.qs (intr_enable_scl_interference_qs)
@@ -963,8 +963,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_sda_interference (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_sda_interference_we),
@@ -972,11 +972,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.sda_interference.q ),
+ .q (reg2hw.intr_enable.sda_interference.q),
// to register interface (read)
.qs (intr_enable_sda_interference_qs)
@@ -989,8 +989,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_stretch_timeout (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_stretch_timeout_we),
@@ -998,11 +998,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.stretch_timeout.q ),
+ .q (reg2hw.intr_enable.stretch_timeout.q),
// to register interface (read)
.qs (intr_enable_stretch_timeout_qs)
@@ -1015,8 +1015,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_sda_unstable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_sda_unstable_we),
@@ -1024,11 +1024,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.sda_unstable.q ),
+ .q (reg2hw.intr_enable.sda_unstable.q),
// to register interface (read)
.qs (intr_enable_sda_unstable_qs)
@@ -1041,8 +1041,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_trans_complete (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_trans_complete_we),
@@ -1050,11 +1050,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.trans_complete.q ),
+ .q (reg2hw.intr_enable.trans_complete.q),
// to register interface (read)
.qs (intr_enable_trans_complete_qs)
@@ -1067,8 +1067,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_tx_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_tx_empty_we),
@@ -1076,11 +1076,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.tx_empty.q ),
+ .q (reg2hw.intr_enable.tx_empty.q),
// to register interface (read)
.qs (intr_enable_tx_empty_qs)
@@ -1093,8 +1093,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_tx_nonempty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_tx_nonempty_we),
@@ -1102,11 +1102,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.tx_nonempty.q ),
+ .q (reg2hw.intr_enable.tx_nonempty.q),
// to register interface (read)
.qs (intr_enable_tx_nonempty_qs)
@@ -1119,8 +1119,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_tx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_tx_overflow_we),
@@ -1128,11 +1128,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.tx_overflow.q ),
+ .q (reg2hw.intr_enable.tx_overflow.q),
// to register interface (read)
.qs (intr_enable_tx_overflow_qs)
@@ -1145,8 +1145,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_acq_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_acq_overflow_we),
@@ -1154,11 +1154,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.acq_overflow.q ),
+ .q (reg2hw.intr_enable.acq_overflow.q),
// to register interface (read)
.qs (intr_enable_acq_overflow_qs)
@@ -1171,8 +1171,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_ack_stop (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_ack_stop_we),
@@ -1180,11 +1180,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.ack_stop.q ),
+ .q (reg2hw.intr_enable.ack_stop.q),
// to register interface (read)
.qs (intr_enable_ack_stop_qs)
@@ -1197,8 +1197,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_host_timeout (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_host_timeout_we),
@@ -1206,11 +1206,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.host_timeout.q ),
+ .q (reg2hw.intr_enable.host_timeout.q),
// to register interface (read)
.qs (intr_enable_host_timeout_qs)
@@ -1229,7 +1229,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.fmt_watermark.qe),
- .q (reg2hw.intr_test.fmt_watermark.q ),
+ .q (reg2hw.intr_test.fmt_watermark.q),
.qs ()
);
@@ -1244,7 +1244,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_watermark.qe),
- .q (reg2hw.intr_test.rx_watermark.q ),
+ .q (reg2hw.intr_test.rx_watermark.q),
.qs ()
);
@@ -1259,7 +1259,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.fmt_overflow.qe),
- .q (reg2hw.intr_test.fmt_overflow.q ),
+ .q (reg2hw.intr_test.fmt_overflow.q),
.qs ()
);
@@ -1274,7 +1274,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_overflow.qe),
- .q (reg2hw.intr_test.rx_overflow.q ),
+ .q (reg2hw.intr_test.rx_overflow.q),
.qs ()
);
@@ -1289,7 +1289,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.nak.qe),
- .q (reg2hw.intr_test.nak.q ),
+ .q (reg2hw.intr_test.nak.q),
.qs ()
);
@@ -1304,7 +1304,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.scl_interference.qe),
- .q (reg2hw.intr_test.scl_interference.q ),
+ .q (reg2hw.intr_test.scl_interference.q),
.qs ()
);
@@ -1319,7 +1319,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.sda_interference.qe),
- .q (reg2hw.intr_test.sda_interference.q ),
+ .q (reg2hw.intr_test.sda_interference.q),
.qs ()
);
@@ -1334,7 +1334,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.stretch_timeout.qe),
- .q (reg2hw.intr_test.stretch_timeout.q ),
+ .q (reg2hw.intr_test.stretch_timeout.q),
.qs ()
);
@@ -1349,7 +1349,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.sda_unstable.qe),
- .q (reg2hw.intr_test.sda_unstable.q ),
+ .q (reg2hw.intr_test.sda_unstable.q),
.qs ()
);
@@ -1364,7 +1364,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.trans_complete.qe),
- .q (reg2hw.intr_test.trans_complete.q ),
+ .q (reg2hw.intr_test.trans_complete.q),
.qs ()
);
@@ -1379,7 +1379,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.tx_empty.qe),
- .q (reg2hw.intr_test.tx_empty.q ),
+ .q (reg2hw.intr_test.tx_empty.q),
.qs ()
);
@@ -1394,7 +1394,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.tx_nonempty.qe),
- .q (reg2hw.intr_test.tx_nonempty.q ),
+ .q (reg2hw.intr_test.tx_nonempty.q),
.qs ()
);
@@ -1409,7 +1409,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.tx_overflow.qe),
- .q (reg2hw.intr_test.tx_overflow.q ),
+ .q (reg2hw.intr_test.tx_overflow.q),
.qs ()
);
@@ -1424,7 +1424,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.acq_overflow.qe),
- .q (reg2hw.intr_test.acq_overflow.q ),
+ .q (reg2hw.intr_test.acq_overflow.q),
.qs ()
);
@@ -1439,7 +1439,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.ack_stop.qe),
- .q (reg2hw.intr_test.ack_stop.q ),
+ .q (reg2hw.intr_test.ack_stop.q),
.qs ()
);
@@ -1454,7 +1454,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.host_timeout.qe),
- .q (reg2hw.intr_test.host_timeout.q ),
+ .q (reg2hw.intr_test.host_timeout.q),
.qs ()
);
@@ -1467,8 +1467,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_enablehost (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_enablehost_we),
@@ -1476,11 +1476,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.enablehost.q ),
+ .q (reg2hw.ctrl.enablehost.q),
// to register interface (read)
.qs (ctrl_enablehost_qs)
@@ -1493,8 +1493,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_enabletarget (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_enabletarget_we),
@@ -1502,11 +1502,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.enabletarget.q ),
+ .q (reg2hw.ctrl.enabletarget.q),
// to register interface (read)
.qs (ctrl_enabletarget_qs)
@@ -1519,8 +1519,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_llpbk (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_llpbk_we),
@@ -1528,11 +1528,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.llpbk.q ),
+ .q (reg2hw.ctrl.llpbk.q),
// to register interface (read)
.qs (ctrl_llpbk_qs)
@@ -1702,7 +1702,7 @@
.d (hw2reg.rdata.d),
.qre (reg2hw.rdata.re),
.qe (),
- .q (reg2hw.rdata.q ),
+ .q (reg2hw.rdata.q),
.qs (rdata_qs)
);
@@ -1715,8 +1715,8 @@
.SWACCESS("WO"),
.RESVAL (8'h0)
) u_fdata_fbyte (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fdata_fbyte_we),
@@ -1724,12 +1724,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fdata.fbyte.qe),
- .q (reg2hw.fdata.fbyte.q ),
+ .q (reg2hw.fdata.fbyte.q),
+ // to register interface (read)
.qs ()
);
@@ -1740,8 +1741,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fdata_start (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fdata_start_we),
@@ -1749,12 +1750,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fdata.start.qe),
- .q (reg2hw.fdata.start.q ),
+ .q (reg2hw.fdata.start.q),
+ // to register interface (read)
.qs ()
);
@@ -1765,8 +1767,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fdata_stop (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fdata_stop_we),
@@ -1774,12 +1776,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fdata.stop.qe),
- .q (reg2hw.fdata.stop.q ),
+ .q (reg2hw.fdata.stop.q),
+ // to register interface (read)
.qs ()
);
@@ -1790,8 +1793,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fdata_read (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fdata_read_we),
@@ -1799,12 +1802,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fdata.read.qe),
- .q (reg2hw.fdata.read.q ),
+ .q (reg2hw.fdata.read.q),
+ // to register interface (read)
.qs ()
);
@@ -1815,8 +1819,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fdata_rcont (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fdata_rcont_we),
@@ -1824,12 +1828,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fdata.rcont.qe),
- .q (reg2hw.fdata.rcont.q ),
+ .q (reg2hw.fdata.rcont.q),
+ // to register interface (read)
.qs ()
);
@@ -1840,8 +1845,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fdata_nakok (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fdata_nakok_we),
@@ -1849,12 +1854,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fdata.nakok.qe),
- .q (reg2hw.fdata.nakok.q ),
+ .q (reg2hw.fdata.nakok.q),
+ // to register interface (read)
.qs ()
);
@@ -1867,8 +1873,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fifo_ctrl_rxrst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_rxrst_we),
@@ -1876,12 +1882,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fifo_ctrl.rxrst.qe),
- .q (reg2hw.fifo_ctrl.rxrst.q ),
+ .q (reg2hw.fifo_ctrl.rxrst.q),
+ // to register interface (read)
.qs ()
);
@@ -1892,8 +1899,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fifo_ctrl_fmtrst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_fmtrst_we),
@@ -1901,12 +1908,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fifo_ctrl.fmtrst.qe),
- .q (reg2hw.fifo_ctrl.fmtrst.q ),
+ .q (reg2hw.fifo_ctrl.fmtrst.q),
+ // to register interface (read)
.qs ()
);
@@ -1917,8 +1925,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_fifo_ctrl_rxilvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_rxilvl_we),
@@ -1926,11 +1934,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fifo_ctrl.rxilvl.qe),
- .q (reg2hw.fifo_ctrl.rxilvl.q ),
+ .q (reg2hw.fifo_ctrl.rxilvl.q),
// to register interface (read)
.qs (fifo_ctrl_rxilvl_qs)
@@ -1943,8 +1951,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_fifo_ctrl_fmtilvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_fmtilvl_we),
@@ -1952,11 +1960,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fifo_ctrl.fmtilvl.qe),
- .q (reg2hw.fifo_ctrl.fmtilvl.q ),
+ .q (reg2hw.fifo_ctrl.fmtilvl.q),
// to register interface (read)
.qs (fifo_ctrl_fmtilvl_qs)
@@ -1969,8 +1977,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fifo_ctrl_acqrst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_acqrst_we),
@@ -1978,12 +1986,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fifo_ctrl.acqrst.qe),
- .q (reg2hw.fifo_ctrl.acqrst.q ),
+ .q (reg2hw.fifo_ctrl.acqrst.q),
+ // to register interface (read)
.qs ()
);
@@ -1994,8 +2003,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fifo_ctrl_txrst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_txrst_we),
@@ -2003,12 +2012,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fifo_ctrl.txrst.qe),
- .q (reg2hw.fifo_ctrl.txrst.q ),
+ .q (reg2hw.fifo_ctrl.txrst.q),
+ // to register interface (read)
.qs ()
);
@@ -2083,8 +2093,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ovrd_txovrden (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ovrd_txovrden_we),
@@ -2092,11 +2102,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ovrd.txovrden.q ),
+ .q (reg2hw.ovrd.txovrden.q),
// to register interface (read)
.qs (ovrd_txovrden_qs)
@@ -2109,8 +2119,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ovrd_sclval (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ovrd_sclval_we),
@@ -2118,11 +2128,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ovrd.sclval.q ),
+ .q (reg2hw.ovrd.sclval.q),
// to register interface (read)
.qs (ovrd_sclval_qs)
@@ -2135,8 +2145,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ovrd_sdaval (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ovrd_sdaval_we),
@@ -2144,11 +2154,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ovrd.sdaval.q ),
+ .q (reg2hw.ovrd.sdaval.q),
// to register interface (read)
.qs (ovrd_sdaval_qs)
@@ -2195,8 +2205,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing0_thigh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing0_thigh_we),
@@ -2204,11 +2214,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing0.thigh.q ),
+ .q (reg2hw.timing0.thigh.q),
// to register interface (read)
.qs (timing0_thigh_qs)
@@ -2221,8 +2231,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing0_tlow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing0_tlow_we),
@@ -2230,11 +2240,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing0.tlow.q ),
+ .q (reg2hw.timing0.tlow.q),
// to register interface (read)
.qs (timing0_tlow_qs)
@@ -2249,8 +2259,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing1_t_r (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing1_t_r_we),
@@ -2258,11 +2268,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing1.t_r.q ),
+ .q (reg2hw.timing1.t_r.q),
// to register interface (read)
.qs (timing1_t_r_qs)
@@ -2275,8 +2285,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing1_t_f (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing1_t_f_we),
@@ -2284,11 +2294,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing1.t_f.q ),
+ .q (reg2hw.timing1.t_f.q),
// to register interface (read)
.qs (timing1_t_f_qs)
@@ -2303,8 +2313,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing2_tsu_sta (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing2_tsu_sta_we),
@@ -2312,11 +2322,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing2.tsu_sta.q ),
+ .q (reg2hw.timing2.tsu_sta.q),
// to register interface (read)
.qs (timing2_tsu_sta_qs)
@@ -2329,8 +2339,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing2_thd_sta (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing2_thd_sta_we),
@@ -2338,11 +2348,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing2.thd_sta.q ),
+ .q (reg2hw.timing2.thd_sta.q),
// to register interface (read)
.qs (timing2_thd_sta_qs)
@@ -2357,8 +2367,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing3_tsu_dat (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing3_tsu_dat_we),
@@ -2366,11 +2376,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing3.tsu_dat.q ),
+ .q (reg2hw.timing3.tsu_dat.q),
// to register interface (read)
.qs (timing3_tsu_dat_qs)
@@ -2383,8 +2393,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing3_thd_dat (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing3_thd_dat_we),
@@ -2392,11 +2402,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing3.thd_dat.q ),
+ .q (reg2hw.timing3.thd_dat.q),
// to register interface (read)
.qs (timing3_thd_dat_qs)
@@ -2411,8 +2421,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing4_tsu_sto (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing4_tsu_sto_we),
@@ -2420,11 +2430,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing4.tsu_sto.q ),
+ .q (reg2hw.timing4.tsu_sto.q),
// to register interface (read)
.qs (timing4_tsu_sto_qs)
@@ -2437,8 +2447,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_timing4_t_buf (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timing4_t_buf_we),
@@ -2446,11 +2456,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timing4.t_buf.q ),
+ .q (reg2hw.timing4.t_buf.q),
// to register interface (read)
.qs (timing4_t_buf_qs)
@@ -2465,8 +2475,8 @@
.SWACCESS("RW"),
.RESVAL (31'h0)
) u_timeout_ctrl_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timeout_ctrl_val_we),
@@ -2474,11 +2484,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timeout_ctrl.val.q ),
+ .q (reg2hw.timeout_ctrl.val.q),
// to register interface (read)
.qs (timeout_ctrl_val_qs)
@@ -2491,8 +2501,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_timeout_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timeout_ctrl_en_we),
@@ -2500,11 +2510,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timeout_ctrl.en.q ),
+ .q (reg2hw.timeout_ctrl.en.q),
// to register interface (read)
.qs (timeout_ctrl_en_qs)
@@ -2519,8 +2529,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_target_id_address0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (target_id_address0_we),
@@ -2528,11 +2538,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.target_id.address0.q ),
+ .q (reg2hw.target_id.address0.q),
// to register interface (read)
.qs (target_id_address0_qs)
@@ -2545,8 +2555,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_target_id_mask0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (target_id_mask0_we),
@@ -2554,11 +2564,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.target_id.mask0.q ),
+ .q (reg2hw.target_id.mask0.q),
// to register interface (read)
.qs (target_id_mask0_qs)
@@ -2571,8 +2581,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_target_id_address1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (target_id_address1_we),
@@ -2580,11 +2590,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.target_id.address1.q ),
+ .q (reg2hw.target_id.address1.q),
// to register interface (read)
.qs (target_id_address1_qs)
@@ -2597,8 +2607,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_target_id_mask1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (target_id_mask1_we),
@@ -2606,11 +2616,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.target_id.mask1.q ),
+ .q (reg2hw.target_id.mask1.q),
// to register interface (read)
.qs (target_id_mask1_qs)
@@ -2629,7 +2639,7 @@
.d (hw2reg.acqdata.abyte.d),
.qre (reg2hw.acqdata.abyte.re),
.qe (),
- .q (reg2hw.acqdata.abyte.q ),
+ .q (reg2hw.acqdata.abyte.q),
.qs (acqdata_abyte_qs)
);
@@ -2644,7 +2654,7 @@
.d (hw2reg.acqdata.signal.d),
.qre (reg2hw.acqdata.signal.re),
.qe (),
- .q (reg2hw.acqdata.signal.q ),
+ .q (reg2hw.acqdata.signal.q),
.qs (acqdata_signal_qs)
);
@@ -2656,8 +2666,8 @@
.SWACCESS("WO"),
.RESVAL (8'h0)
) u_txdata (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (txdata_we),
@@ -2665,12 +2675,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.txdata.qe),
- .q (reg2hw.txdata.q ),
+ .q (reg2hw.txdata.q),
+ // to register interface (read)
.qs ()
);
@@ -2683,8 +2694,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stretch_ctrl_en_addr_tx (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stretch_ctrl_en_addr_tx_we),
@@ -2692,11 +2703,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.stretch_ctrl.en_addr_tx.q ),
+ .q (reg2hw.stretch_ctrl.en_addr_tx.q),
// to register interface (read)
.qs (stretch_ctrl_en_addr_tx_qs)
@@ -2709,8 +2720,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stretch_ctrl_en_addr_acq (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stretch_ctrl_en_addr_acq_we),
@@ -2718,11 +2729,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.stretch_ctrl.en_addr_acq.q ),
+ .q (reg2hw.stretch_ctrl.en_addr_acq.q),
// to register interface (read)
.qs (stretch_ctrl_en_addr_acq_qs)
@@ -2735,8 +2746,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stretch_ctrl_stop_tx (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stretch_ctrl_stop_tx_we),
@@ -2744,11 +2755,11 @@
// from internal hardware
.de (hw2reg.stretch_ctrl.stop_tx.de),
- .d (hw2reg.stretch_ctrl.stop_tx.d ),
+ .d (hw2reg.stretch_ctrl.stop_tx.d),
// to internal hardware
.qe (),
- .q (reg2hw.stretch_ctrl.stop_tx.q ),
+ .q (reg2hw.stretch_ctrl.stop_tx.q),
// to register interface (read)
.qs (stretch_ctrl_stop_tx_qs)
@@ -2761,8 +2772,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stretch_ctrl_stop_acq (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stretch_ctrl_stop_acq_we),
@@ -2770,11 +2781,11 @@
// from internal hardware
.de (hw2reg.stretch_ctrl.stop_acq.de),
- .d (hw2reg.stretch_ctrl.stop_acq.d ),
+ .d (hw2reg.stretch_ctrl.stop_acq.d),
// to internal hardware
.qe (),
- .q (reg2hw.stretch_ctrl.stop_acq.q ),
+ .q (reg2hw.stretch_ctrl.stop_acq.q),
// to register interface (read)
.qs (stretch_ctrl_stop_acq_qs)
@@ -2788,8 +2799,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_host_timeout_ctrl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (host_timeout_ctrl_we),
@@ -2797,11 +2808,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.host_timeout_ctrl.q ),
+ .q (reg2hw.host_timeout_ctrl.q),
// to register interface (read)
.qs (host_timeout_ctrl_qs)
diff --git a/hw/ip/keymgr/rtl/keymgr_reg_top.sv b/hw/ip/keymgr/rtl/keymgr_reg_top.sv
index b7c8fb9..bb2eefe 100644
--- a/hw/ip/keymgr/rtl/keymgr_reg_top.sv
+++ b/hw/ip/keymgr/rtl/keymgr_reg_top.sv
@@ -279,8 +279,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
@@ -288,11 +288,11 @@
// from internal hardware
.de (hw2reg.intr_state.de),
- .d (hw2reg.intr_state.d ),
+ .d (hw2reg.intr_state.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.q ),
+ .q (reg2hw.intr_state.q),
// to register interface (read)
.qs (intr_state_qs)
@@ -306,8 +306,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
@@ -315,11 +315,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.q ),
+ .q (reg2hw.intr_enable.q),
// to register interface (read)
.qs (intr_enable_qs)
@@ -337,7 +337,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.qe),
- .q (reg2hw.intr_test.q ),
+ .q (reg2hw.intr_test.q),
.qs ()
);
@@ -354,7 +354,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_fault_err.qe),
- .q (reg2hw.alert_test.fatal_fault_err.q ),
+ .q (reg2hw.alert_test.fatal_fault_err.q),
.qs ()
);
@@ -369,7 +369,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_operation_err.qe),
- .q (reg2hw.alert_test.recov_operation_err.q ),
+ .q (reg2hw.alert_test.recov_operation_err.q),
.qs ()
);
@@ -398,20 +398,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_start (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_start_we & cfg_regwen_qs),
.wd (control_start_wd),
// from internal hardware
.de (hw2reg.control.start.de),
- .d (hw2reg.control.start.d ),
+ .d (hw2reg.control.start.d),
// to internal hardware
.qe (),
- .q (reg2hw.control.start.q ),
+ .q (reg2hw.control.start.q),
// to register interface (read)
.qs (control_start_qs)
@@ -424,20 +424,20 @@
.SWACCESS("RW"),
.RESVAL (3'h1)
) u_control_operation (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_operation_we & cfg_regwen_qs),
.wd (control_operation_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.operation.q ),
+ .q (reg2hw.control.operation.q),
// to register interface (read)
.qs (control_operation_qs)
@@ -450,20 +450,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_control_dest_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_dest_sel_we & cfg_regwen_qs),
.wd (control_dest_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.dest_sel.q ),
+ .q (reg2hw.control.dest_sel.q),
// to register interface (read)
.qs (control_dest_sel_qs)
@@ -477,8 +477,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_sideload_clear (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sideload_clear_we),
@@ -486,11 +486,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sideload_clear.q ),
+ .q (reg2hw.sideload_clear.q),
// to register interface (read)
.qs (sideload_clear_qs)
@@ -504,8 +504,8 @@
.SWACCESS("RW"),
.RESVAL (16'h100)
) u_reseed_interval (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reseed_interval_we),
@@ -513,11 +513,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.reseed_interval.q ),
+ .q (reg2hw.reseed_interval.q),
// to register interface (read)
.qs (reseed_interval_qs)
@@ -535,7 +535,7 @@
.d (hw2reg.sw_binding_regwen.d),
.qre (),
.qe (reg2hw.sw_binding_regwen.qe),
- .q (reg2hw.sw_binding_regwen.q ),
+ .q (reg2hw.sw_binding_regwen.q),
.qs (sw_binding_regwen_qs)
);
@@ -549,20 +549,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_sw_binding_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (sw_binding_0_we & sw_binding_regwen_qs),
.wd (sw_binding_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_binding[0].q ),
+ .q (reg2hw.sw_binding[0].q),
// to register interface (read)
.qs (sw_binding_0_qs)
@@ -576,20 +576,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_sw_binding_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (sw_binding_1_we & sw_binding_regwen_qs),
.wd (sw_binding_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_binding[1].q ),
+ .q (reg2hw.sw_binding[1].q),
// to register interface (read)
.qs (sw_binding_1_qs)
@@ -603,20 +603,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_sw_binding_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (sw_binding_2_we & sw_binding_regwen_qs),
.wd (sw_binding_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_binding[2].q ),
+ .q (reg2hw.sw_binding[2].q),
// to register interface (read)
.qs (sw_binding_2_qs)
@@ -630,20 +630,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_sw_binding_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (sw_binding_3_we & sw_binding_regwen_qs),
.wd (sw_binding_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_binding[3].q ),
+ .q (reg2hw.sw_binding[3].q),
// to register interface (read)
.qs (sw_binding_3_qs)
@@ -657,20 +657,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_sw_binding_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (sw_binding_4_we & sw_binding_regwen_qs),
.wd (sw_binding_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_binding[4].q ),
+ .q (reg2hw.sw_binding[4].q),
// to register interface (read)
.qs (sw_binding_4_qs)
@@ -684,20 +684,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_sw_binding_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (sw_binding_5_we & sw_binding_regwen_qs),
.wd (sw_binding_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_binding[5].q ),
+ .q (reg2hw.sw_binding[5].q),
// to register interface (read)
.qs (sw_binding_5_qs)
@@ -711,20 +711,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_sw_binding_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (sw_binding_6_we & sw_binding_regwen_qs),
.wd (sw_binding_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_binding[6].q ),
+ .q (reg2hw.sw_binding[6].q),
// to register interface (read)
.qs (sw_binding_6_qs)
@@ -738,20 +738,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_sw_binding_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (sw_binding_7_we & sw_binding_regwen_qs),
.wd (sw_binding_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_binding[7].q ),
+ .q (reg2hw.sw_binding[7].q),
// to register interface (read)
.qs (sw_binding_7_qs)
@@ -767,20 +767,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_salt_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (salt_0_we & cfg_regwen_qs),
.wd (salt_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.salt[0].q ),
+ .q (reg2hw.salt[0].q),
// to register interface (read)
.qs (salt_0_qs)
@@ -794,20 +794,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_salt_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (salt_1_we & cfg_regwen_qs),
.wd (salt_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.salt[1].q ),
+ .q (reg2hw.salt[1].q),
// to register interface (read)
.qs (salt_1_qs)
@@ -821,20 +821,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_salt_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (salt_2_we & cfg_regwen_qs),
.wd (salt_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.salt[2].q ),
+ .q (reg2hw.salt[2].q),
// to register interface (read)
.qs (salt_2_qs)
@@ -848,20 +848,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_salt_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (salt_3_we & cfg_regwen_qs),
.wd (salt_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.salt[3].q ),
+ .q (reg2hw.salt[3].q),
// to register interface (read)
.qs (salt_3_qs)
@@ -875,20 +875,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_salt_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (salt_4_we & cfg_regwen_qs),
.wd (salt_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.salt[4].q ),
+ .q (reg2hw.salt[4].q),
// to register interface (read)
.qs (salt_4_qs)
@@ -902,20 +902,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_salt_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (salt_5_we & cfg_regwen_qs),
.wd (salt_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.salt[5].q ),
+ .q (reg2hw.salt[5].q),
// to register interface (read)
.qs (salt_5_qs)
@@ -929,20 +929,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_salt_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (salt_6_we & cfg_regwen_qs),
.wd (salt_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.salt[6].q ),
+ .q (reg2hw.salt[6].q),
// to register interface (read)
.qs (salt_6_qs)
@@ -956,20 +956,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_salt_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (salt_7_we & cfg_regwen_qs),
.wd (salt_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.salt[7].q ),
+ .q (reg2hw.salt[7].q),
// to register interface (read)
.qs (salt_7_qs)
@@ -985,20 +985,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_key_version (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_version_we & cfg_regwen_qs),
.wd (key_version_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_version[0].q ),
+ .q (reg2hw.key_version[0].q),
// to register interface (read)
.qs (key_version_qs)
@@ -1012,8 +1012,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_max_creator_key_ver_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (max_creator_key_ver_regwen_we),
@@ -1021,7 +1021,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1039,20 +1039,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_max_creator_key_ver (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (max_creator_key_ver_we & max_creator_key_ver_regwen_qs),
.wd (max_creator_key_ver_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.max_creator_key_ver.q ),
+ .q (reg2hw.max_creator_key_ver.q),
// to register interface (read)
.qs (max_creator_key_ver_qs)
@@ -1066,8 +1066,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_max_owner_int_key_ver_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (max_owner_int_key_ver_regwen_we),
@@ -1075,7 +1075,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1093,20 +1093,20 @@
.SWACCESS("RW"),
.RESVAL (32'h1)
) u_max_owner_int_key_ver (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (max_owner_int_key_ver_we & max_owner_int_key_ver_regwen_qs),
.wd (max_owner_int_key_ver_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.max_owner_int_key_ver.q ),
+ .q (reg2hw.max_owner_int_key_ver.q),
// to register interface (read)
.qs (max_owner_int_key_ver_qs)
@@ -1120,8 +1120,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_max_owner_key_ver_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (max_owner_key_ver_regwen_we),
@@ -1129,7 +1129,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1147,20 +1147,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_max_owner_key_ver (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (max_owner_key_ver_we & max_owner_key_ver_regwen_qs),
.wd (max_owner_key_ver_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.max_owner_key_ver.q ),
+ .q (reg2hw.max_owner_key_ver.q),
// to register interface (read)
.qs (max_owner_key_ver_qs)
@@ -1176,8 +1176,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share0_output_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_0_we),
@@ -1185,7 +1185,7 @@
// from internal hardware
.de (hw2reg.sw_share0_output[0].de),
- .d (hw2reg.sw_share0_output[0].d ),
+ .d (hw2reg.sw_share0_output[0].d),
// to internal hardware
.qe (),
@@ -1203,8 +1203,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share0_output_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_1_we),
@@ -1212,7 +1212,7 @@
// from internal hardware
.de (hw2reg.sw_share0_output[1].de),
- .d (hw2reg.sw_share0_output[1].d ),
+ .d (hw2reg.sw_share0_output[1].d),
// to internal hardware
.qe (),
@@ -1230,8 +1230,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share0_output_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_2_we),
@@ -1239,7 +1239,7 @@
// from internal hardware
.de (hw2reg.sw_share0_output[2].de),
- .d (hw2reg.sw_share0_output[2].d ),
+ .d (hw2reg.sw_share0_output[2].d),
// to internal hardware
.qe (),
@@ -1257,8 +1257,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share0_output_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_3_we),
@@ -1266,7 +1266,7 @@
// from internal hardware
.de (hw2reg.sw_share0_output[3].de),
- .d (hw2reg.sw_share0_output[3].d ),
+ .d (hw2reg.sw_share0_output[3].d),
// to internal hardware
.qe (),
@@ -1284,8 +1284,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share0_output_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_4_we),
@@ -1293,7 +1293,7 @@
// from internal hardware
.de (hw2reg.sw_share0_output[4].de),
- .d (hw2reg.sw_share0_output[4].d ),
+ .d (hw2reg.sw_share0_output[4].d),
// to internal hardware
.qe (),
@@ -1311,8 +1311,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share0_output_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_5_we),
@@ -1320,7 +1320,7 @@
// from internal hardware
.de (hw2reg.sw_share0_output[5].de),
- .d (hw2reg.sw_share0_output[5].d ),
+ .d (hw2reg.sw_share0_output[5].d),
// to internal hardware
.qe (),
@@ -1338,8 +1338,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share0_output_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_6_we),
@@ -1347,7 +1347,7 @@
// from internal hardware
.de (hw2reg.sw_share0_output[6].de),
- .d (hw2reg.sw_share0_output[6].d ),
+ .d (hw2reg.sw_share0_output[6].d),
// to internal hardware
.qe (),
@@ -1365,8 +1365,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share0_output_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share0_output_7_we),
@@ -1374,7 +1374,7 @@
// from internal hardware
.de (hw2reg.sw_share0_output[7].de),
- .d (hw2reg.sw_share0_output[7].d ),
+ .d (hw2reg.sw_share0_output[7].d),
// to internal hardware
.qe (),
@@ -1394,8 +1394,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share1_output_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_0_we),
@@ -1403,7 +1403,7 @@
// from internal hardware
.de (hw2reg.sw_share1_output[0].de),
- .d (hw2reg.sw_share1_output[0].d ),
+ .d (hw2reg.sw_share1_output[0].d),
// to internal hardware
.qe (),
@@ -1421,8 +1421,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share1_output_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_1_we),
@@ -1430,7 +1430,7 @@
// from internal hardware
.de (hw2reg.sw_share1_output[1].de),
- .d (hw2reg.sw_share1_output[1].d ),
+ .d (hw2reg.sw_share1_output[1].d),
// to internal hardware
.qe (),
@@ -1448,8 +1448,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share1_output_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_2_we),
@@ -1457,7 +1457,7 @@
// from internal hardware
.de (hw2reg.sw_share1_output[2].de),
- .d (hw2reg.sw_share1_output[2].d ),
+ .d (hw2reg.sw_share1_output[2].d),
// to internal hardware
.qe (),
@@ -1475,8 +1475,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share1_output_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_3_we),
@@ -1484,7 +1484,7 @@
// from internal hardware
.de (hw2reg.sw_share1_output[3].de),
- .d (hw2reg.sw_share1_output[3].d ),
+ .d (hw2reg.sw_share1_output[3].d),
// to internal hardware
.qe (),
@@ -1502,8 +1502,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share1_output_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_4_we),
@@ -1511,7 +1511,7 @@
// from internal hardware
.de (hw2reg.sw_share1_output[4].de),
- .d (hw2reg.sw_share1_output[4].d ),
+ .d (hw2reg.sw_share1_output[4].d),
// to internal hardware
.qe (),
@@ -1529,8 +1529,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share1_output_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_5_we),
@@ -1538,7 +1538,7 @@
// from internal hardware
.de (hw2reg.sw_share1_output[5].de),
- .d (hw2reg.sw_share1_output[5].d ),
+ .d (hw2reg.sw_share1_output[5].d),
// to internal hardware
.qe (),
@@ -1556,8 +1556,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share1_output_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_6_we),
@@ -1565,7 +1565,7 @@
// from internal hardware
.de (hw2reg.sw_share1_output[6].de),
- .d (hw2reg.sw_share1_output[6].d ),
+ .d (hw2reg.sw_share1_output[6].d),
// to internal hardware
.qe (),
@@ -1583,8 +1583,8 @@
.SWACCESS("RC"),
.RESVAL (32'h0)
) u_sw_share1_output_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_share1_output_7_we),
@@ -1592,7 +1592,7 @@
// from internal hardware
.de (hw2reg.sw_share1_output[7].de),
- .d (hw2reg.sw_share1_output[7].d ),
+ .d (hw2reg.sw_share1_output[7].d),
// to internal hardware
.qe (),
@@ -1610,15 +1610,16 @@
.SWACCESS("RO"),
.RESVAL (3'h0)
) u_working_state (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.working_state.de),
- .d (hw2reg.working_state.d ),
+ .d (hw2reg.working_state.d),
// to internal hardware
.qe (),
@@ -1636,8 +1637,8 @@
.SWACCESS("W1C"),
.RESVAL (2'h0)
) u_op_status (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (op_status_we),
@@ -1645,7 +1646,7 @@
// from internal hardware
.de (hw2reg.op_status.de),
- .d (hw2reg.op_status.d ),
+ .d (hw2reg.op_status.d),
// to internal hardware
.qe (),
@@ -1664,8 +1665,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_invalid_op (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_invalid_op_we),
@@ -1673,11 +1674,11 @@
// from internal hardware
.de (hw2reg.err_code.invalid_op.de),
- .d (hw2reg.err_code.invalid_op.d ),
+ .d (hw2reg.err_code.invalid_op.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.invalid_op.q ),
+ .q (reg2hw.err_code.invalid_op.q),
// to register interface (read)
.qs (err_code_invalid_op_qs)
@@ -1690,8 +1691,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_invalid_cmd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_invalid_cmd_we),
@@ -1699,11 +1700,11 @@
// from internal hardware
.de (hw2reg.err_code.invalid_cmd.de),
- .d (hw2reg.err_code.invalid_cmd.d ),
+ .d (hw2reg.err_code.invalid_cmd.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.invalid_cmd.q ),
+ .q (reg2hw.err_code.invalid_cmd.q),
// to register interface (read)
.qs (err_code_invalid_cmd_qs)
@@ -1716,8 +1717,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_invalid_kmac_input (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_invalid_kmac_input_we),
@@ -1725,11 +1726,11 @@
// from internal hardware
.de (hw2reg.err_code.invalid_kmac_input.de),
- .d (hw2reg.err_code.invalid_kmac_input.d ),
+ .d (hw2reg.err_code.invalid_kmac_input.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.invalid_kmac_input.q ),
+ .q (reg2hw.err_code.invalid_kmac_input.q),
// to register interface (read)
.qs (err_code_invalid_kmac_input_qs)
@@ -1742,8 +1743,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_invalid_kmac_data (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_invalid_kmac_data_we),
@@ -1751,11 +1752,11 @@
// from internal hardware
.de (hw2reg.err_code.invalid_kmac_data.de),
- .d (hw2reg.err_code.invalid_kmac_data.d ),
+ .d (hw2reg.err_code.invalid_kmac_data.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.invalid_kmac_data.q ),
+ .q (reg2hw.err_code.invalid_kmac_data.q),
// to register interface (read)
.qs (err_code_invalid_kmac_data_qs)
diff --git a/hw/ip/kmac/rtl/kmac_reg_top.sv b/hw/ip/kmac/rtl/kmac_reg_top.sv
index a136609..88713af 100644
--- a/hw/ip/kmac/rtl/kmac_reg_top.sv
+++ b/hw/ip/kmac/rtl/kmac_reg_top.sv
@@ -351,8 +351,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_kmac_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_kmac_done_we),
@@ -360,11 +360,11 @@
// from internal hardware
.de (hw2reg.intr_state.kmac_done.de),
- .d (hw2reg.intr_state.kmac_done.d ),
+ .d (hw2reg.intr_state.kmac_done.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.kmac_done.q ),
+ .q (reg2hw.intr_state.kmac_done.q),
// to register interface (read)
.qs (intr_state_kmac_done_qs)
@@ -377,8 +377,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_fifo_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_fifo_empty_we),
@@ -386,11 +386,11 @@
// from internal hardware
.de (hw2reg.intr_state.fifo_empty.de),
- .d (hw2reg.intr_state.fifo_empty.d ),
+ .d (hw2reg.intr_state.fifo_empty.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.fifo_empty.q ),
+ .q (reg2hw.intr_state.fifo_empty.q),
// to register interface (read)
.qs (intr_state_fifo_empty_qs)
@@ -403,8 +403,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_kmac_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_kmac_err_we),
@@ -412,11 +412,11 @@
// from internal hardware
.de (hw2reg.intr_state.kmac_err.de),
- .d (hw2reg.intr_state.kmac_err.d ),
+ .d (hw2reg.intr_state.kmac_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.kmac_err.q ),
+ .q (reg2hw.intr_state.kmac_err.q),
// to register interface (read)
.qs (intr_state_kmac_err_qs)
@@ -431,8 +431,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_kmac_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_kmac_done_we),
@@ -440,11 +440,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.kmac_done.q ),
+ .q (reg2hw.intr_enable.kmac_done.q),
// to register interface (read)
.qs (intr_enable_kmac_done_qs)
@@ -457,8 +457,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_fifo_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_fifo_empty_we),
@@ -466,11 +466,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.fifo_empty.q ),
+ .q (reg2hw.intr_enable.fifo_empty.q),
// to register interface (read)
.qs (intr_enable_fifo_empty_qs)
@@ -483,8 +483,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_kmac_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_kmac_err_we),
@@ -492,11 +492,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.kmac_err.q ),
+ .q (reg2hw.intr_enable.kmac_err.q),
// to register interface (read)
.qs (intr_enable_kmac_err_qs)
@@ -515,7 +515,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.kmac_done.qe),
- .q (reg2hw.intr_test.kmac_done.q ),
+ .q (reg2hw.intr_test.kmac_done.q),
.qs ()
);
@@ -530,7 +530,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.fifo_empty.qe),
- .q (reg2hw.intr_test.fifo_empty.q ),
+ .q (reg2hw.intr_test.fifo_empty.q),
.qs ()
);
@@ -545,7 +545,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.kmac_err.qe),
- .q (reg2hw.intr_test.kmac_err.q ),
+ .q (reg2hw.intr_test.kmac_err.q),
.qs ()
);
@@ -561,7 +561,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.qe),
- .q (reg2hw.alert_test.q ),
+ .q (reg2hw.alert_test.q),
.qs ()
);
@@ -590,20 +590,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_kmac_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_kmac_en_we & cfg_regwen_qs),
.wd (cfg_kmac_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.kmac_en.q ),
+ .q (reg2hw.cfg.kmac_en.q),
// to register interface (read)
.qs (cfg_kmac_en_qs)
@@ -616,20 +616,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_cfg_kstrength (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_kstrength_we & cfg_regwen_qs),
.wd (cfg_kstrength_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.kstrength.q ),
+ .q (reg2hw.cfg.kstrength.q),
// to register interface (read)
.qs (cfg_kstrength_qs)
@@ -642,20 +642,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_cfg_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_mode_we & cfg_regwen_qs),
.wd (cfg_mode_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.mode.q ),
+ .q (reg2hw.cfg.mode.q),
// to register interface (read)
.qs (cfg_mode_qs)
@@ -668,20 +668,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_msg_endianness (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_msg_endianness_we & cfg_regwen_qs),
.wd (cfg_msg_endianness_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.msg_endianness.q ),
+ .q (reg2hw.cfg.msg_endianness.q),
// to register interface (read)
.qs (cfg_msg_endianness_qs)
@@ -694,20 +694,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_state_endianness (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_state_endianness_we & cfg_regwen_qs),
.wd (cfg_state_endianness_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.state_endianness.q ),
+ .q (reg2hw.cfg.state_endianness.q),
// to register interface (read)
.qs (cfg_state_endianness_qs)
@@ -720,20 +720,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_sideload (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_sideload_we & cfg_regwen_qs),
.wd (cfg_sideload_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.sideload.q ),
+ .q (reg2hw.cfg.sideload.q),
// to register interface (read)
.qs (cfg_sideload_qs)
@@ -746,20 +746,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_cfg_entropy_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_entropy_mode_we & cfg_regwen_qs),
.wd (cfg_entropy_mode_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.entropy_mode.q ),
+ .q (reg2hw.cfg.entropy_mode.q),
// to register interface (read)
.qs (cfg_entropy_mode_qs)
@@ -772,20 +772,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_entropy_fast_process (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_entropy_fast_process_we & cfg_regwen_qs),
.wd (cfg_entropy_fast_process_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.entropy_fast_process.q ),
+ .q (reg2hw.cfg.entropy_fast_process.q),
// to register interface (read)
.qs (cfg_entropy_fast_process_qs)
@@ -798,20 +798,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_entropy_ready (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_entropy_ready_we & cfg_regwen_qs),
.wd (cfg_entropy_ready_wd),
// from internal hardware
.de (hw2reg.cfg.entropy_ready.de),
- .d (hw2reg.cfg.entropy_ready.d ),
+ .d (hw2reg.cfg.entropy_ready.d),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.entropy_ready.q ),
+ .q (reg2hw.cfg.entropy_ready.q),
// to register interface (read)
.qs (cfg_entropy_ready_qs)
@@ -824,20 +824,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_err_processed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cfg_err_processed_we & cfg_regwen_qs),
.wd (cfg_err_processed_wd),
// from internal hardware
.de (hw2reg.cfg.err_processed.de),
- .d (hw2reg.cfg.err_processed.d ),
+ .d (hw2reg.cfg.err_processed.d),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.err_processed.q ),
+ .q (reg2hw.cfg.err_processed.q),
// to register interface (read)
.qs (cfg_err_processed_qs)
@@ -855,7 +855,7 @@
.d ('0),
.qre (),
.qe (reg2hw.cmd.qe),
- .q (reg2hw.cmd.q ),
+ .q (reg2hw.cmd.q),
.qs ()
);
@@ -960,20 +960,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_entropy_period_entropy_timer (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (entropy_period_entropy_timer_we & cfg_regwen_qs),
.wd (entropy_period_entropy_timer_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.entropy_period.entropy_timer.q ),
+ .q (reg2hw.entropy_period.entropy_timer.q),
// to register interface (read)
.qs (entropy_period_entropy_timer_qs)
@@ -986,20 +986,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_entropy_period_wait_timer (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (entropy_period_wait_timer_we & cfg_regwen_qs),
.wd (entropy_period_wait_timer_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.entropy_period.wait_timer.q ),
+ .q (reg2hw.entropy_period.wait_timer.q),
// to register interface (read)
.qs (entropy_period_wait_timer_qs)
@@ -1013,20 +1013,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_entropy_seed_lower (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (entropy_seed_lower_we & cfg_regwen_qs),
.wd (entropy_seed_lower_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.entropy_seed_lower.qe),
- .q (reg2hw.entropy_seed_lower.q ),
+ .q (reg2hw.entropy_seed_lower.q),
// to register interface (read)
.qs (entropy_seed_lower_qs)
@@ -1040,20 +1040,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_entropy_seed_upper (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (entropy_seed_upper_we & cfg_regwen_qs),
.wd (entropy_seed_upper_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.entropy_seed_upper.qe),
- .q (reg2hw.entropy_seed_upper.q ),
+ .q (reg2hw.entropy_seed_upper.q),
// to register interface (read)
.qs (entropy_seed_upper_qs)
@@ -1073,7 +1073,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[0].qe),
- .q (reg2hw.key_share0[0].q ),
+ .q (reg2hw.key_share0[0].q),
.qs ()
);
@@ -1089,7 +1089,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[1].qe),
- .q (reg2hw.key_share0[1].q ),
+ .q (reg2hw.key_share0[1].q),
.qs ()
);
@@ -1105,7 +1105,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[2].qe),
- .q (reg2hw.key_share0[2].q ),
+ .q (reg2hw.key_share0[2].q),
.qs ()
);
@@ -1121,7 +1121,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[3].qe),
- .q (reg2hw.key_share0[3].q ),
+ .q (reg2hw.key_share0[3].q),
.qs ()
);
@@ -1137,7 +1137,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[4].qe),
- .q (reg2hw.key_share0[4].q ),
+ .q (reg2hw.key_share0[4].q),
.qs ()
);
@@ -1153,7 +1153,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[5].qe),
- .q (reg2hw.key_share0[5].q ),
+ .q (reg2hw.key_share0[5].q),
.qs ()
);
@@ -1169,7 +1169,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[6].qe),
- .q (reg2hw.key_share0[6].q ),
+ .q (reg2hw.key_share0[6].q),
.qs ()
);
@@ -1185,7 +1185,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[7].qe),
- .q (reg2hw.key_share0[7].q ),
+ .q (reg2hw.key_share0[7].q),
.qs ()
);
@@ -1201,7 +1201,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[8].qe),
- .q (reg2hw.key_share0[8].q ),
+ .q (reg2hw.key_share0[8].q),
.qs ()
);
@@ -1217,7 +1217,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[9].qe),
- .q (reg2hw.key_share0[9].q ),
+ .q (reg2hw.key_share0[9].q),
.qs ()
);
@@ -1233,7 +1233,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[10].qe),
- .q (reg2hw.key_share0[10].q ),
+ .q (reg2hw.key_share0[10].q),
.qs ()
);
@@ -1249,7 +1249,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[11].qe),
- .q (reg2hw.key_share0[11].q ),
+ .q (reg2hw.key_share0[11].q),
.qs ()
);
@@ -1265,7 +1265,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[12].qe),
- .q (reg2hw.key_share0[12].q ),
+ .q (reg2hw.key_share0[12].q),
.qs ()
);
@@ -1281,7 +1281,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[13].qe),
- .q (reg2hw.key_share0[13].q ),
+ .q (reg2hw.key_share0[13].q),
.qs ()
);
@@ -1297,7 +1297,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[14].qe),
- .q (reg2hw.key_share0[14].q ),
+ .q (reg2hw.key_share0[14].q),
.qs ()
);
@@ -1313,7 +1313,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share0[15].qe),
- .q (reg2hw.key_share0[15].q ),
+ .q (reg2hw.key_share0[15].q),
.qs ()
);
@@ -1331,7 +1331,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[0].qe),
- .q (reg2hw.key_share1[0].q ),
+ .q (reg2hw.key_share1[0].q),
.qs ()
);
@@ -1347,7 +1347,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[1].qe),
- .q (reg2hw.key_share1[1].q ),
+ .q (reg2hw.key_share1[1].q),
.qs ()
);
@@ -1363,7 +1363,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[2].qe),
- .q (reg2hw.key_share1[2].q ),
+ .q (reg2hw.key_share1[2].q),
.qs ()
);
@@ -1379,7 +1379,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[3].qe),
- .q (reg2hw.key_share1[3].q ),
+ .q (reg2hw.key_share1[3].q),
.qs ()
);
@@ -1395,7 +1395,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[4].qe),
- .q (reg2hw.key_share1[4].q ),
+ .q (reg2hw.key_share1[4].q),
.qs ()
);
@@ -1411,7 +1411,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[5].qe),
- .q (reg2hw.key_share1[5].q ),
+ .q (reg2hw.key_share1[5].q),
.qs ()
);
@@ -1427,7 +1427,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[6].qe),
- .q (reg2hw.key_share1[6].q ),
+ .q (reg2hw.key_share1[6].q),
.qs ()
);
@@ -1443,7 +1443,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[7].qe),
- .q (reg2hw.key_share1[7].q ),
+ .q (reg2hw.key_share1[7].q),
.qs ()
);
@@ -1459,7 +1459,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[8].qe),
- .q (reg2hw.key_share1[8].q ),
+ .q (reg2hw.key_share1[8].q),
.qs ()
);
@@ -1475,7 +1475,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[9].qe),
- .q (reg2hw.key_share1[9].q ),
+ .q (reg2hw.key_share1[9].q),
.qs ()
);
@@ -1491,7 +1491,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[10].qe),
- .q (reg2hw.key_share1[10].q ),
+ .q (reg2hw.key_share1[10].q),
.qs ()
);
@@ -1507,7 +1507,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[11].qe),
- .q (reg2hw.key_share1[11].q ),
+ .q (reg2hw.key_share1[11].q),
.qs ()
);
@@ -1523,7 +1523,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[12].qe),
- .q (reg2hw.key_share1[12].q ),
+ .q (reg2hw.key_share1[12].q),
.qs ()
);
@@ -1539,7 +1539,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[13].qe),
- .q (reg2hw.key_share1[13].q ),
+ .q (reg2hw.key_share1[13].q),
.qs ()
);
@@ -1555,7 +1555,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[14].qe),
- .q (reg2hw.key_share1[14].q ),
+ .q (reg2hw.key_share1[14].q),
.qs ()
);
@@ -1571,7 +1571,7 @@
.d ('0),
.qre (),
.qe (reg2hw.key_share1[15].qe),
- .q (reg2hw.key_share1[15].q ),
+ .q (reg2hw.key_share1[15].q),
.qs ()
);
@@ -1583,21 +1583,22 @@
.SWACCESS("WO"),
.RESVAL (3'h0)
) u_key_len (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_len_we & cfg_regwen_qs),
.wd (key_len_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_len.q ),
+ .q (reg2hw.key_len.q),
+ // to register interface (read)
.qs ()
);
@@ -1611,8 +1612,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_0_we),
@@ -1620,11 +1621,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[0].q ),
+ .q (reg2hw.prefix[0].q),
// to register interface (read)
.qs (prefix_0_qs)
@@ -1638,8 +1639,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_1_we),
@@ -1647,11 +1648,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[1].q ),
+ .q (reg2hw.prefix[1].q),
// to register interface (read)
.qs (prefix_1_qs)
@@ -1665,8 +1666,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_2_we),
@@ -1674,11 +1675,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[2].q ),
+ .q (reg2hw.prefix[2].q),
// to register interface (read)
.qs (prefix_2_qs)
@@ -1692,8 +1693,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_3_we),
@@ -1701,11 +1702,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[3].q ),
+ .q (reg2hw.prefix[3].q),
// to register interface (read)
.qs (prefix_3_qs)
@@ -1719,8 +1720,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_4_we),
@@ -1728,11 +1729,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[4].q ),
+ .q (reg2hw.prefix[4].q),
// to register interface (read)
.qs (prefix_4_qs)
@@ -1746,8 +1747,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_5_we),
@@ -1755,11 +1756,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[5].q ),
+ .q (reg2hw.prefix[5].q),
// to register interface (read)
.qs (prefix_5_qs)
@@ -1773,8 +1774,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_6_we),
@@ -1782,11 +1783,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[6].q ),
+ .q (reg2hw.prefix[6].q),
// to register interface (read)
.qs (prefix_6_qs)
@@ -1800,8 +1801,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_7_we),
@@ -1809,11 +1810,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[7].q ),
+ .q (reg2hw.prefix[7].q),
// to register interface (read)
.qs (prefix_7_qs)
@@ -1827,8 +1828,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_8_we),
@@ -1836,11 +1837,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[8].q ),
+ .q (reg2hw.prefix[8].q),
// to register interface (read)
.qs (prefix_8_qs)
@@ -1854,8 +1855,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_9_we),
@@ -1863,11 +1864,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[9].q ),
+ .q (reg2hw.prefix[9].q),
// to register interface (read)
.qs (prefix_9_qs)
@@ -1881,8 +1882,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prefix_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prefix_10_we),
@@ -1890,11 +1891,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prefix[10].q ),
+ .q (reg2hw.prefix[10].q),
// to register interface (read)
.qs (prefix_10_qs)
@@ -1908,15 +1909,16 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_err_code (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_code.de),
- .d (hw2reg.err_code.d ),
+ .d (hw2reg.err_code.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv
index bd344e2..7e9f4df 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv
@@ -194,7 +194,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_prog_error.qe),
- .q (reg2hw.alert_test.fatal_prog_error.q ),
+ .q (reg2hw.alert_test.fatal_prog_error.q),
.qs ()
);
@@ -209,7 +209,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_state_error.qe),
- .q (reg2hw.alert_test.fatal_state_error.q ),
+ .q (reg2hw.alert_test.fatal_state_error.q),
.qs ()
);
@@ -362,7 +362,7 @@
.d (hw2reg.claim_transition_if.d),
.qre (),
.qe (reg2hw.claim_transition_if.qe),
- .q (reg2hw.claim_transition_if.q ),
+ .q (reg2hw.claim_transition_if.q),
.qs (claim_transition_if_qs)
);
@@ -389,13 +389,12 @@
.DW (1)
) u_transition_cmd (
.re (1'b0),
- // qualified with register enable
.we (transition_cmd_we & transition_regwen_qs),
.wd (transition_cmd_wd),
.d ('0),
.qre (),
.qe (reg2hw.transition_cmd.qe),
- .q (reg2hw.transition_cmd.q ),
+ .q (reg2hw.transition_cmd.q),
.qs ()
);
@@ -408,13 +407,12 @@
.DW (32)
) u_transition_token_0 (
.re (transition_token_0_re),
- // qualified with register enable
.we (transition_token_0_we & transition_regwen_qs),
.wd (transition_token_0_wd),
.d (hw2reg.transition_token[0].d),
.qre (),
.qe (reg2hw.transition_token[0].qe),
- .q (reg2hw.transition_token[0].q ),
+ .q (reg2hw.transition_token[0].q),
.qs (transition_token_0_qs)
);
@@ -425,13 +423,12 @@
.DW (32)
) u_transition_token_1 (
.re (transition_token_1_re),
- // qualified with register enable
.we (transition_token_1_we & transition_regwen_qs),
.wd (transition_token_1_wd),
.d (hw2reg.transition_token[1].d),
.qre (),
.qe (reg2hw.transition_token[1].qe),
- .q (reg2hw.transition_token[1].q ),
+ .q (reg2hw.transition_token[1].q),
.qs (transition_token_1_qs)
);
@@ -442,13 +439,12 @@
.DW (32)
) u_transition_token_2 (
.re (transition_token_2_re),
- // qualified with register enable
.we (transition_token_2_we & transition_regwen_qs),
.wd (transition_token_2_wd),
.d (hw2reg.transition_token[2].d),
.qre (),
.qe (reg2hw.transition_token[2].qe),
- .q (reg2hw.transition_token[2].q ),
+ .q (reg2hw.transition_token[2].q),
.qs (transition_token_2_qs)
);
@@ -459,13 +455,12 @@
.DW (32)
) u_transition_token_3 (
.re (transition_token_3_re),
- // qualified with register enable
.we (transition_token_3_we & transition_regwen_qs),
.wd (transition_token_3_wd),
.d (hw2reg.transition_token[3].d),
.qre (),
.qe (reg2hw.transition_token[3].qe),
- .q (reg2hw.transition_token[3].q ),
+ .q (reg2hw.transition_token[3].q),
.qs (transition_token_3_qs)
);
@@ -476,13 +471,12 @@
.DW (4)
) u_transition_target (
.re (transition_target_re),
- // qualified with register enable
.we (transition_target_we & transition_regwen_qs),
.wd (transition_target_wd),
.d (hw2reg.transition_target.d),
.qre (),
.qe (reg2hw.transition_target.qe),
- .q (reg2hw.transition_target.q ),
+ .q (reg2hw.transition_target.q),
.qs (transition_target_qs)
);
@@ -493,13 +487,12 @@
.DW (8)
) u_otp_test_ctrl (
.re (otp_test_ctrl_re),
- // qualified with register enable
.we (otp_test_ctrl_we & transition_regwen_qs),
.wd (otp_test_ctrl_wd),
.d (hw2reg.otp_test_ctrl.d),
.qre (),
.qe (reg2hw.otp_test_ctrl.qe),
- .q (reg2hw.otp_test_ctrl.q ),
+ .q (reg2hw.otp_test_ctrl.q),
.qs (otp_test_ctrl_qs)
);
diff --git a/hw/ip/nmi_gen/rtl/nmi_gen_reg_top.sv b/hw/ip/nmi_gen/rtl/nmi_gen_reg_top.sv
index 5b84733..d22e43e 100644
--- a/hw/ip/nmi_gen/rtl/nmi_gen_reg_top.sv
+++ b/hw/ip/nmi_gen/rtl/nmi_gen_reg_top.sv
@@ -138,8 +138,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_esc0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_esc0_we),
@@ -147,11 +147,11 @@
// from internal hardware
.de (hw2reg.intr_state.esc0.de),
- .d (hw2reg.intr_state.esc0.d ),
+ .d (hw2reg.intr_state.esc0.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.esc0.q ),
+ .q (reg2hw.intr_state.esc0.q),
// to register interface (read)
.qs (intr_state_esc0_qs)
@@ -164,8 +164,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_esc1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_esc1_we),
@@ -173,11 +173,11 @@
// from internal hardware
.de (hw2reg.intr_state.esc1.de),
- .d (hw2reg.intr_state.esc1.d ),
+ .d (hw2reg.intr_state.esc1.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.esc1.q ),
+ .q (reg2hw.intr_state.esc1.q),
// to register interface (read)
.qs (intr_state_esc1_qs)
@@ -190,8 +190,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_esc2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_esc2_we),
@@ -199,11 +199,11 @@
// from internal hardware
.de (hw2reg.intr_state.esc2.de),
- .d (hw2reg.intr_state.esc2.d ),
+ .d (hw2reg.intr_state.esc2.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.esc2.q ),
+ .q (reg2hw.intr_state.esc2.q),
// to register interface (read)
.qs (intr_state_esc2_qs)
@@ -218,8 +218,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_esc0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_esc0_we),
@@ -227,11 +227,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.esc0.q ),
+ .q (reg2hw.intr_enable.esc0.q),
// to register interface (read)
.qs (intr_enable_esc0_qs)
@@ -244,8 +244,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_esc1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_esc1_we),
@@ -253,11 +253,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.esc1.q ),
+ .q (reg2hw.intr_enable.esc1.q),
// to register interface (read)
.qs (intr_enable_esc1_qs)
@@ -270,8 +270,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_esc2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_esc2_we),
@@ -279,11 +279,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.esc2.q ),
+ .q (reg2hw.intr_enable.esc2.q),
// to register interface (read)
.qs (intr_enable_esc2_qs)
@@ -302,7 +302,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.esc0.qe),
- .q (reg2hw.intr_test.esc0.q ),
+ .q (reg2hw.intr_test.esc0.q),
.qs ()
);
@@ -317,7 +317,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.esc1.qe),
- .q (reg2hw.intr_test.esc1.q ),
+ .q (reg2hw.intr_test.esc1.q),
.qs ()
);
@@ -332,7 +332,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.esc2.qe),
- .q (reg2hw.intr_test.esc2.q ),
+ .q (reg2hw.intr_test.esc2.q),
.qs ()
);
diff --git a/hw/ip/otbn/rtl/otbn_reg_top.sv b/hw/ip/otbn/rtl/otbn_reg_top.sv
index aefb4a4..cf68677 100644
--- a/hw/ip/otbn/rtl/otbn_reg_top.sv
+++ b/hw/ip/otbn/rtl/otbn_reg_top.sv
@@ -197,8 +197,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
@@ -206,11 +206,11 @@
// from internal hardware
.de (hw2reg.intr_state.de),
- .d (hw2reg.intr_state.d ),
+ .d (hw2reg.intr_state.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.q ),
+ .q (reg2hw.intr_state.q),
// to register interface (read)
.qs (intr_state_qs)
@@ -224,8 +224,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
@@ -233,11 +233,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.q ),
+ .q (reg2hw.intr_enable.q),
// to register interface (read)
.qs (intr_enable_qs)
@@ -255,7 +255,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.qe),
- .q (reg2hw.intr_test.q ),
+ .q (reg2hw.intr_test.q),
.qs ()
);
@@ -272,7 +272,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal.qe),
- .q (reg2hw.alert_test.fatal.q ),
+ .q (reg2hw.alert_test.fatal.q),
.qs ()
);
@@ -287,7 +287,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov.qe),
- .q (reg2hw.alert_test.recov.q ),
+ .q (reg2hw.alert_test.recov.q),
.qs ()
);
@@ -303,7 +303,7 @@
.d ('0),
.qre (),
.qe (reg2hw.cmd.qe),
- .q (reg2hw.cmd.q ),
+ .q (reg2hw.cmd.q),
.qs ()
);
@@ -332,15 +332,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_bits_bad_data_addr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_bits.bad_data_addr.de),
- .d (hw2reg.err_bits.bad_data_addr.d ),
+ .d (hw2reg.err_bits.bad_data_addr.d),
// to internal hardware
.qe (),
@@ -357,15 +358,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_bits_bad_insn_addr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_bits.bad_insn_addr.de),
- .d (hw2reg.err_bits.bad_insn_addr.d ),
+ .d (hw2reg.err_bits.bad_insn_addr.d),
// to internal hardware
.qe (),
@@ -382,15 +384,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_bits_call_stack (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_bits.call_stack.de),
- .d (hw2reg.err_bits.call_stack.d ),
+ .d (hw2reg.err_bits.call_stack.d),
// to internal hardware
.qe (),
@@ -407,15 +410,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_bits_illegal_insn (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_bits.illegal_insn.de),
- .d (hw2reg.err_bits.illegal_insn.d ),
+ .d (hw2reg.err_bits.illegal_insn.d),
// to internal hardware
.qe (),
@@ -432,15 +436,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_bits_loop (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_bits.loop.de),
- .d (hw2reg.err_bits.loop.d ),
+ .d (hw2reg.err_bits.loop.d),
// to internal hardware
.qe (),
@@ -457,15 +462,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_bits_fatal_imem (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_bits.fatal_imem.de),
- .d (hw2reg.err_bits.fatal_imem.d ),
+ .d (hw2reg.err_bits.fatal_imem.d),
// to internal hardware
.qe (),
@@ -482,15 +488,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_bits_fatal_dmem (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_bits.fatal_dmem.de),
- .d (hw2reg.err_bits.fatal_dmem.d ),
+ .d (hw2reg.err_bits.fatal_dmem.d),
// to internal hardware
.qe (),
@@ -507,15 +514,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_bits_fatal_reg (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_bits.fatal_reg.de),
- .d (hw2reg.err_bits.fatal_reg.d ),
+ .d (hw2reg.err_bits.fatal_reg.d),
// to internal hardware
.qe (),
@@ -533,8 +541,8 @@
.SWACCESS("WO"),
.RESVAL (32'h0)
) u_start_addr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (start_addr_we),
@@ -542,12 +550,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.start_addr.q ),
+ .q (reg2hw.start_addr.q),
+ // to register interface (read)
.qs ()
);
@@ -560,15 +569,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_fatal_alert_cause_bus_integrity_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.fatal_alert_cause.bus_integrity_error.de),
- .d (hw2reg.fatal_alert_cause.bus_integrity_error.d ),
+ .d (hw2reg.fatal_alert_cause.bus_integrity_error.d),
// to internal hardware
.qe (),
@@ -585,15 +595,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_fatal_alert_cause_imem_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.fatal_alert_cause.imem_error.de),
- .d (hw2reg.fatal_alert_cause.imem_error.d ),
+ .d (hw2reg.fatal_alert_cause.imem_error.d),
// to internal hardware
.qe (),
@@ -610,15 +621,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_fatal_alert_cause_dmem_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.fatal_alert_cause.dmem_error.de),
- .d (hw2reg.fatal_alert_cause.dmem_error.d ),
+ .d (hw2reg.fatal_alert_cause.dmem_error.d),
// to internal hardware
.qe (),
@@ -635,15 +647,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_fatal_alert_cause_reg_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.fatal_alert_cause.reg_error.de),
- .d (hw2reg.fatal_alert_cause.reg_error.d ),
+ .d (hw2reg.fatal_alert_cause.reg_error.d),
// to internal hardware
.qe (),
@@ -661,15 +674,16 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_insn_cnt (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.insn_cnt.de),
- .d (hw2reg.insn_cnt.d ),
+ .d (hw2reg.insn_cnt.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
index adbbbf7..ced8589 100644
--- a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
+++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
@@ -305,8 +305,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_otp_operation_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_otp_operation_done_we),
@@ -314,11 +314,11 @@
// from internal hardware
.de (hw2reg.intr_state.otp_operation_done.de),
- .d (hw2reg.intr_state.otp_operation_done.d ),
+ .d (hw2reg.intr_state.otp_operation_done.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.otp_operation_done.q ),
+ .q (reg2hw.intr_state.otp_operation_done.q),
// to register interface (read)
.qs (intr_state_otp_operation_done_qs)
@@ -331,8 +331,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_otp_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_otp_error_we),
@@ -340,11 +340,11 @@
// from internal hardware
.de (hw2reg.intr_state.otp_error.de),
- .d (hw2reg.intr_state.otp_error.d ),
+ .d (hw2reg.intr_state.otp_error.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.otp_error.q ),
+ .q (reg2hw.intr_state.otp_error.q),
// to register interface (read)
.qs (intr_state_otp_error_qs)
@@ -359,8 +359,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_otp_operation_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_otp_operation_done_we),
@@ -368,11 +368,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.otp_operation_done.q ),
+ .q (reg2hw.intr_enable.otp_operation_done.q),
// to register interface (read)
.qs (intr_enable_otp_operation_done_qs)
@@ -385,8 +385,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_otp_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_otp_error_we),
@@ -394,11 +394,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.otp_error.q ),
+ .q (reg2hw.intr_enable.otp_error.q),
// to register interface (read)
.qs (intr_enable_otp_error_qs)
@@ -417,7 +417,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.otp_operation_done.qe),
- .q (reg2hw.intr_test.otp_operation_done.q ),
+ .q (reg2hw.intr_test.otp_operation_done.q),
.qs ()
);
@@ -432,7 +432,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.otp_error.qe),
- .q (reg2hw.intr_test.otp_error.q ),
+ .q (reg2hw.intr_test.otp_error.q),
.qs ()
);
@@ -449,7 +449,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_macro_error.qe),
- .q (reg2hw.alert_test.fatal_macro_error.q ),
+ .q (reg2hw.alert_test.fatal_macro_error.q),
.qs ()
);
@@ -464,7 +464,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_check_error.qe),
- .q (reg2hw.alert_test.fatal_check_error.q ),
+ .q (reg2hw.alert_test.fatal_check_error.q),
.qs ()
);
@@ -859,13 +859,12 @@
.DW (1)
) u_direct_access_cmd_rd (
.re (1'b0),
- // qualified with register enable
.we (direct_access_cmd_rd_we & direct_access_regwen_qs),
.wd (direct_access_cmd_rd_wd),
.d ('0),
.qre (),
.qe (reg2hw.direct_access_cmd.rd.qe),
- .q (reg2hw.direct_access_cmd.rd.q ),
+ .q (reg2hw.direct_access_cmd.rd.q),
.qs ()
);
@@ -875,13 +874,12 @@
.DW (1)
) u_direct_access_cmd_wr (
.re (1'b0),
- // qualified with register enable
.we (direct_access_cmd_wr_we & direct_access_regwen_qs),
.wd (direct_access_cmd_wr_wd),
.d ('0),
.qre (),
.qe (reg2hw.direct_access_cmd.wr.qe),
- .q (reg2hw.direct_access_cmd.wr.q ),
+ .q (reg2hw.direct_access_cmd.wr.q),
.qs ()
);
@@ -891,13 +889,12 @@
.DW (1)
) u_direct_access_cmd_digest (
.re (1'b0),
- // qualified with register enable
.we (direct_access_cmd_digest_we & direct_access_regwen_qs),
.wd (direct_access_cmd_digest_wd),
.d ('0),
.qre (),
.qe (reg2hw.direct_access_cmd.digest.qe),
- .q (reg2hw.direct_access_cmd.digest.q ),
+ .q (reg2hw.direct_access_cmd.digest.q),
.qs ()
);
@@ -909,20 +906,20 @@
.SWACCESS("RW"),
.RESVAL (11'h0)
) u_direct_access_address (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (direct_access_address_we & direct_access_regwen_qs),
.wd (direct_access_address_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.direct_access_address.q ),
+ .q (reg2hw.direct_access_address.q),
// to register interface (read)
.qs (direct_access_address_qs)
@@ -938,20 +935,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_direct_access_wdata_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (direct_access_wdata_0_we & direct_access_regwen_qs),
.wd (direct_access_wdata_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.direct_access_wdata[0].q ),
+ .q (reg2hw.direct_access_wdata[0].q),
// to register interface (read)
.qs (direct_access_wdata_0_qs)
@@ -965,20 +962,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_direct_access_wdata_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (direct_access_wdata_1_we & direct_access_regwen_qs),
.wd (direct_access_wdata_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.direct_access_wdata[1].q ),
+ .q (reg2hw.direct_access_wdata[1].q),
// to register interface (read)
.qs (direct_access_wdata_1_qs)
@@ -1026,8 +1023,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_check_trigger_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (check_trigger_regwen_we),
@@ -1035,7 +1032,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1053,13 +1050,12 @@
.DW (1)
) u_check_trigger_integrity (
.re (1'b0),
- // qualified with register enable
.we (check_trigger_integrity_we & check_trigger_regwen_qs),
.wd (check_trigger_integrity_wd),
.d ('0),
.qre (),
.qe (reg2hw.check_trigger.integrity.qe),
- .q (reg2hw.check_trigger.integrity.q ),
+ .q (reg2hw.check_trigger.integrity.q),
.qs ()
);
@@ -1069,13 +1065,12 @@
.DW (1)
) u_check_trigger_consistency (
.re (1'b0),
- // qualified with register enable
.we (check_trigger_consistency_we & check_trigger_regwen_qs),
.wd (check_trigger_consistency_wd),
.d ('0),
.qre (),
.qe (reg2hw.check_trigger.consistency.qe),
- .q (reg2hw.check_trigger.consistency.q ),
+ .q (reg2hw.check_trigger.consistency.q),
.qs ()
);
@@ -1087,8 +1082,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_check_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (check_regwen_we),
@@ -1096,7 +1091,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1114,20 +1109,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_check_timeout (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (check_timeout_we & check_regwen_qs),
.wd (check_timeout_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.check_timeout.q ),
+ .q (reg2hw.check_timeout.q),
// to register interface (read)
.qs (check_timeout_qs)
@@ -1141,20 +1136,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_integrity_check_period (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (integrity_check_period_we & check_regwen_qs),
.wd (integrity_check_period_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.integrity_check_period.q ),
+ .q (reg2hw.integrity_check_period.q),
// to register interface (read)
.qs (integrity_check_period_qs)
@@ -1168,20 +1163,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_consistency_check_period (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (consistency_check_period_we & check_regwen_qs),
.wd (consistency_check_period_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.consistency_check_period.q ),
+ .q (reg2hw.consistency_check_period.q),
// to register interface (read)
.qs (consistency_check_period_qs)
@@ -1195,20 +1190,20 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_creator_sw_cfg_read_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (creator_sw_cfg_read_lock_we & direct_access_regwen_qs),
.wd (creator_sw_cfg_read_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.creator_sw_cfg_read_lock.q ),
+ .q (reg2hw.creator_sw_cfg_read_lock.q),
// to register interface (read)
.qs (creator_sw_cfg_read_lock_qs)
@@ -1222,20 +1217,20 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_owner_sw_cfg_read_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (owner_sw_cfg_read_lock_we & direct_access_regwen_qs),
.wd (owner_sw_cfg_read_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.owner_sw_cfg_read_lock.q ),
+ .q (reg2hw.owner_sw_cfg_read_lock.q),
// to register interface (read)
.qs (owner_sw_cfg_read_lock_qs)
diff --git a/hw/ip/pattgen/rtl/pattgen_reg_top.sv b/hw/ip/pattgen/rtl/pattgen_reg_top.sv
index 83099cd..2b449fe 100644
--- a/hw/ip/pattgen/rtl/pattgen_reg_top.sv
+++ b/hw/ip/pattgen/rtl/pattgen_reg_top.sv
@@ -172,8 +172,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_done_ch0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_done_ch0_we),
@@ -181,11 +181,11 @@
// from internal hardware
.de (hw2reg.intr_state.done_ch0.de),
- .d (hw2reg.intr_state.done_ch0.d ),
+ .d (hw2reg.intr_state.done_ch0.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.done_ch0.q ),
+ .q (reg2hw.intr_state.done_ch0.q),
// to register interface (read)
.qs (intr_state_done_ch0_qs)
@@ -198,8 +198,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_done_ch1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_done_ch1_we),
@@ -207,11 +207,11 @@
// from internal hardware
.de (hw2reg.intr_state.done_ch1.de),
- .d (hw2reg.intr_state.done_ch1.d ),
+ .d (hw2reg.intr_state.done_ch1.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.done_ch1.q ),
+ .q (reg2hw.intr_state.done_ch1.q),
// to register interface (read)
.qs (intr_state_done_ch1_qs)
@@ -226,8 +226,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_done_ch0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_done_ch0_we),
@@ -235,11 +235,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.done_ch0.q ),
+ .q (reg2hw.intr_enable.done_ch0.q),
// to register interface (read)
.qs (intr_enable_done_ch0_qs)
@@ -252,8 +252,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_done_ch1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_done_ch1_we),
@@ -261,11 +261,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.done_ch1.q ),
+ .q (reg2hw.intr_enable.done_ch1.q),
// to register interface (read)
.qs (intr_enable_done_ch1_qs)
@@ -284,7 +284,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.done_ch0.qe),
- .q (reg2hw.intr_test.done_ch0.q ),
+ .q (reg2hw.intr_test.done_ch0.q),
.qs ()
);
@@ -299,7 +299,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.done_ch1.qe),
- .q (reg2hw.intr_test.done_ch1.q ),
+ .q (reg2hw.intr_test.done_ch1.q),
.qs ()
);
@@ -312,8 +312,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_enable_ch0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_enable_ch0_we),
@@ -321,11 +321,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.enable_ch0.q ),
+ .q (reg2hw.ctrl.enable_ch0.q),
// to register interface (read)
.qs (ctrl_enable_ch0_qs)
@@ -338,8 +338,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_enable_ch1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_enable_ch1_we),
@@ -347,11 +347,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.enable_ch1.q ),
+ .q (reg2hw.ctrl.enable_ch1.q),
// to register interface (read)
.qs (ctrl_enable_ch1_qs)
@@ -364,8 +364,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_polarity_ch0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_polarity_ch0_we),
@@ -373,11 +373,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.polarity_ch0.q ),
+ .q (reg2hw.ctrl.polarity_ch0.q),
// to register interface (read)
.qs (ctrl_polarity_ch0_qs)
@@ -390,8 +390,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_polarity_ch1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_polarity_ch1_we),
@@ -399,11 +399,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.polarity_ch1.q ),
+ .q (reg2hw.ctrl.polarity_ch1.q),
// to register interface (read)
.qs (ctrl_polarity_ch1_qs)
@@ -417,8 +417,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prediv_ch0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prediv_ch0_we),
@@ -426,11 +426,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prediv_ch0.q ),
+ .q (reg2hw.prediv_ch0.q),
// to register interface (read)
.qs (prediv_ch0_qs)
@@ -444,8 +444,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_prediv_ch1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prediv_ch1_we),
@@ -453,11 +453,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prediv_ch1.q ),
+ .q (reg2hw.prediv_ch1.q),
// to register interface (read)
.qs (prediv_ch1_qs)
@@ -473,8 +473,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_data_ch0_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_ch0_0_we),
@@ -482,11 +482,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.data_ch0[0].q ),
+ .q (reg2hw.data_ch0[0].q),
// to register interface (read)
.qs (data_ch0_0_qs)
@@ -500,8 +500,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_data_ch0_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_ch0_1_we),
@@ -509,11 +509,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.data_ch0[1].q ),
+ .q (reg2hw.data_ch0[1].q),
// to register interface (read)
.qs (data_ch0_1_qs)
@@ -529,8 +529,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_data_ch1_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_ch1_0_we),
@@ -538,11 +538,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.data_ch1[0].q ),
+ .q (reg2hw.data_ch1[0].q),
// to register interface (read)
.qs (data_ch1_0_qs)
@@ -556,8 +556,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_data_ch1_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_ch1_1_we),
@@ -565,11 +565,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.data_ch1[1].q ),
+ .q (reg2hw.data_ch1[1].q),
// to register interface (read)
.qs (data_ch1_1_qs)
@@ -584,8 +584,8 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_size_len_ch0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (size_len_ch0_we),
@@ -593,11 +593,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.size.len_ch0.q ),
+ .q (reg2hw.size.len_ch0.q),
// to register interface (read)
.qs (size_len_ch0_qs)
@@ -610,8 +610,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_size_reps_ch0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (size_reps_ch0_we),
@@ -619,11 +619,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.size.reps_ch0.q ),
+ .q (reg2hw.size.reps_ch0.q),
// to register interface (read)
.qs (size_reps_ch0_qs)
@@ -636,8 +636,8 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_size_len_ch1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (size_len_ch1_we),
@@ -645,11 +645,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.size.len_ch1.q ),
+ .q (reg2hw.size.len_ch1.q),
// to register interface (read)
.qs (size_len_ch1_qs)
@@ -662,8 +662,8 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_size_reps_ch1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (size_reps_ch1_we),
@@ -671,11 +671,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.size.reps_ch1.q ),
+ .q (reg2hw.size.reps_ch1.q),
// to register interface (read)
.qs (size_reps_ch1_qs)
diff --git a/hw/ip/pinmux/rtl/pinmux_reg_top.sv b/hw/ip/pinmux/rtl/pinmux_reg_top.sv
index 7b6205a..4fb1823 100644
--- a/hw/ip/pinmux/rtl/pinmux_reg_top.sv
+++ b/hw/ip/pinmux/rtl/pinmux_reg_top.sv
@@ -1617,8 +1617,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_0_we),
@@ -1626,7 +1626,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1644,8 +1644,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_1_we),
@@ -1653,7 +1653,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1671,8 +1671,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_2_we),
@@ -1680,7 +1680,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1698,8 +1698,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_3_we),
@@ -1707,7 +1707,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1725,8 +1725,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_4_we),
@@ -1734,7 +1734,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1752,8 +1752,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_5_we),
@@ -1761,7 +1761,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1779,8 +1779,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_6_we),
@@ -1788,7 +1788,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1806,8 +1806,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_7_we),
@@ -1815,7 +1815,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1833,8 +1833,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_8_we),
@@ -1842,7 +1842,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1860,8 +1860,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_9_we),
@@ -1869,7 +1869,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1887,8 +1887,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_10_we),
@@ -1896,7 +1896,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1914,8 +1914,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_11_we),
@@ -1923,7 +1923,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1941,8 +1941,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_12_we),
@@ -1950,7 +1950,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1968,8 +1968,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_13_we),
@@ -1977,7 +1977,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1995,8 +1995,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_14_we),
@@ -2004,7 +2004,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2022,8 +2022,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_15_we),
@@ -2031,7 +2031,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2049,8 +2049,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_16_we),
@@ -2058,7 +2058,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2076,8 +2076,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_17_we),
@@ -2085,7 +2085,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2103,8 +2103,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_18_we),
@@ -2112,7 +2112,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2130,8 +2130,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_19_we),
@@ -2139,7 +2139,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2157,8 +2157,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_20_we),
@@ -2166,7 +2166,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2184,8 +2184,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_21_we),
@@ -2193,7 +2193,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2211,8 +2211,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_22_we),
@@ -2220,7 +2220,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2238,8 +2238,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_23_we),
@@ -2247,7 +2247,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2265,8 +2265,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_24_we),
@@ -2274,7 +2274,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2292,8 +2292,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_25_we),
@@ -2301,7 +2301,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2319,8 +2319,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_26_we),
@@ -2328,7 +2328,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2346,8 +2346,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_27_we),
@@ -2355,7 +2355,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2373,8 +2373,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_28_we),
@@ -2382,7 +2382,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2400,8 +2400,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_29_we),
@@ -2409,7 +2409,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2427,8 +2427,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_30_we),
@@ -2436,7 +2436,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2454,8 +2454,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_31_we),
@@ -2463,7 +2463,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2481,8 +2481,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_32_we),
@@ -2490,7 +2490,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2510,20 +2510,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs),
.wd (mio_periph_insel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[0].q ),
+ .q (reg2hw.mio_periph_insel[0].q),
// to register interface (read)
.qs (mio_periph_insel_0_qs)
@@ -2537,20 +2537,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs),
.wd (mio_periph_insel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[1].q ),
+ .q (reg2hw.mio_periph_insel[1].q),
// to register interface (read)
.qs (mio_periph_insel_1_qs)
@@ -2564,20 +2564,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs),
.wd (mio_periph_insel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[2].q ),
+ .q (reg2hw.mio_periph_insel[2].q),
// to register interface (read)
.qs (mio_periph_insel_2_qs)
@@ -2591,20 +2591,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs),
.wd (mio_periph_insel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[3].q ),
+ .q (reg2hw.mio_periph_insel[3].q),
// to register interface (read)
.qs (mio_periph_insel_3_qs)
@@ -2618,20 +2618,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_4_we & mio_periph_insel_regwen_4_qs),
.wd (mio_periph_insel_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[4].q ),
+ .q (reg2hw.mio_periph_insel[4].q),
// to register interface (read)
.qs (mio_periph_insel_4_qs)
@@ -2645,20 +2645,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_5_we & mio_periph_insel_regwen_5_qs),
.wd (mio_periph_insel_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[5].q ),
+ .q (reg2hw.mio_periph_insel[5].q),
// to register interface (read)
.qs (mio_periph_insel_5_qs)
@@ -2672,20 +2672,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_6_we & mio_periph_insel_regwen_6_qs),
.wd (mio_periph_insel_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[6].q ),
+ .q (reg2hw.mio_periph_insel[6].q),
// to register interface (read)
.qs (mio_periph_insel_6_qs)
@@ -2699,20 +2699,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_7_we & mio_periph_insel_regwen_7_qs),
.wd (mio_periph_insel_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[7].q ),
+ .q (reg2hw.mio_periph_insel[7].q),
// to register interface (read)
.qs (mio_periph_insel_7_qs)
@@ -2726,20 +2726,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_8_we & mio_periph_insel_regwen_8_qs),
.wd (mio_periph_insel_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[8].q ),
+ .q (reg2hw.mio_periph_insel[8].q),
// to register interface (read)
.qs (mio_periph_insel_8_qs)
@@ -2753,20 +2753,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_9_we & mio_periph_insel_regwen_9_qs),
.wd (mio_periph_insel_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[9].q ),
+ .q (reg2hw.mio_periph_insel[9].q),
// to register interface (read)
.qs (mio_periph_insel_9_qs)
@@ -2780,20 +2780,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_10_we & mio_periph_insel_regwen_10_qs),
.wd (mio_periph_insel_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[10].q ),
+ .q (reg2hw.mio_periph_insel[10].q),
// to register interface (read)
.qs (mio_periph_insel_10_qs)
@@ -2807,20 +2807,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_11_we & mio_periph_insel_regwen_11_qs),
.wd (mio_periph_insel_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[11].q ),
+ .q (reg2hw.mio_periph_insel[11].q),
// to register interface (read)
.qs (mio_periph_insel_11_qs)
@@ -2834,20 +2834,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_12_we & mio_periph_insel_regwen_12_qs),
.wd (mio_periph_insel_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[12].q ),
+ .q (reg2hw.mio_periph_insel[12].q),
// to register interface (read)
.qs (mio_periph_insel_12_qs)
@@ -2861,20 +2861,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_13_we & mio_periph_insel_regwen_13_qs),
.wd (mio_periph_insel_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[13].q ),
+ .q (reg2hw.mio_periph_insel[13].q),
// to register interface (read)
.qs (mio_periph_insel_13_qs)
@@ -2888,20 +2888,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_14_we & mio_periph_insel_regwen_14_qs),
.wd (mio_periph_insel_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[14].q ),
+ .q (reg2hw.mio_periph_insel[14].q),
// to register interface (read)
.qs (mio_periph_insel_14_qs)
@@ -2915,20 +2915,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_15_we & mio_periph_insel_regwen_15_qs),
.wd (mio_periph_insel_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[15].q ),
+ .q (reg2hw.mio_periph_insel[15].q),
// to register interface (read)
.qs (mio_periph_insel_15_qs)
@@ -2942,20 +2942,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_16_we & mio_periph_insel_regwen_16_qs),
.wd (mio_periph_insel_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[16].q ),
+ .q (reg2hw.mio_periph_insel[16].q),
// to register interface (read)
.qs (mio_periph_insel_16_qs)
@@ -2969,20 +2969,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_17_we & mio_periph_insel_regwen_17_qs),
.wd (mio_periph_insel_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[17].q ),
+ .q (reg2hw.mio_periph_insel[17].q),
// to register interface (read)
.qs (mio_periph_insel_17_qs)
@@ -2996,20 +2996,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_18_we & mio_periph_insel_regwen_18_qs),
.wd (mio_periph_insel_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[18].q ),
+ .q (reg2hw.mio_periph_insel[18].q),
// to register interface (read)
.qs (mio_periph_insel_18_qs)
@@ -3023,20 +3023,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_19_we & mio_periph_insel_regwen_19_qs),
.wd (mio_periph_insel_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[19].q ),
+ .q (reg2hw.mio_periph_insel[19].q),
// to register interface (read)
.qs (mio_periph_insel_19_qs)
@@ -3050,20 +3050,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_20_we & mio_periph_insel_regwen_20_qs),
.wd (mio_periph_insel_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[20].q ),
+ .q (reg2hw.mio_periph_insel[20].q),
// to register interface (read)
.qs (mio_periph_insel_20_qs)
@@ -3077,20 +3077,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_21_we & mio_periph_insel_regwen_21_qs),
.wd (mio_periph_insel_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[21].q ),
+ .q (reg2hw.mio_periph_insel[21].q),
// to register interface (read)
.qs (mio_periph_insel_21_qs)
@@ -3104,20 +3104,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_22_we & mio_periph_insel_regwen_22_qs),
.wd (mio_periph_insel_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[22].q ),
+ .q (reg2hw.mio_periph_insel[22].q),
// to register interface (read)
.qs (mio_periph_insel_22_qs)
@@ -3131,20 +3131,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_23_we & mio_periph_insel_regwen_23_qs),
.wd (mio_periph_insel_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[23].q ),
+ .q (reg2hw.mio_periph_insel[23].q),
// to register interface (read)
.qs (mio_periph_insel_23_qs)
@@ -3158,20 +3158,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_24_we & mio_periph_insel_regwen_24_qs),
.wd (mio_periph_insel_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[24].q ),
+ .q (reg2hw.mio_periph_insel[24].q),
// to register interface (read)
.qs (mio_periph_insel_24_qs)
@@ -3185,20 +3185,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_25_we & mio_periph_insel_regwen_25_qs),
.wd (mio_periph_insel_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[25].q ),
+ .q (reg2hw.mio_periph_insel[25].q),
// to register interface (read)
.qs (mio_periph_insel_25_qs)
@@ -3212,20 +3212,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_26_we & mio_periph_insel_regwen_26_qs),
.wd (mio_periph_insel_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[26].q ),
+ .q (reg2hw.mio_periph_insel[26].q),
// to register interface (read)
.qs (mio_periph_insel_26_qs)
@@ -3239,20 +3239,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_27_we & mio_periph_insel_regwen_27_qs),
.wd (mio_periph_insel_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[27].q ),
+ .q (reg2hw.mio_periph_insel[27].q),
// to register interface (read)
.qs (mio_periph_insel_27_qs)
@@ -3266,20 +3266,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_28_we & mio_periph_insel_regwen_28_qs),
.wd (mio_periph_insel_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[28].q ),
+ .q (reg2hw.mio_periph_insel[28].q),
// to register interface (read)
.qs (mio_periph_insel_28_qs)
@@ -3293,20 +3293,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_29_we & mio_periph_insel_regwen_29_qs),
.wd (mio_periph_insel_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[29].q ),
+ .q (reg2hw.mio_periph_insel[29].q),
// to register interface (read)
.qs (mio_periph_insel_29_qs)
@@ -3320,20 +3320,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_30_we & mio_periph_insel_regwen_30_qs),
.wd (mio_periph_insel_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[30].q ),
+ .q (reg2hw.mio_periph_insel[30].q),
// to register interface (read)
.qs (mio_periph_insel_30_qs)
@@ -3347,20 +3347,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_31_we & mio_periph_insel_regwen_31_qs),
.wd (mio_periph_insel_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[31].q ),
+ .q (reg2hw.mio_periph_insel[31].q),
// to register interface (read)
.qs (mio_periph_insel_31_qs)
@@ -3374,20 +3374,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_32_we & mio_periph_insel_regwen_32_qs),
.wd (mio_periph_insel_32_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[32].q ),
+ .q (reg2hw.mio_periph_insel[32].q),
// to register interface (read)
.qs (mio_periph_insel_32_qs)
@@ -3403,8 +3403,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_0_we),
@@ -3412,7 +3412,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3430,8 +3430,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_1_we),
@@ -3439,7 +3439,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3457,8 +3457,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_2_we),
@@ -3466,7 +3466,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3484,8 +3484,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_3_we),
@@ -3493,7 +3493,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3511,8 +3511,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_4_we),
@@ -3520,7 +3520,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3538,8 +3538,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_5_we),
@@ -3547,7 +3547,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3565,8 +3565,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_6_we),
@@ -3574,7 +3574,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3592,8 +3592,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_7_we),
@@ -3601,7 +3601,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3619,8 +3619,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_8_we),
@@ -3628,7 +3628,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3646,8 +3646,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_9_we),
@@ -3655,7 +3655,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3673,8 +3673,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_10_we),
@@ -3682,7 +3682,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3700,8 +3700,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_11_we),
@@ -3709,7 +3709,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3727,8 +3727,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_12_we),
@@ -3736,7 +3736,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3754,8 +3754,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_13_we),
@@ -3763,7 +3763,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3781,8 +3781,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_14_we),
@@ -3790,7 +3790,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3808,8 +3808,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_15_we),
@@ -3817,7 +3817,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3835,8 +3835,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_16_we),
@@ -3844,7 +3844,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3862,8 +3862,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_17_we),
@@ -3871,7 +3871,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3889,8 +3889,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_18_we),
@@ -3898,7 +3898,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3916,8 +3916,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_19_we),
@@ -3925,7 +3925,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3943,8 +3943,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_20_we),
@@ -3952,7 +3952,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3970,8 +3970,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_21_we),
@@ -3979,7 +3979,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3997,8 +3997,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_22_we),
@@ -4006,7 +4006,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4024,8 +4024,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_23_we),
@@ -4033,7 +4033,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4051,8 +4051,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_24_we),
@@ -4060,7 +4060,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4078,8 +4078,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_25_we),
@@ -4087,7 +4087,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4105,8 +4105,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_26_we),
@@ -4114,7 +4114,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4132,8 +4132,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_27_we),
@@ -4141,7 +4141,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4159,8 +4159,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_28_we),
@@ -4168,7 +4168,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4186,8 +4186,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_29_we),
@@ -4195,7 +4195,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4213,8 +4213,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_30_we),
@@ -4222,7 +4222,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4240,8 +4240,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_31_we),
@@ -4249,7 +4249,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4269,20 +4269,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_0_we & mio_outsel_regwen_0_qs),
.wd (mio_outsel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[0].q ),
+ .q (reg2hw.mio_outsel[0].q),
// to register interface (read)
.qs (mio_outsel_0_qs)
@@ -4296,20 +4296,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_1_we & mio_outsel_regwen_1_qs),
.wd (mio_outsel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[1].q ),
+ .q (reg2hw.mio_outsel[1].q),
// to register interface (read)
.qs (mio_outsel_1_qs)
@@ -4323,20 +4323,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_2_we & mio_outsel_regwen_2_qs),
.wd (mio_outsel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[2].q ),
+ .q (reg2hw.mio_outsel[2].q),
// to register interface (read)
.qs (mio_outsel_2_qs)
@@ -4350,20 +4350,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_3_we & mio_outsel_regwen_3_qs),
.wd (mio_outsel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[3].q ),
+ .q (reg2hw.mio_outsel[3].q),
// to register interface (read)
.qs (mio_outsel_3_qs)
@@ -4377,20 +4377,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_4_we & mio_outsel_regwen_4_qs),
.wd (mio_outsel_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[4].q ),
+ .q (reg2hw.mio_outsel[4].q),
// to register interface (read)
.qs (mio_outsel_4_qs)
@@ -4404,20 +4404,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_5_we & mio_outsel_regwen_5_qs),
.wd (mio_outsel_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[5].q ),
+ .q (reg2hw.mio_outsel[5].q),
// to register interface (read)
.qs (mio_outsel_5_qs)
@@ -4431,20 +4431,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_6_we & mio_outsel_regwen_6_qs),
.wd (mio_outsel_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[6].q ),
+ .q (reg2hw.mio_outsel[6].q),
// to register interface (read)
.qs (mio_outsel_6_qs)
@@ -4458,20 +4458,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_7_we & mio_outsel_regwen_7_qs),
.wd (mio_outsel_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[7].q ),
+ .q (reg2hw.mio_outsel[7].q),
// to register interface (read)
.qs (mio_outsel_7_qs)
@@ -4485,20 +4485,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_8_we & mio_outsel_regwen_8_qs),
.wd (mio_outsel_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[8].q ),
+ .q (reg2hw.mio_outsel[8].q),
// to register interface (read)
.qs (mio_outsel_8_qs)
@@ -4512,20 +4512,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_9_we & mio_outsel_regwen_9_qs),
.wd (mio_outsel_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[9].q ),
+ .q (reg2hw.mio_outsel[9].q),
// to register interface (read)
.qs (mio_outsel_9_qs)
@@ -4539,20 +4539,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_10_we & mio_outsel_regwen_10_qs),
.wd (mio_outsel_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[10].q ),
+ .q (reg2hw.mio_outsel[10].q),
// to register interface (read)
.qs (mio_outsel_10_qs)
@@ -4566,20 +4566,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_11_we & mio_outsel_regwen_11_qs),
.wd (mio_outsel_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[11].q ),
+ .q (reg2hw.mio_outsel[11].q),
// to register interface (read)
.qs (mio_outsel_11_qs)
@@ -4593,20 +4593,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_12_we & mio_outsel_regwen_12_qs),
.wd (mio_outsel_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[12].q ),
+ .q (reg2hw.mio_outsel[12].q),
// to register interface (read)
.qs (mio_outsel_12_qs)
@@ -4620,20 +4620,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_13_we & mio_outsel_regwen_13_qs),
.wd (mio_outsel_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[13].q ),
+ .q (reg2hw.mio_outsel[13].q),
// to register interface (read)
.qs (mio_outsel_13_qs)
@@ -4647,20 +4647,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_14_we & mio_outsel_regwen_14_qs),
.wd (mio_outsel_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[14].q ),
+ .q (reg2hw.mio_outsel[14].q),
// to register interface (read)
.qs (mio_outsel_14_qs)
@@ -4674,20 +4674,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_15_we & mio_outsel_regwen_15_qs),
.wd (mio_outsel_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[15].q ),
+ .q (reg2hw.mio_outsel[15].q),
// to register interface (read)
.qs (mio_outsel_15_qs)
@@ -4701,20 +4701,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_16_we & mio_outsel_regwen_16_qs),
.wd (mio_outsel_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[16].q ),
+ .q (reg2hw.mio_outsel[16].q),
// to register interface (read)
.qs (mio_outsel_16_qs)
@@ -4728,20 +4728,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_17_we & mio_outsel_regwen_17_qs),
.wd (mio_outsel_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[17].q ),
+ .q (reg2hw.mio_outsel[17].q),
// to register interface (read)
.qs (mio_outsel_17_qs)
@@ -4755,20 +4755,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_18_we & mio_outsel_regwen_18_qs),
.wd (mio_outsel_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[18].q ),
+ .q (reg2hw.mio_outsel[18].q),
// to register interface (read)
.qs (mio_outsel_18_qs)
@@ -4782,20 +4782,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_19_we & mio_outsel_regwen_19_qs),
.wd (mio_outsel_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[19].q ),
+ .q (reg2hw.mio_outsel[19].q),
// to register interface (read)
.qs (mio_outsel_19_qs)
@@ -4809,20 +4809,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_20_we & mio_outsel_regwen_20_qs),
.wd (mio_outsel_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[20].q ),
+ .q (reg2hw.mio_outsel[20].q),
// to register interface (read)
.qs (mio_outsel_20_qs)
@@ -4836,20 +4836,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_21_we & mio_outsel_regwen_21_qs),
.wd (mio_outsel_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[21].q ),
+ .q (reg2hw.mio_outsel[21].q),
// to register interface (read)
.qs (mio_outsel_21_qs)
@@ -4863,20 +4863,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_22_we & mio_outsel_regwen_22_qs),
.wd (mio_outsel_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[22].q ),
+ .q (reg2hw.mio_outsel[22].q),
// to register interface (read)
.qs (mio_outsel_22_qs)
@@ -4890,20 +4890,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_23_we & mio_outsel_regwen_23_qs),
.wd (mio_outsel_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[23].q ),
+ .q (reg2hw.mio_outsel[23].q),
// to register interface (read)
.qs (mio_outsel_23_qs)
@@ -4917,20 +4917,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_24_we & mio_outsel_regwen_24_qs),
.wd (mio_outsel_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[24].q ),
+ .q (reg2hw.mio_outsel[24].q),
// to register interface (read)
.qs (mio_outsel_24_qs)
@@ -4944,20 +4944,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_25_we & mio_outsel_regwen_25_qs),
.wd (mio_outsel_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[25].q ),
+ .q (reg2hw.mio_outsel[25].q),
// to register interface (read)
.qs (mio_outsel_25_qs)
@@ -4971,20 +4971,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_26_we & mio_outsel_regwen_26_qs),
.wd (mio_outsel_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[26].q ),
+ .q (reg2hw.mio_outsel[26].q),
// to register interface (read)
.qs (mio_outsel_26_qs)
@@ -4998,20 +4998,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_27_we & mio_outsel_regwen_27_qs),
.wd (mio_outsel_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[27].q ),
+ .q (reg2hw.mio_outsel[27].q),
// to register interface (read)
.qs (mio_outsel_27_qs)
@@ -5025,20 +5025,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_28_we & mio_outsel_regwen_28_qs),
.wd (mio_outsel_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[28].q ),
+ .q (reg2hw.mio_outsel[28].q),
// to register interface (read)
.qs (mio_outsel_28_qs)
@@ -5052,20 +5052,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_29_we & mio_outsel_regwen_29_qs),
.wd (mio_outsel_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[29].q ),
+ .q (reg2hw.mio_outsel[29].q),
// to register interface (read)
.qs (mio_outsel_29_qs)
@@ -5079,20 +5079,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_30_we & mio_outsel_regwen_30_qs),
.wd (mio_outsel_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[30].q ),
+ .q (reg2hw.mio_outsel[30].q),
// to register interface (read)
.qs (mio_outsel_30_qs)
@@ -5106,20 +5106,20 @@
.SWACCESS("RW"),
.RESVAL (6'h2)
) u_mio_outsel_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_31_we & mio_outsel_regwen_31_qs),
.wd (mio_outsel_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[31].q ),
+ .q (reg2hw.mio_outsel[31].q),
// to register interface (read)
.qs (mio_outsel_31_qs)
@@ -5135,8 +5135,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_0_we),
@@ -5144,7 +5144,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5162,8 +5162,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_1_we),
@@ -5171,7 +5171,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5189,8 +5189,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_2_we),
@@ -5198,7 +5198,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5216,8 +5216,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_3_we),
@@ -5225,7 +5225,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5243,8 +5243,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_4_we),
@@ -5252,7 +5252,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5270,8 +5270,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_5_we),
@@ -5279,7 +5279,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5297,8 +5297,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_6_we),
@@ -5306,7 +5306,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5324,8 +5324,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_7_we),
@@ -5333,7 +5333,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5351,8 +5351,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_8_we),
@@ -5360,7 +5360,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5378,8 +5378,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_9_we),
@@ -5387,7 +5387,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5405,8 +5405,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_10_we),
@@ -5414,7 +5414,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5432,8 +5432,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_11_we),
@@ -5441,7 +5441,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5459,8 +5459,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_12_we),
@@ -5468,7 +5468,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5486,8 +5486,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_13_we),
@@ -5495,7 +5495,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5513,8 +5513,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_14_we),
@@ -5522,7 +5522,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5540,8 +5540,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_15_we),
@@ -5549,7 +5549,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5567,8 +5567,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_16_we),
@@ -5576,7 +5576,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5594,8 +5594,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_17_we),
@@ -5603,7 +5603,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5621,8 +5621,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_18_we),
@@ -5630,7 +5630,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5648,8 +5648,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_19_we),
@@ -5657,7 +5657,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5675,8 +5675,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_20_we),
@@ -5684,7 +5684,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5702,8 +5702,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_21_we),
@@ -5711,7 +5711,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5729,8 +5729,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_22_we),
@@ -5738,7 +5738,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5756,8 +5756,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_23_we),
@@ -5765,7 +5765,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5783,8 +5783,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_24_we),
@@ -5792,7 +5792,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5810,8 +5810,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_25_we),
@@ -5819,7 +5819,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5837,8 +5837,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_26_we),
@@ -5846,7 +5846,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5864,8 +5864,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_27_we),
@@ -5873,7 +5873,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5891,8 +5891,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_28_we),
@@ -5900,7 +5900,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5918,8 +5918,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_29_we),
@@ -5927,7 +5927,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5945,8 +5945,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_30_we),
@@ -5954,7 +5954,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5972,8 +5972,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_31_we),
@@ -5981,7 +5981,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6000,13 +6000,12 @@
.DW (13)
) u_mio_pad_attr_0 (
.re (mio_pad_attr_0_re),
- // qualified with register enable
.we (mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs),
.wd (mio_pad_attr_0_wd),
.d (hw2reg.mio_pad_attr[0].d),
.qre (),
.qe (reg2hw.mio_pad_attr[0].qe),
- .q (reg2hw.mio_pad_attr[0].q ),
+ .q (reg2hw.mio_pad_attr[0].q),
.qs (mio_pad_attr_0_qs)
);
@@ -6017,13 +6016,12 @@
.DW (13)
) u_mio_pad_attr_1 (
.re (mio_pad_attr_1_re),
- // qualified with register enable
.we (mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs),
.wd (mio_pad_attr_1_wd),
.d (hw2reg.mio_pad_attr[1].d),
.qre (),
.qe (reg2hw.mio_pad_attr[1].qe),
- .q (reg2hw.mio_pad_attr[1].q ),
+ .q (reg2hw.mio_pad_attr[1].q),
.qs (mio_pad_attr_1_qs)
);
@@ -6034,13 +6032,12 @@
.DW (13)
) u_mio_pad_attr_2 (
.re (mio_pad_attr_2_re),
- // qualified with register enable
.we (mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs),
.wd (mio_pad_attr_2_wd),
.d (hw2reg.mio_pad_attr[2].d),
.qre (),
.qe (reg2hw.mio_pad_attr[2].qe),
- .q (reg2hw.mio_pad_attr[2].q ),
+ .q (reg2hw.mio_pad_attr[2].q),
.qs (mio_pad_attr_2_qs)
);
@@ -6051,13 +6048,12 @@
.DW (13)
) u_mio_pad_attr_3 (
.re (mio_pad_attr_3_re),
- // qualified with register enable
.we (mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs),
.wd (mio_pad_attr_3_wd),
.d (hw2reg.mio_pad_attr[3].d),
.qre (),
.qe (reg2hw.mio_pad_attr[3].qe),
- .q (reg2hw.mio_pad_attr[3].q ),
+ .q (reg2hw.mio_pad_attr[3].q),
.qs (mio_pad_attr_3_qs)
);
@@ -6068,13 +6064,12 @@
.DW (13)
) u_mio_pad_attr_4 (
.re (mio_pad_attr_4_re),
- // qualified with register enable
.we (mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs),
.wd (mio_pad_attr_4_wd),
.d (hw2reg.mio_pad_attr[4].d),
.qre (),
.qe (reg2hw.mio_pad_attr[4].qe),
- .q (reg2hw.mio_pad_attr[4].q ),
+ .q (reg2hw.mio_pad_attr[4].q),
.qs (mio_pad_attr_4_qs)
);
@@ -6085,13 +6080,12 @@
.DW (13)
) u_mio_pad_attr_5 (
.re (mio_pad_attr_5_re),
- // qualified with register enable
.we (mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs),
.wd (mio_pad_attr_5_wd),
.d (hw2reg.mio_pad_attr[5].d),
.qre (),
.qe (reg2hw.mio_pad_attr[5].qe),
- .q (reg2hw.mio_pad_attr[5].q ),
+ .q (reg2hw.mio_pad_attr[5].q),
.qs (mio_pad_attr_5_qs)
);
@@ -6102,13 +6096,12 @@
.DW (13)
) u_mio_pad_attr_6 (
.re (mio_pad_attr_6_re),
- // qualified with register enable
.we (mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs),
.wd (mio_pad_attr_6_wd),
.d (hw2reg.mio_pad_attr[6].d),
.qre (),
.qe (reg2hw.mio_pad_attr[6].qe),
- .q (reg2hw.mio_pad_attr[6].q ),
+ .q (reg2hw.mio_pad_attr[6].q),
.qs (mio_pad_attr_6_qs)
);
@@ -6119,13 +6112,12 @@
.DW (13)
) u_mio_pad_attr_7 (
.re (mio_pad_attr_7_re),
- // qualified with register enable
.we (mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs),
.wd (mio_pad_attr_7_wd),
.d (hw2reg.mio_pad_attr[7].d),
.qre (),
.qe (reg2hw.mio_pad_attr[7].qe),
- .q (reg2hw.mio_pad_attr[7].q ),
+ .q (reg2hw.mio_pad_attr[7].q),
.qs (mio_pad_attr_7_qs)
);
@@ -6136,13 +6128,12 @@
.DW (13)
) u_mio_pad_attr_8 (
.re (mio_pad_attr_8_re),
- // qualified with register enable
.we (mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs),
.wd (mio_pad_attr_8_wd),
.d (hw2reg.mio_pad_attr[8].d),
.qre (),
.qe (reg2hw.mio_pad_attr[8].qe),
- .q (reg2hw.mio_pad_attr[8].q ),
+ .q (reg2hw.mio_pad_attr[8].q),
.qs (mio_pad_attr_8_qs)
);
@@ -6153,13 +6144,12 @@
.DW (13)
) u_mio_pad_attr_9 (
.re (mio_pad_attr_9_re),
- // qualified with register enable
.we (mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs),
.wd (mio_pad_attr_9_wd),
.d (hw2reg.mio_pad_attr[9].d),
.qre (),
.qe (reg2hw.mio_pad_attr[9].qe),
- .q (reg2hw.mio_pad_attr[9].q ),
+ .q (reg2hw.mio_pad_attr[9].q),
.qs (mio_pad_attr_9_qs)
);
@@ -6170,13 +6160,12 @@
.DW (13)
) u_mio_pad_attr_10 (
.re (mio_pad_attr_10_re),
- // qualified with register enable
.we (mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs),
.wd (mio_pad_attr_10_wd),
.d (hw2reg.mio_pad_attr[10].d),
.qre (),
.qe (reg2hw.mio_pad_attr[10].qe),
- .q (reg2hw.mio_pad_attr[10].q ),
+ .q (reg2hw.mio_pad_attr[10].q),
.qs (mio_pad_attr_10_qs)
);
@@ -6187,13 +6176,12 @@
.DW (13)
) u_mio_pad_attr_11 (
.re (mio_pad_attr_11_re),
- // qualified with register enable
.we (mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs),
.wd (mio_pad_attr_11_wd),
.d (hw2reg.mio_pad_attr[11].d),
.qre (),
.qe (reg2hw.mio_pad_attr[11].qe),
- .q (reg2hw.mio_pad_attr[11].q ),
+ .q (reg2hw.mio_pad_attr[11].q),
.qs (mio_pad_attr_11_qs)
);
@@ -6204,13 +6192,12 @@
.DW (13)
) u_mio_pad_attr_12 (
.re (mio_pad_attr_12_re),
- // qualified with register enable
.we (mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs),
.wd (mio_pad_attr_12_wd),
.d (hw2reg.mio_pad_attr[12].d),
.qre (),
.qe (reg2hw.mio_pad_attr[12].qe),
- .q (reg2hw.mio_pad_attr[12].q ),
+ .q (reg2hw.mio_pad_attr[12].q),
.qs (mio_pad_attr_12_qs)
);
@@ -6221,13 +6208,12 @@
.DW (13)
) u_mio_pad_attr_13 (
.re (mio_pad_attr_13_re),
- // qualified with register enable
.we (mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs),
.wd (mio_pad_attr_13_wd),
.d (hw2reg.mio_pad_attr[13].d),
.qre (),
.qe (reg2hw.mio_pad_attr[13].qe),
- .q (reg2hw.mio_pad_attr[13].q ),
+ .q (reg2hw.mio_pad_attr[13].q),
.qs (mio_pad_attr_13_qs)
);
@@ -6238,13 +6224,12 @@
.DW (13)
) u_mio_pad_attr_14 (
.re (mio_pad_attr_14_re),
- // qualified with register enable
.we (mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs),
.wd (mio_pad_attr_14_wd),
.d (hw2reg.mio_pad_attr[14].d),
.qre (),
.qe (reg2hw.mio_pad_attr[14].qe),
- .q (reg2hw.mio_pad_attr[14].q ),
+ .q (reg2hw.mio_pad_attr[14].q),
.qs (mio_pad_attr_14_qs)
);
@@ -6255,13 +6240,12 @@
.DW (13)
) u_mio_pad_attr_15 (
.re (mio_pad_attr_15_re),
- // qualified with register enable
.we (mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs),
.wd (mio_pad_attr_15_wd),
.d (hw2reg.mio_pad_attr[15].d),
.qre (),
.qe (reg2hw.mio_pad_attr[15].qe),
- .q (reg2hw.mio_pad_attr[15].q ),
+ .q (reg2hw.mio_pad_attr[15].q),
.qs (mio_pad_attr_15_qs)
);
@@ -6272,13 +6256,12 @@
.DW (13)
) u_mio_pad_attr_16 (
.re (mio_pad_attr_16_re),
- // qualified with register enable
.we (mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs),
.wd (mio_pad_attr_16_wd),
.d (hw2reg.mio_pad_attr[16].d),
.qre (),
.qe (reg2hw.mio_pad_attr[16].qe),
- .q (reg2hw.mio_pad_attr[16].q ),
+ .q (reg2hw.mio_pad_attr[16].q),
.qs (mio_pad_attr_16_qs)
);
@@ -6289,13 +6272,12 @@
.DW (13)
) u_mio_pad_attr_17 (
.re (mio_pad_attr_17_re),
- // qualified with register enable
.we (mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs),
.wd (mio_pad_attr_17_wd),
.d (hw2reg.mio_pad_attr[17].d),
.qre (),
.qe (reg2hw.mio_pad_attr[17].qe),
- .q (reg2hw.mio_pad_attr[17].q ),
+ .q (reg2hw.mio_pad_attr[17].q),
.qs (mio_pad_attr_17_qs)
);
@@ -6306,13 +6288,12 @@
.DW (13)
) u_mio_pad_attr_18 (
.re (mio_pad_attr_18_re),
- // qualified with register enable
.we (mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs),
.wd (mio_pad_attr_18_wd),
.d (hw2reg.mio_pad_attr[18].d),
.qre (),
.qe (reg2hw.mio_pad_attr[18].qe),
- .q (reg2hw.mio_pad_attr[18].q ),
+ .q (reg2hw.mio_pad_attr[18].q),
.qs (mio_pad_attr_18_qs)
);
@@ -6323,13 +6304,12 @@
.DW (13)
) u_mio_pad_attr_19 (
.re (mio_pad_attr_19_re),
- // qualified with register enable
.we (mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs),
.wd (mio_pad_attr_19_wd),
.d (hw2reg.mio_pad_attr[19].d),
.qre (),
.qe (reg2hw.mio_pad_attr[19].qe),
- .q (reg2hw.mio_pad_attr[19].q ),
+ .q (reg2hw.mio_pad_attr[19].q),
.qs (mio_pad_attr_19_qs)
);
@@ -6340,13 +6320,12 @@
.DW (13)
) u_mio_pad_attr_20 (
.re (mio_pad_attr_20_re),
- // qualified with register enable
.we (mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs),
.wd (mio_pad_attr_20_wd),
.d (hw2reg.mio_pad_attr[20].d),
.qre (),
.qe (reg2hw.mio_pad_attr[20].qe),
- .q (reg2hw.mio_pad_attr[20].q ),
+ .q (reg2hw.mio_pad_attr[20].q),
.qs (mio_pad_attr_20_qs)
);
@@ -6357,13 +6336,12 @@
.DW (13)
) u_mio_pad_attr_21 (
.re (mio_pad_attr_21_re),
- // qualified with register enable
.we (mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs),
.wd (mio_pad_attr_21_wd),
.d (hw2reg.mio_pad_attr[21].d),
.qre (),
.qe (reg2hw.mio_pad_attr[21].qe),
- .q (reg2hw.mio_pad_attr[21].q ),
+ .q (reg2hw.mio_pad_attr[21].q),
.qs (mio_pad_attr_21_qs)
);
@@ -6374,13 +6352,12 @@
.DW (13)
) u_mio_pad_attr_22 (
.re (mio_pad_attr_22_re),
- // qualified with register enable
.we (mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs),
.wd (mio_pad_attr_22_wd),
.d (hw2reg.mio_pad_attr[22].d),
.qre (),
.qe (reg2hw.mio_pad_attr[22].qe),
- .q (reg2hw.mio_pad_attr[22].q ),
+ .q (reg2hw.mio_pad_attr[22].q),
.qs (mio_pad_attr_22_qs)
);
@@ -6391,13 +6368,12 @@
.DW (13)
) u_mio_pad_attr_23 (
.re (mio_pad_attr_23_re),
- // qualified with register enable
.we (mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs),
.wd (mio_pad_attr_23_wd),
.d (hw2reg.mio_pad_attr[23].d),
.qre (),
.qe (reg2hw.mio_pad_attr[23].qe),
- .q (reg2hw.mio_pad_attr[23].q ),
+ .q (reg2hw.mio_pad_attr[23].q),
.qs (mio_pad_attr_23_qs)
);
@@ -6408,13 +6384,12 @@
.DW (13)
) u_mio_pad_attr_24 (
.re (mio_pad_attr_24_re),
- // qualified with register enable
.we (mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs),
.wd (mio_pad_attr_24_wd),
.d (hw2reg.mio_pad_attr[24].d),
.qre (),
.qe (reg2hw.mio_pad_attr[24].qe),
- .q (reg2hw.mio_pad_attr[24].q ),
+ .q (reg2hw.mio_pad_attr[24].q),
.qs (mio_pad_attr_24_qs)
);
@@ -6425,13 +6400,12 @@
.DW (13)
) u_mio_pad_attr_25 (
.re (mio_pad_attr_25_re),
- // qualified with register enable
.we (mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs),
.wd (mio_pad_attr_25_wd),
.d (hw2reg.mio_pad_attr[25].d),
.qre (),
.qe (reg2hw.mio_pad_attr[25].qe),
- .q (reg2hw.mio_pad_attr[25].q ),
+ .q (reg2hw.mio_pad_attr[25].q),
.qs (mio_pad_attr_25_qs)
);
@@ -6442,13 +6416,12 @@
.DW (13)
) u_mio_pad_attr_26 (
.re (mio_pad_attr_26_re),
- // qualified with register enable
.we (mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs),
.wd (mio_pad_attr_26_wd),
.d (hw2reg.mio_pad_attr[26].d),
.qre (),
.qe (reg2hw.mio_pad_attr[26].qe),
- .q (reg2hw.mio_pad_attr[26].q ),
+ .q (reg2hw.mio_pad_attr[26].q),
.qs (mio_pad_attr_26_qs)
);
@@ -6459,13 +6432,12 @@
.DW (13)
) u_mio_pad_attr_27 (
.re (mio_pad_attr_27_re),
- // qualified with register enable
.we (mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs),
.wd (mio_pad_attr_27_wd),
.d (hw2reg.mio_pad_attr[27].d),
.qre (),
.qe (reg2hw.mio_pad_attr[27].qe),
- .q (reg2hw.mio_pad_attr[27].q ),
+ .q (reg2hw.mio_pad_attr[27].q),
.qs (mio_pad_attr_27_qs)
);
@@ -6476,13 +6448,12 @@
.DW (13)
) u_mio_pad_attr_28 (
.re (mio_pad_attr_28_re),
- // qualified with register enable
.we (mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs),
.wd (mio_pad_attr_28_wd),
.d (hw2reg.mio_pad_attr[28].d),
.qre (),
.qe (reg2hw.mio_pad_attr[28].qe),
- .q (reg2hw.mio_pad_attr[28].q ),
+ .q (reg2hw.mio_pad_attr[28].q),
.qs (mio_pad_attr_28_qs)
);
@@ -6493,13 +6464,12 @@
.DW (13)
) u_mio_pad_attr_29 (
.re (mio_pad_attr_29_re),
- // qualified with register enable
.we (mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs),
.wd (mio_pad_attr_29_wd),
.d (hw2reg.mio_pad_attr[29].d),
.qre (),
.qe (reg2hw.mio_pad_attr[29].qe),
- .q (reg2hw.mio_pad_attr[29].q ),
+ .q (reg2hw.mio_pad_attr[29].q),
.qs (mio_pad_attr_29_qs)
);
@@ -6510,13 +6480,12 @@
.DW (13)
) u_mio_pad_attr_30 (
.re (mio_pad_attr_30_re),
- // qualified with register enable
.we (mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs),
.wd (mio_pad_attr_30_wd),
.d (hw2reg.mio_pad_attr[30].d),
.qre (),
.qe (reg2hw.mio_pad_attr[30].qe),
- .q (reg2hw.mio_pad_attr[30].q ),
+ .q (reg2hw.mio_pad_attr[30].q),
.qs (mio_pad_attr_30_qs)
);
@@ -6527,13 +6496,12 @@
.DW (13)
) u_mio_pad_attr_31 (
.re (mio_pad_attr_31_re),
- // qualified with register enable
.we (mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs),
.wd (mio_pad_attr_31_wd),
.d (hw2reg.mio_pad_attr[31].d),
.qre (),
.qe (reg2hw.mio_pad_attr[31].qe),
- .q (reg2hw.mio_pad_attr[31].q ),
+ .q (reg2hw.mio_pad_attr[31].q),
.qs (mio_pad_attr_31_qs)
);
@@ -6547,8 +6515,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_0_we),
@@ -6556,7 +6524,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6574,8 +6542,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_1_we),
@@ -6583,7 +6551,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6601,8 +6569,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_2_we),
@@ -6610,7 +6578,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6628,8 +6596,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_3_we),
@@ -6637,7 +6605,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6655,8 +6623,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_4_we),
@@ -6664,7 +6632,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6682,8 +6650,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_5_we),
@@ -6691,7 +6659,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6709,8 +6677,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_6_we),
@@ -6718,7 +6686,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6736,8 +6704,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_7_we),
@@ -6745,7 +6713,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6763,8 +6731,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_8_we),
@@ -6772,7 +6740,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6790,8 +6758,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_9_we),
@@ -6799,7 +6767,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6817,8 +6785,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_10_we),
@@ -6826,7 +6794,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6844,8 +6812,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_11_we),
@@ -6853,7 +6821,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6871,8 +6839,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_12_we),
@@ -6880,7 +6848,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6898,8 +6866,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_13_we),
@@ -6907,7 +6875,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6925,8 +6893,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_14_we),
@@ -6934,7 +6902,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6952,8 +6920,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_15_we),
@@ -6961,7 +6929,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6980,13 +6948,12 @@
.DW (13)
) u_dio_pad_attr_0 (
.re (dio_pad_attr_0_re),
- // qualified with register enable
.we (dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs),
.wd (dio_pad_attr_0_wd),
.d (hw2reg.dio_pad_attr[0].d),
.qre (),
.qe (reg2hw.dio_pad_attr[0].qe),
- .q (reg2hw.dio_pad_attr[0].q ),
+ .q (reg2hw.dio_pad_attr[0].q),
.qs (dio_pad_attr_0_qs)
);
@@ -6997,13 +6964,12 @@
.DW (13)
) u_dio_pad_attr_1 (
.re (dio_pad_attr_1_re),
- // qualified with register enable
.we (dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs),
.wd (dio_pad_attr_1_wd),
.d (hw2reg.dio_pad_attr[1].d),
.qre (),
.qe (reg2hw.dio_pad_attr[1].qe),
- .q (reg2hw.dio_pad_attr[1].q ),
+ .q (reg2hw.dio_pad_attr[1].q),
.qs (dio_pad_attr_1_qs)
);
@@ -7014,13 +6980,12 @@
.DW (13)
) u_dio_pad_attr_2 (
.re (dio_pad_attr_2_re),
- // qualified with register enable
.we (dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs),
.wd (dio_pad_attr_2_wd),
.d (hw2reg.dio_pad_attr[2].d),
.qre (),
.qe (reg2hw.dio_pad_attr[2].qe),
- .q (reg2hw.dio_pad_attr[2].q ),
+ .q (reg2hw.dio_pad_attr[2].q),
.qs (dio_pad_attr_2_qs)
);
@@ -7031,13 +6996,12 @@
.DW (13)
) u_dio_pad_attr_3 (
.re (dio_pad_attr_3_re),
- // qualified with register enable
.we (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs),
.wd (dio_pad_attr_3_wd),
.d (hw2reg.dio_pad_attr[3].d),
.qre (),
.qe (reg2hw.dio_pad_attr[3].qe),
- .q (reg2hw.dio_pad_attr[3].q ),
+ .q (reg2hw.dio_pad_attr[3].q),
.qs (dio_pad_attr_3_qs)
);
@@ -7048,13 +7012,12 @@
.DW (13)
) u_dio_pad_attr_4 (
.re (dio_pad_attr_4_re),
- // qualified with register enable
.we (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs),
.wd (dio_pad_attr_4_wd),
.d (hw2reg.dio_pad_attr[4].d),
.qre (),
.qe (reg2hw.dio_pad_attr[4].qe),
- .q (reg2hw.dio_pad_attr[4].q ),
+ .q (reg2hw.dio_pad_attr[4].q),
.qs (dio_pad_attr_4_qs)
);
@@ -7065,13 +7028,12 @@
.DW (13)
) u_dio_pad_attr_5 (
.re (dio_pad_attr_5_re),
- // qualified with register enable
.we (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs),
.wd (dio_pad_attr_5_wd),
.d (hw2reg.dio_pad_attr[5].d),
.qre (),
.qe (reg2hw.dio_pad_attr[5].qe),
- .q (reg2hw.dio_pad_attr[5].q ),
+ .q (reg2hw.dio_pad_attr[5].q),
.qs (dio_pad_attr_5_qs)
);
@@ -7082,13 +7044,12 @@
.DW (13)
) u_dio_pad_attr_6 (
.re (dio_pad_attr_6_re),
- // qualified with register enable
.we (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs),
.wd (dio_pad_attr_6_wd),
.d (hw2reg.dio_pad_attr[6].d),
.qre (),
.qe (reg2hw.dio_pad_attr[6].qe),
- .q (reg2hw.dio_pad_attr[6].q ),
+ .q (reg2hw.dio_pad_attr[6].q),
.qs (dio_pad_attr_6_qs)
);
@@ -7099,13 +7060,12 @@
.DW (13)
) u_dio_pad_attr_7 (
.re (dio_pad_attr_7_re),
- // qualified with register enable
.we (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs),
.wd (dio_pad_attr_7_wd),
.d (hw2reg.dio_pad_attr[7].d),
.qre (),
.qe (reg2hw.dio_pad_attr[7].qe),
- .q (reg2hw.dio_pad_attr[7].q ),
+ .q (reg2hw.dio_pad_attr[7].q),
.qs (dio_pad_attr_7_qs)
);
@@ -7116,13 +7076,12 @@
.DW (13)
) u_dio_pad_attr_8 (
.re (dio_pad_attr_8_re),
- // qualified with register enable
.we (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs),
.wd (dio_pad_attr_8_wd),
.d (hw2reg.dio_pad_attr[8].d),
.qre (),
.qe (reg2hw.dio_pad_attr[8].qe),
- .q (reg2hw.dio_pad_attr[8].q ),
+ .q (reg2hw.dio_pad_attr[8].q),
.qs (dio_pad_attr_8_qs)
);
@@ -7133,13 +7092,12 @@
.DW (13)
) u_dio_pad_attr_9 (
.re (dio_pad_attr_9_re),
- // qualified with register enable
.we (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs),
.wd (dio_pad_attr_9_wd),
.d (hw2reg.dio_pad_attr[9].d),
.qre (),
.qe (reg2hw.dio_pad_attr[9].qe),
- .q (reg2hw.dio_pad_attr[9].q ),
+ .q (reg2hw.dio_pad_attr[9].q),
.qs (dio_pad_attr_9_qs)
);
@@ -7150,13 +7108,12 @@
.DW (13)
) u_dio_pad_attr_10 (
.re (dio_pad_attr_10_re),
- // qualified with register enable
.we (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs),
.wd (dio_pad_attr_10_wd),
.d (hw2reg.dio_pad_attr[10].d),
.qre (),
.qe (reg2hw.dio_pad_attr[10].qe),
- .q (reg2hw.dio_pad_attr[10].q ),
+ .q (reg2hw.dio_pad_attr[10].q),
.qs (dio_pad_attr_10_qs)
);
@@ -7167,13 +7124,12 @@
.DW (13)
) u_dio_pad_attr_11 (
.re (dio_pad_attr_11_re),
- // qualified with register enable
.we (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs),
.wd (dio_pad_attr_11_wd),
.d (hw2reg.dio_pad_attr[11].d),
.qre (),
.qe (reg2hw.dio_pad_attr[11].qe),
- .q (reg2hw.dio_pad_attr[11].q ),
+ .q (reg2hw.dio_pad_attr[11].q),
.qs (dio_pad_attr_11_qs)
);
@@ -7184,13 +7140,12 @@
.DW (13)
) u_dio_pad_attr_12 (
.re (dio_pad_attr_12_re),
- // qualified with register enable
.we (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs),
.wd (dio_pad_attr_12_wd),
.d (hw2reg.dio_pad_attr[12].d),
.qre (),
.qe (reg2hw.dio_pad_attr[12].qe),
- .q (reg2hw.dio_pad_attr[12].q ),
+ .q (reg2hw.dio_pad_attr[12].q),
.qs (dio_pad_attr_12_qs)
);
@@ -7201,13 +7156,12 @@
.DW (13)
) u_dio_pad_attr_13 (
.re (dio_pad_attr_13_re),
- // qualified with register enable
.we (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs),
.wd (dio_pad_attr_13_wd),
.d (hw2reg.dio_pad_attr[13].d),
.qre (),
.qe (reg2hw.dio_pad_attr[13].qe),
- .q (reg2hw.dio_pad_attr[13].q ),
+ .q (reg2hw.dio_pad_attr[13].q),
.qs (dio_pad_attr_13_qs)
);
@@ -7218,13 +7172,12 @@
.DW (13)
) u_dio_pad_attr_14 (
.re (dio_pad_attr_14_re),
- // qualified with register enable
.we (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs),
.wd (dio_pad_attr_14_wd),
.d (hw2reg.dio_pad_attr[14].d),
.qre (),
.qe (reg2hw.dio_pad_attr[14].qe),
- .q (reg2hw.dio_pad_attr[14].q ),
+ .q (reg2hw.dio_pad_attr[14].q),
.qs (dio_pad_attr_14_qs)
);
@@ -7235,13 +7188,12 @@
.DW (13)
) u_dio_pad_attr_15 (
.re (dio_pad_attr_15_re),
- // qualified with register enable
.we (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs),
.wd (dio_pad_attr_15_wd),
.d (hw2reg.dio_pad_attr[15].d),
.qre (),
.qe (reg2hw.dio_pad_attr[15].qe),
- .q (reg2hw.dio_pad_attr[15].q ),
+ .q (reg2hw.dio_pad_attr[15].q),
.qs (dio_pad_attr_15_qs)
);
@@ -7256,8 +7208,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_0_we),
@@ -7265,11 +7217,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[0].de),
- .d (hw2reg.mio_pad_sleep_status[0].d ),
+ .d (hw2reg.mio_pad_sleep_status[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[0].q ),
+ .q (reg2hw.mio_pad_sleep_status[0].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_0_qs)
@@ -7282,8 +7234,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_1_we),
@@ -7291,11 +7243,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[1].de),
- .d (hw2reg.mio_pad_sleep_status[1].d ),
+ .d (hw2reg.mio_pad_sleep_status[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[1].q ),
+ .q (reg2hw.mio_pad_sleep_status[1].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_1_qs)
@@ -7308,8 +7260,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_2_we),
@@ -7317,11 +7269,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[2].de),
- .d (hw2reg.mio_pad_sleep_status[2].d ),
+ .d (hw2reg.mio_pad_sleep_status[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[2].q ),
+ .q (reg2hw.mio_pad_sleep_status[2].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_2_qs)
@@ -7334,8 +7286,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_3_we),
@@ -7343,11 +7295,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[3].de),
- .d (hw2reg.mio_pad_sleep_status[3].d ),
+ .d (hw2reg.mio_pad_sleep_status[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[3].q ),
+ .q (reg2hw.mio_pad_sleep_status[3].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_3_qs)
@@ -7360,8 +7312,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_4_we),
@@ -7369,11 +7321,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[4].de),
- .d (hw2reg.mio_pad_sleep_status[4].d ),
+ .d (hw2reg.mio_pad_sleep_status[4].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[4].q ),
+ .q (reg2hw.mio_pad_sleep_status[4].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_4_qs)
@@ -7386,8 +7338,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_5_we),
@@ -7395,11 +7347,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[5].de),
- .d (hw2reg.mio_pad_sleep_status[5].d ),
+ .d (hw2reg.mio_pad_sleep_status[5].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[5].q ),
+ .q (reg2hw.mio_pad_sleep_status[5].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_5_qs)
@@ -7412,8 +7364,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_6_we),
@@ -7421,11 +7373,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[6].de),
- .d (hw2reg.mio_pad_sleep_status[6].d ),
+ .d (hw2reg.mio_pad_sleep_status[6].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[6].q ),
+ .q (reg2hw.mio_pad_sleep_status[6].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_6_qs)
@@ -7438,8 +7390,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_7_we),
@@ -7447,11 +7399,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[7].de),
- .d (hw2reg.mio_pad_sleep_status[7].d ),
+ .d (hw2reg.mio_pad_sleep_status[7].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[7].q ),
+ .q (reg2hw.mio_pad_sleep_status[7].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_7_qs)
@@ -7464,8 +7416,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_8_we),
@@ -7473,11 +7425,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[8].de),
- .d (hw2reg.mio_pad_sleep_status[8].d ),
+ .d (hw2reg.mio_pad_sleep_status[8].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[8].q ),
+ .q (reg2hw.mio_pad_sleep_status[8].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_8_qs)
@@ -7490,8 +7442,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_9_we),
@@ -7499,11 +7451,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[9].de),
- .d (hw2reg.mio_pad_sleep_status[9].d ),
+ .d (hw2reg.mio_pad_sleep_status[9].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[9].q ),
+ .q (reg2hw.mio_pad_sleep_status[9].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_9_qs)
@@ -7516,8 +7468,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_10_we),
@@ -7525,11 +7477,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[10].de),
- .d (hw2reg.mio_pad_sleep_status[10].d ),
+ .d (hw2reg.mio_pad_sleep_status[10].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[10].q ),
+ .q (reg2hw.mio_pad_sleep_status[10].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_10_qs)
@@ -7542,8 +7494,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_11_we),
@@ -7551,11 +7503,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[11].de),
- .d (hw2reg.mio_pad_sleep_status[11].d ),
+ .d (hw2reg.mio_pad_sleep_status[11].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[11].q ),
+ .q (reg2hw.mio_pad_sleep_status[11].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_11_qs)
@@ -7568,8 +7520,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_12_we),
@@ -7577,11 +7529,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[12].de),
- .d (hw2reg.mio_pad_sleep_status[12].d ),
+ .d (hw2reg.mio_pad_sleep_status[12].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[12].q ),
+ .q (reg2hw.mio_pad_sleep_status[12].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_12_qs)
@@ -7594,8 +7546,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_13_we),
@@ -7603,11 +7555,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[13].de),
- .d (hw2reg.mio_pad_sleep_status[13].d ),
+ .d (hw2reg.mio_pad_sleep_status[13].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[13].q ),
+ .q (reg2hw.mio_pad_sleep_status[13].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_13_qs)
@@ -7620,8 +7572,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_14_we),
@@ -7629,11 +7581,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[14].de),
- .d (hw2reg.mio_pad_sleep_status[14].d ),
+ .d (hw2reg.mio_pad_sleep_status[14].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[14].q ),
+ .q (reg2hw.mio_pad_sleep_status[14].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_14_qs)
@@ -7646,8 +7598,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_15_we),
@@ -7655,11 +7607,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[15].de),
- .d (hw2reg.mio_pad_sleep_status[15].d ),
+ .d (hw2reg.mio_pad_sleep_status[15].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[15].q ),
+ .q (reg2hw.mio_pad_sleep_status[15].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_15_qs)
@@ -7672,8 +7624,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_16_we),
@@ -7681,11 +7633,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[16].de),
- .d (hw2reg.mio_pad_sleep_status[16].d ),
+ .d (hw2reg.mio_pad_sleep_status[16].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[16].q ),
+ .q (reg2hw.mio_pad_sleep_status[16].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_16_qs)
@@ -7698,8 +7650,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_17_we),
@@ -7707,11 +7659,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[17].de),
- .d (hw2reg.mio_pad_sleep_status[17].d ),
+ .d (hw2reg.mio_pad_sleep_status[17].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[17].q ),
+ .q (reg2hw.mio_pad_sleep_status[17].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_17_qs)
@@ -7724,8 +7676,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_18_we),
@@ -7733,11 +7685,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[18].de),
- .d (hw2reg.mio_pad_sleep_status[18].d ),
+ .d (hw2reg.mio_pad_sleep_status[18].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[18].q ),
+ .q (reg2hw.mio_pad_sleep_status[18].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_18_qs)
@@ -7750,8 +7702,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_19_we),
@@ -7759,11 +7711,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[19].de),
- .d (hw2reg.mio_pad_sleep_status[19].d ),
+ .d (hw2reg.mio_pad_sleep_status[19].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[19].q ),
+ .q (reg2hw.mio_pad_sleep_status[19].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_19_qs)
@@ -7776,8 +7728,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_20_we),
@@ -7785,11 +7737,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[20].de),
- .d (hw2reg.mio_pad_sleep_status[20].d ),
+ .d (hw2reg.mio_pad_sleep_status[20].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[20].q ),
+ .q (reg2hw.mio_pad_sleep_status[20].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_20_qs)
@@ -7802,8 +7754,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_21_we),
@@ -7811,11 +7763,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[21].de),
- .d (hw2reg.mio_pad_sleep_status[21].d ),
+ .d (hw2reg.mio_pad_sleep_status[21].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[21].q ),
+ .q (reg2hw.mio_pad_sleep_status[21].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_21_qs)
@@ -7828,8 +7780,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_22_we),
@@ -7837,11 +7789,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[22].de),
- .d (hw2reg.mio_pad_sleep_status[22].d ),
+ .d (hw2reg.mio_pad_sleep_status[22].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[22].q ),
+ .q (reg2hw.mio_pad_sleep_status[22].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_22_qs)
@@ -7854,8 +7806,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_23_we),
@@ -7863,11 +7815,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[23].de),
- .d (hw2reg.mio_pad_sleep_status[23].d ),
+ .d (hw2reg.mio_pad_sleep_status[23].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[23].q ),
+ .q (reg2hw.mio_pad_sleep_status[23].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_23_qs)
@@ -7880,8 +7832,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_24_we),
@@ -7889,11 +7841,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[24].de),
- .d (hw2reg.mio_pad_sleep_status[24].d ),
+ .d (hw2reg.mio_pad_sleep_status[24].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[24].q ),
+ .q (reg2hw.mio_pad_sleep_status[24].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_24_qs)
@@ -7906,8 +7858,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_25_we),
@@ -7915,11 +7867,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[25].de),
- .d (hw2reg.mio_pad_sleep_status[25].d ),
+ .d (hw2reg.mio_pad_sleep_status[25].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[25].q ),
+ .q (reg2hw.mio_pad_sleep_status[25].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_25_qs)
@@ -7932,8 +7884,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_26_we),
@@ -7941,11 +7893,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[26].de),
- .d (hw2reg.mio_pad_sleep_status[26].d ),
+ .d (hw2reg.mio_pad_sleep_status[26].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[26].q ),
+ .q (reg2hw.mio_pad_sleep_status[26].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_26_qs)
@@ -7958,8 +7910,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_27_we),
@@ -7967,11 +7919,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[27].de),
- .d (hw2reg.mio_pad_sleep_status[27].d ),
+ .d (hw2reg.mio_pad_sleep_status[27].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[27].q ),
+ .q (reg2hw.mio_pad_sleep_status[27].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_27_qs)
@@ -7984,8 +7936,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_28_we),
@@ -7993,11 +7945,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[28].de),
- .d (hw2reg.mio_pad_sleep_status[28].d ),
+ .d (hw2reg.mio_pad_sleep_status[28].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[28].q ),
+ .q (reg2hw.mio_pad_sleep_status[28].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_28_qs)
@@ -8010,8 +7962,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_29_we),
@@ -8019,11 +7971,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[29].de),
- .d (hw2reg.mio_pad_sleep_status[29].d ),
+ .d (hw2reg.mio_pad_sleep_status[29].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[29].q ),
+ .q (reg2hw.mio_pad_sleep_status[29].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_29_qs)
@@ -8036,8 +7988,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_30_we),
@@ -8045,11 +7997,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[30].de),
- .d (hw2reg.mio_pad_sleep_status[30].d ),
+ .d (hw2reg.mio_pad_sleep_status[30].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[30].q ),
+ .q (reg2hw.mio_pad_sleep_status[30].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_30_qs)
@@ -8062,8 +8014,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_en_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_en_31_we),
@@ -8071,11 +8023,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[31].de),
- .d (hw2reg.mio_pad_sleep_status[31].d ),
+ .d (hw2reg.mio_pad_sleep_status[31].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[31].q ),
+ .q (reg2hw.mio_pad_sleep_status[31].q),
// to register interface (read)
.qs (mio_pad_sleep_status_en_31_qs)
@@ -8092,8 +8044,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_0_we),
@@ -8101,7 +8053,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8119,8 +8071,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_1_we),
@@ -8128,7 +8080,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8146,8 +8098,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_2_we),
@@ -8155,7 +8107,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8173,8 +8125,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_3_we),
@@ -8182,7 +8134,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8200,8 +8152,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_4_we),
@@ -8209,7 +8161,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8227,8 +8179,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_5_we),
@@ -8236,7 +8188,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8254,8 +8206,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_6_we),
@@ -8263,7 +8215,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8281,8 +8233,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_7_we),
@@ -8290,7 +8242,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8308,8 +8260,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_8_we),
@@ -8317,7 +8269,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8335,8 +8287,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_9_we),
@@ -8344,7 +8296,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8362,8 +8314,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_10_we),
@@ -8371,7 +8323,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8389,8 +8341,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_11_we),
@@ -8398,7 +8350,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8416,8 +8368,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_12_we),
@@ -8425,7 +8377,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8443,8 +8395,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_13_we),
@@ -8452,7 +8404,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8470,8 +8422,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_14_we),
@@ -8479,7 +8431,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8497,8 +8449,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_15_we),
@@ -8506,7 +8458,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8524,8 +8476,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_16_we),
@@ -8533,7 +8485,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8551,8 +8503,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_17_we),
@@ -8560,7 +8512,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8578,8 +8530,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_18_we),
@@ -8587,7 +8539,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8605,8 +8557,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_19_we),
@@ -8614,7 +8566,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8632,8 +8584,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_20_we),
@@ -8641,7 +8593,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8659,8 +8611,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_21_we),
@@ -8668,7 +8620,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8686,8 +8638,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_22_we),
@@ -8695,7 +8647,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8713,8 +8665,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_23_we),
@@ -8722,7 +8674,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8740,8 +8692,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_24_we),
@@ -8749,7 +8701,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8767,8 +8719,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_25_we),
@@ -8776,7 +8728,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8794,8 +8746,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_26_we),
@@ -8803,7 +8755,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8821,8 +8773,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_27_we),
@@ -8830,7 +8782,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8848,8 +8800,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_28_we),
@@ -8857,7 +8809,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8875,8 +8827,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_29_we),
@@ -8884,7 +8836,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8902,8 +8854,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_30_we),
@@ -8911,7 +8863,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8929,8 +8881,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_31_we),
@@ -8938,7 +8890,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8958,20 +8910,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs),
.wd (mio_pad_sleep_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[0].q ),
+ .q (reg2hw.mio_pad_sleep_en[0].q),
// to register interface (read)
.qs (mio_pad_sleep_en_0_qs)
@@ -8985,20 +8937,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs),
.wd (mio_pad_sleep_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[1].q ),
+ .q (reg2hw.mio_pad_sleep_en[1].q),
// to register interface (read)
.qs (mio_pad_sleep_en_1_qs)
@@ -9012,20 +8964,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs),
.wd (mio_pad_sleep_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[2].q ),
+ .q (reg2hw.mio_pad_sleep_en[2].q),
// to register interface (read)
.qs (mio_pad_sleep_en_2_qs)
@@ -9039,20 +8991,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs),
.wd (mio_pad_sleep_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[3].q ),
+ .q (reg2hw.mio_pad_sleep_en[3].q),
// to register interface (read)
.qs (mio_pad_sleep_en_3_qs)
@@ -9066,20 +9018,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs),
.wd (mio_pad_sleep_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[4].q ),
+ .q (reg2hw.mio_pad_sleep_en[4].q),
// to register interface (read)
.qs (mio_pad_sleep_en_4_qs)
@@ -9093,20 +9045,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs),
.wd (mio_pad_sleep_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[5].q ),
+ .q (reg2hw.mio_pad_sleep_en[5].q),
// to register interface (read)
.qs (mio_pad_sleep_en_5_qs)
@@ -9120,20 +9072,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs),
.wd (mio_pad_sleep_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[6].q ),
+ .q (reg2hw.mio_pad_sleep_en[6].q),
// to register interface (read)
.qs (mio_pad_sleep_en_6_qs)
@@ -9147,20 +9099,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs),
.wd (mio_pad_sleep_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[7].q ),
+ .q (reg2hw.mio_pad_sleep_en[7].q),
// to register interface (read)
.qs (mio_pad_sleep_en_7_qs)
@@ -9174,20 +9126,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs),
.wd (mio_pad_sleep_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[8].q ),
+ .q (reg2hw.mio_pad_sleep_en[8].q),
// to register interface (read)
.qs (mio_pad_sleep_en_8_qs)
@@ -9201,20 +9153,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs),
.wd (mio_pad_sleep_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[9].q ),
+ .q (reg2hw.mio_pad_sleep_en[9].q),
// to register interface (read)
.qs (mio_pad_sleep_en_9_qs)
@@ -9228,20 +9180,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs),
.wd (mio_pad_sleep_en_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[10].q ),
+ .q (reg2hw.mio_pad_sleep_en[10].q),
// to register interface (read)
.qs (mio_pad_sleep_en_10_qs)
@@ -9255,20 +9207,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs),
.wd (mio_pad_sleep_en_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[11].q ),
+ .q (reg2hw.mio_pad_sleep_en[11].q),
// to register interface (read)
.qs (mio_pad_sleep_en_11_qs)
@@ -9282,20 +9234,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs),
.wd (mio_pad_sleep_en_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[12].q ),
+ .q (reg2hw.mio_pad_sleep_en[12].q),
// to register interface (read)
.qs (mio_pad_sleep_en_12_qs)
@@ -9309,20 +9261,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs),
.wd (mio_pad_sleep_en_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[13].q ),
+ .q (reg2hw.mio_pad_sleep_en[13].q),
// to register interface (read)
.qs (mio_pad_sleep_en_13_qs)
@@ -9336,20 +9288,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs),
.wd (mio_pad_sleep_en_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[14].q ),
+ .q (reg2hw.mio_pad_sleep_en[14].q),
// to register interface (read)
.qs (mio_pad_sleep_en_14_qs)
@@ -9363,20 +9315,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs),
.wd (mio_pad_sleep_en_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[15].q ),
+ .q (reg2hw.mio_pad_sleep_en[15].q),
// to register interface (read)
.qs (mio_pad_sleep_en_15_qs)
@@ -9390,20 +9342,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs),
.wd (mio_pad_sleep_en_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[16].q ),
+ .q (reg2hw.mio_pad_sleep_en[16].q),
// to register interface (read)
.qs (mio_pad_sleep_en_16_qs)
@@ -9417,20 +9369,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs),
.wd (mio_pad_sleep_en_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[17].q ),
+ .q (reg2hw.mio_pad_sleep_en[17].q),
// to register interface (read)
.qs (mio_pad_sleep_en_17_qs)
@@ -9444,20 +9396,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs),
.wd (mio_pad_sleep_en_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[18].q ),
+ .q (reg2hw.mio_pad_sleep_en[18].q),
// to register interface (read)
.qs (mio_pad_sleep_en_18_qs)
@@ -9471,20 +9423,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs),
.wd (mio_pad_sleep_en_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[19].q ),
+ .q (reg2hw.mio_pad_sleep_en[19].q),
// to register interface (read)
.qs (mio_pad_sleep_en_19_qs)
@@ -9498,20 +9450,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs),
.wd (mio_pad_sleep_en_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[20].q ),
+ .q (reg2hw.mio_pad_sleep_en[20].q),
// to register interface (read)
.qs (mio_pad_sleep_en_20_qs)
@@ -9525,20 +9477,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs),
.wd (mio_pad_sleep_en_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[21].q ),
+ .q (reg2hw.mio_pad_sleep_en[21].q),
// to register interface (read)
.qs (mio_pad_sleep_en_21_qs)
@@ -9552,20 +9504,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs),
.wd (mio_pad_sleep_en_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[22].q ),
+ .q (reg2hw.mio_pad_sleep_en[22].q),
// to register interface (read)
.qs (mio_pad_sleep_en_22_qs)
@@ -9579,20 +9531,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs),
.wd (mio_pad_sleep_en_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[23].q ),
+ .q (reg2hw.mio_pad_sleep_en[23].q),
// to register interface (read)
.qs (mio_pad_sleep_en_23_qs)
@@ -9606,20 +9558,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs),
.wd (mio_pad_sleep_en_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[24].q ),
+ .q (reg2hw.mio_pad_sleep_en[24].q),
// to register interface (read)
.qs (mio_pad_sleep_en_24_qs)
@@ -9633,20 +9585,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs),
.wd (mio_pad_sleep_en_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[25].q ),
+ .q (reg2hw.mio_pad_sleep_en[25].q),
// to register interface (read)
.qs (mio_pad_sleep_en_25_qs)
@@ -9660,20 +9612,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs),
.wd (mio_pad_sleep_en_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[26].q ),
+ .q (reg2hw.mio_pad_sleep_en[26].q),
// to register interface (read)
.qs (mio_pad_sleep_en_26_qs)
@@ -9687,20 +9639,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs),
.wd (mio_pad_sleep_en_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[27].q ),
+ .q (reg2hw.mio_pad_sleep_en[27].q),
// to register interface (read)
.qs (mio_pad_sleep_en_27_qs)
@@ -9714,20 +9666,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs),
.wd (mio_pad_sleep_en_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[28].q ),
+ .q (reg2hw.mio_pad_sleep_en[28].q),
// to register interface (read)
.qs (mio_pad_sleep_en_28_qs)
@@ -9741,20 +9693,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs),
.wd (mio_pad_sleep_en_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[29].q ),
+ .q (reg2hw.mio_pad_sleep_en[29].q),
// to register interface (read)
.qs (mio_pad_sleep_en_29_qs)
@@ -9768,20 +9720,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs),
.wd (mio_pad_sleep_en_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[30].q ),
+ .q (reg2hw.mio_pad_sleep_en[30].q),
// to register interface (read)
.qs (mio_pad_sleep_en_30_qs)
@@ -9795,20 +9747,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs),
.wd (mio_pad_sleep_en_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[31].q ),
+ .q (reg2hw.mio_pad_sleep_en[31].q),
// to register interface (read)
.qs (mio_pad_sleep_en_31_qs)
@@ -9824,20 +9776,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs),
.wd (mio_pad_sleep_mode_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[0].q ),
+ .q (reg2hw.mio_pad_sleep_mode[0].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_0_qs)
@@ -9851,20 +9803,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs),
.wd (mio_pad_sleep_mode_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[1].q ),
+ .q (reg2hw.mio_pad_sleep_mode[1].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_1_qs)
@@ -9878,20 +9830,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs),
.wd (mio_pad_sleep_mode_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[2].q ),
+ .q (reg2hw.mio_pad_sleep_mode[2].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_2_qs)
@@ -9905,20 +9857,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs),
.wd (mio_pad_sleep_mode_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[3].q ),
+ .q (reg2hw.mio_pad_sleep_mode[3].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_3_qs)
@@ -9932,20 +9884,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs),
.wd (mio_pad_sleep_mode_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[4].q ),
+ .q (reg2hw.mio_pad_sleep_mode[4].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_4_qs)
@@ -9959,20 +9911,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs),
.wd (mio_pad_sleep_mode_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[5].q ),
+ .q (reg2hw.mio_pad_sleep_mode[5].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_5_qs)
@@ -9986,20 +9938,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs),
.wd (mio_pad_sleep_mode_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[6].q ),
+ .q (reg2hw.mio_pad_sleep_mode[6].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_6_qs)
@@ -10013,20 +9965,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs),
.wd (mio_pad_sleep_mode_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[7].q ),
+ .q (reg2hw.mio_pad_sleep_mode[7].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_7_qs)
@@ -10040,20 +9992,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs),
.wd (mio_pad_sleep_mode_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[8].q ),
+ .q (reg2hw.mio_pad_sleep_mode[8].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_8_qs)
@@ -10067,20 +10019,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs),
.wd (mio_pad_sleep_mode_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[9].q ),
+ .q (reg2hw.mio_pad_sleep_mode[9].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_9_qs)
@@ -10094,20 +10046,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs),
.wd (mio_pad_sleep_mode_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[10].q ),
+ .q (reg2hw.mio_pad_sleep_mode[10].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_10_qs)
@@ -10121,20 +10073,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs),
.wd (mio_pad_sleep_mode_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[11].q ),
+ .q (reg2hw.mio_pad_sleep_mode[11].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_11_qs)
@@ -10148,20 +10100,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs),
.wd (mio_pad_sleep_mode_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[12].q ),
+ .q (reg2hw.mio_pad_sleep_mode[12].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_12_qs)
@@ -10175,20 +10127,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs),
.wd (mio_pad_sleep_mode_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[13].q ),
+ .q (reg2hw.mio_pad_sleep_mode[13].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_13_qs)
@@ -10202,20 +10154,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs),
.wd (mio_pad_sleep_mode_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[14].q ),
+ .q (reg2hw.mio_pad_sleep_mode[14].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_14_qs)
@@ -10229,20 +10181,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs),
.wd (mio_pad_sleep_mode_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[15].q ),
+ .q (reg2hw.mio_pad_sleep_mode[15].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_15_qs)
@@ -10256,20 +10208,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs),
.wd (mio_pad_sleep_mode_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[16].q ),
+ .q (reg2hw.mio_pad_sleep_mode[16].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_16_qs)
@@ -10283,20 +10235,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs),
.wd (mio_pad_sleep_mode_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[17].q ),
+ .q (reg2hw.mio_pad_sleep_mode[17].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_17_qs)
@@ -10310,20 +10262,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs),
.wd (mio_pad_sleep_mode_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[18].q ),
+ .q (reg2hw.mio_pad_sleep_mode[18].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_18_qs)
@@ -10337,20 +10289,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs),
.wd (mio_pad_sleep_mode_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[19].q ),
+ .q (reg2hw.mio_pad_sleep_mode[19].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_19_qs)
@@ -10364,20 +10316,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs),
.wd (mio_pad_sleep_mode_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[20].q ),
+ .q (reg2hw.mio_pad_sleep_mode[20].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_20_qs)
@@ -10391,20 +10343,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs),
.wd (mio_pad_sleep_mode_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[21].q ),
+ .q (reg2hw.mio_pad_sleep_mode[21].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_21_qs)
@@ -10418,20 +10370,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs),
.wd (mio_pad_sleep_mode_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[22].q ),
+ .q (reg2hw.mio_pad_sleep_mode[22].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_22_qs)
@@ -10445,20 +10397,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs),
.wd (mio_pad_sleep_mode_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[23].q ),
+ .q (reg2hw.mio_pad_sleep_mode[23].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_23_qs)
@@ -10472,20 +10424,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs),
.wd (mio_pad_sleep_mode_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[24].q ),
+ .q (reg2hw.mio_pad_sleep_mode[24].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_24_qs)
@@ -10499,20 +10451,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs),
.wd (mio_pad_sleep_mode_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[25].q ),
+ .q (reg2hw.mio_pad_sleep_mode[25].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_25_qs)
@@ -10526,20 +10478,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs),
.wd (mio_pad_sleep_mode_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[26].q ),
+ .q (reg2hw.mio_pad_sleep_mode[26].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_26_qs)
@@ -10553,20 +10505,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs),
.wd (mio_pad_sleep_mode_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[27].q ),
+ .q (reg2hw.mio_pad_sleep_mode[27].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_27_qs)
@@ -10580,20 +10532,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs),
.wd (mio_pad_sleep_mode_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[28].q ),
+ .q (reg2hw.mio_pad_sleep_mode[28].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_28_qs)
@@ -10607,20 +10559,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs),
.wd (mio_pad_sleep_mode_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[29].q ),
+ .q (reg2hw.mio_pad_sleep_mode[29].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_29_qs)
@@ -10634,20 +10586,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs),
.wd (mio_pad_sleep_mode_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[30].q ),
+ .q (reg2hw.mio_pad_sleep_mode[30].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_30_qs)
@@ -10661,20 +10613,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs),
.wd (mio_pad_sleep_mode_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[31].q ),
+ .q (reg2hw.mio_pad_sleep_mode[31].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_31_qs)
@@ -10691,8 +10643,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_0_we),
@@ -10700,11 +10652,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[0].de),
- .d (hw2reg.dio_pad_sleep_status[0].d ),
+ .d (hw2reg.dio_pad_sleep_status[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[0].q ),
+ .q (reg2hw.dio_pad_sleep_status[0].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_0_qs)
@@ -10717,8 +10669,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_1_we),
@@ -10726,11 +10678,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[1].de),
- .d (hw2reg.dio_pad_sleep_status[1].d ),
+ .d (hw2reg.dio_pad_sleep_status[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[1].q ),
+ .q (reg2hw.dio_pad_sleep_status[1].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_1_qs)
@@ -10743,8 +10695,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_2_we),
@@ -10752,11 +10704,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[2].de),
- .d (hw2reg.dio_pad_sleep_status[2].d ),
+ .d (hw2reg.dio_pad_sleep_status[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[2].q ),
+ .q (reg2hw.dio_pad_sleep_status[2].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_2_qs)
@@ -10769,8 +10721,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_3_we),
@@ -10778,11 +10730,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[3].de),
- .d (hw2reg.dio_pad_sleep_status[3].d ),
+ .d (hw2reg.dio_pad_sleep_status[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[3].q ),
+ .q (reg2hw.dio_pad_sleep_status[3].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_3_qs)
@@ -10795,8 +10747,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_4_we),
@@ -10804,11 +10756,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[4].de),
- .d (hw2reg.dio_pad_sleep_status[4].d ),
+ .d (hw2reg.dio_pad_sleep_status[4].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[4].q ),
+ .q (reg2hw.dio_pad_sleep_status[4].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_4_qs)
@@ -10821,8 +10773,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_5_we),
@@ -10830,11 +10782,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[5].de),
- .d (hw2reg.dio_pad_sleep_status[5].d ),
+ .d (hw2reg.dio_pad_sleep_status[5].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[5].q ),
+ .q (reg2hw.dio_pad_sleep_status[5].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_5_qs)
@@ -10847,8 +10799,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_6_we),
@@ -10856,11 +10808,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[6].de),
- .d (hw2reg.dio_pad_sleep_status[6].d ),
+ .d (hw2reg.dio_pad_sleep_status[6].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[6].q ),
+ .q (reg2hw.dio_pad_sleep_status[6].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_6_qs)
@@ -10873,8 +10825,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_7_we),
@@ -10882,11 +10834,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[7].de),
- .d (hw2reg.dio_pad_sleep_status[7].d ),
+ .d (hw2reg.dio_pad_sleep_status[7].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[7].q ),
+ .q (reg2hw.dio_pad_sleep_status[7].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_7_qs)
@@ -10899,8 +10851,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_8_we),
@@ -10908,11 +10860,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[8].de),
- .d (hw2reg.dio_pad_sleep_status[8].d ),
+ .d (hw2reg.dio_pad_sleep_status[8].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[8].q ),
+ .q (reg2hw.dio_pad_sleep_status[8].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_8_qs)
@@ -10925,8 +10877,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_9_we),
@@ -10934,11 +10886,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[9].de),
- .d (hw2reg.dio_pad_sleep_status[9].d ),
+ .d (hw2reg.dio_pad_sleep_status[9].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[9].q ),
+ .q (reg2hw.dio_pad_sleep_status[9].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_9_qs)
@@ -10951,8 +10903,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_10_we),
@@ -10960,11 +10912,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[10].de),
- .d (hw2reg.dio_pad_sleep_status[10].d ),
+ .d (hw2reg.dio_pad_sleep_status[10].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[10].q ),
+ .q (reg2hw.dio_pad_sleep_status[10].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_10_qs)
@@ -10977,8 +10929,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_11_we),
@@ -10986,11 +10938,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[11].de),
- .d (hw2reg.dio_pad_sleep_status[11].d ),
+ .d (hw2reg.dio_pad_sleep_status[11].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[11].q ),
+ .q (reg2hw.dio_pad_sleep_status[11].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_11_qs)
@@ -11003,8 +10955,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_12_we),
@@ -11012,11 +10964,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[12].de),
- .d (hw2reg.dio_pad_sleep_status[12].d ),
+ .d (hw2reg.dio_pad_sleep_status[12].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[12].q ),
+ .q (reg2hw.dio_pad_sleep_status[12].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_12_qs)
@@ -11029,8 +10981,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_13_we),
@@ -11038,11 +10990,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[13].de),
- .d (hw2reg.dio_pad_sleep_status[13].d ),
+ .d (hw2reg.dio_pad_sleep_status[13].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[13].q ),
+ .q (reg2hw.dio_pad_sleep_status[13].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_13_qs)
@@ -11055,8 +11007,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_14_we),
@@ -11064,11 +11016,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[14].de),
- .d (hw2reg.dio_pad_sleep_status[14].d ),
+ .d (hw2reg.dio_pad_sleep_status[14].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[14].q ),
+ .q (reg2hw.dio_pad_sleep_status[14].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_14_qs)
@@ -11081,8 +11033,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_15_we),
@@ -11090,11 +11042,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[15].de),
- .d (hw2reg.dio_pad_sleep_status[15].d ),
+ .d (hw2reg.dio_pad_sleep_status[15].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[15].q ),
+ .q (reg2hw.dio_pad_sleep_status[15].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_15_qs)
@@ -11111,8 +11063,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_0_we),
@@ -11120,7 +11072,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11138,8 +11090,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_1_we),
@@ -11147,7 +11099,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11165,8 +11117,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_2_we),
@@ -11174,7 +11126,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11192,8 +11144,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_3_we),
@@ -11201,7 +11153,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11219,8 +11171,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_4_we),
@@ -11228,7 +11180,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11246,8 +11198,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_5_we),
@@ -11255,7 +11207,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11273,8 +11225,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_6_we),
@@ -11282,7 +11234,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11300,8 +11252,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_7_we),
@@ -11309,7 +11261,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11327,8 +11279,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_8_we),
@@ -11336,7 +11288,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11354,8 +11306,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_9_we),
@@ -11363,7 +11315,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11381,8 +11333,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_10_we),
@@ -11390,7 +11342,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11408,8 +11360,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_11_we),
@@ -11417,7 +11369,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11435,8 +11387,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_12_we),
@@ -11444,7 +11396,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11462,8 +11414,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_13_we),
@@ -11471,7 +11423,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11489,8 +11441,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_14_we),
@@ -11498,7 +11450,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11516,8 +11468,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_15_we),
@@ -11525,7 +11477,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -11545,20 +11497,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs),
.wd (dio_pad_sleep_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[0].q ),
+ .q (reg2hw.dio_pad_sleep_en[0].q),
// to register interface (read)
.qs (dio_pad_sleep_en_0_qs)
@@ -11572,20 +11524,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs),
.wd (dio_pad_sleep_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[1].q ),
+ .q (reg2hw.dio_pad_sleep_en[1].q),
// to register interface (read)
.qs (dio_pad_sleep_en_1_qs)
@@ -11599,20 +11551,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs),
.wd (dio_pad_sleep_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[2].q ),
+ .q (reg2hw.dio_pad_sleep_en[2].q),
// to register interface (read)
.qs (dio_pad_sleep_en_2_qs)
@@ -11626,20 +11578,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs),
.wd (dio_pad_sleep_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[3].q ),
+ .q (reg2hw.dio_pad_sleep_en[3].q),
// to register interface (read)
.qs (dio_pad_sleep_en_3_qs)
@@ -11653,20 +11605,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs),
.wd (dio_pad_sleep_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[4].q ),
+ .q (reg2hw.dio_pad_sleep_en[4].q),
// to register interface (read)
.qs (dio_pad_sleep_en_4_qs)
@@ -11680,20 +11632,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs),
.wd (dio_pad_sleep_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[5].q ),
+ .q (reg2hw.dio_pad_sleep_en[5].q),
// to register interface (read)
.qs (dio_pad_sleep_en_5_qs)
@@ -11707,20 +11659,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs),
.wd (dio_pad_sleep_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[6].q ),
+ .q (reg2hw.dio_pad_sleep_en[6].q),
// to register interface (read)
.qs (dio_pad_sleep_en_6_qs)
@@ -11734,20 +11686,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs),
.wd (dio_pad_sleep_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[7].q ),
+ .q (reg2hw.dio_pad_sleep_en[7].q),
// to register interface (read)
.qs (dio_pad_sleep_en_7_qs)
@@ -11761,20 +11713,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs),
.wd (dio_pad_sleep_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[8].q ),
+ .q (reg2hw.dio_pad_sleep_en[8].q),
// to register interface (read)
.qs (dio_pad_sleep_en_8_qs)
@@ -11788,20 +11740,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs),
.wd (dio_pad_sleep_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[9].q ),
+ .q (reg2hw.dio_pad_sleep_en[9].q),
// to register interface (read)
.qs (dio_pad_sleep_en_9_qs)
@@ -11815,20 +11767,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs),
.wd (dio_pad_sleep_en_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[10].q ),
+ .q (reg2hw.dio_pad_sleep_en[10].q),
// to register interface (read)
.qs (dio_pad_sleep_en_10_qs)
@@ -11842,20 +11794,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs),
.wd (dio_pad_sleep_en_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[11].q ),
+ .q (reg2hw.dio_pad_sleep_en[11].q),
// to register interface (read)
.qs (dio_pad_sleep_en_11_qs)
@@ -11869,20 +11821,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs),
.wd (dio_pad_sleep_en_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[12].q ),
+ .q (reg2hw.dio_pad_sleep_en[12].q),
// to register interface (read)
.qs (dio_pad_sleep_en_12_qs)
@@ -11896,20 +11848,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs),
.wd (dio_pad_sleep_en_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[13].q ),
+ .q (reg2hw.dio_pad_sleep_en[13].q),
// to register interface (read)
.qs (dio_pad_sleep_en_13_qs)
@@ -11923,20 +11875,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs),
.wd (dio_pad_sleep_en_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[14].q ),
+ .q (reg2hw.dio_pad_sleep_en[14].q),
// to register interface (read)
.qs (dio_pad_sleep_en_14_qs)
@@ -11950,20 +11902,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs),
.wd (dio_pad_sleep_en_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[15].q ),
+ .q (reg2hw.dio_pad_sleep_en[15].q),
// to register interface (read)
.qs (dio_pad_sleep_en_15_qs)
@@ -11979,20 +11931,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs),
.wd (dio_pad_sleep_mode_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[0].q ),
+ .q (reg2hw.dio_pad_sleep_mode[0].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_0_qs)
@@ -12006,20 +11958,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs),
.wd (dio_pad_sleep_mode_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[1].q ),
+ .q (reg2hw.dio_pad_sleep_mode[1].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_1_qs)
@@ -12033,20 +11985,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs),
.wd (dio_pad_sleep_mode_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[2].q ),
+ .q (reg2hw.dio_pad_sleep_mode[2].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_2_qs)
@@ -12060,20 +12012,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs),
.wd (dio_pad_sleep_mode_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[3].q ),
+ .q (reg2hw.dio_pad_sleep_mode[3].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_3_qs)
@@ -12087,20 +12039,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs),
.wd (dio_pad_sleep_mode_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[4].q ),
+ .q (reg2hw.dio_pad_sleep_mode[4].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_4_qs)
@@ -12114,20 +12066,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs),
.wd (dio_pad_sleep_mode_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[5].q ),
+ .q (reg2hw.dio_pad_sleep_mode[5].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_5_qs)
@@ -12141,20 +12093,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs),
.wd (dio_pad_sleep_mode_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[6].q ),
+ .q (reg2hw.dio_pad_sleep_mode[6].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_6_qs)
@@ -12168,20 +12120,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs),
.wd (dio_pad_sleep_mode_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[7].q ),
+ .q (reg2hw.dio_pad_sleep_mode[7].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_7_qs)
@@ -12195,20 +12147,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs),
.wd (dio_pad_sleep_mode_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[8].q ),
+ .q (reg2hw.dio_pad_sleep_mode[8].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_8_qs)
@@ -12222,20 +12174,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs),
.wd (dio_pad_sleep_mode_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[9].q ),
+ .q (reg2hw.dio_pad_sleep_mode[9].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_9_qs)
@@ -12249,20 +12201,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs),
.wd (dio_pad_sleep_mode_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[10].q ),
+ .q (reg2hw.dio_pad_sleep_mode[10].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_10_qs)
@@ -12276,20 +12228,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs),
.wd (dio_pad_sleep_mode_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[11].q ),
+ .q (reg2hw.dio_pad_sleep_mode[11].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_11_qs)
@@ -12303,20 +12255,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs),
.wd (dio_pad_sleep_mode_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[12].q ),
+ .q (reg2hw.dio_pad_sleep_mode[12].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_12_qs)
@@ -12330,20 +12282,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs),
.wd (dio_pad_sleep_mode_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[13].q ),
+ .q (reg2hw.dio_pad_sleep_mode[13].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_13_qs)
@@ -12357,20 +12309,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs),
.wd (dio_pad_sleep_mode_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[14].q ),
+ .q (reg2hw.dio_pad_sleep_mode[14].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_14_qs)
@@ -12384,20 +12336,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs),
.wd (dio_pad_sleep_mode_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[15].q ),
+ .q (reg2hw.dio_pad_sleep_mode[15].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_15_qs)
@@ -12413,8 +12365,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_0_we),
@@ -12422,7 +12374,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12440,8 +12392,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_1_we),
@@ -12449,7 +12401,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12467,8 +12419,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_2_we),
@@ -12476,7 +12428,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12494,8 +12446,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_3_we),
@@ -12503,7 +12455,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12521,8 +12473,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_4_we),
@@ -12530,7 +12482,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12548,8 +12500,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_5_we),
@@ -12557,7 +12509,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12575,8 +12527,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_6_we),
@@ -12584,7 +12536,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12602,8 +12554,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_7_we),
@@ -12611,7 +12563,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12631,20 +12583,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[0].q ),
+ .q (reg2hw.wkup_detector_en[0].q),
// to register interface (read)
.qs (wkup_detector_en_0_qs)
@@ -12658,20 +12610,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[1].q ),
+ .q (reg2hw.wkup_detector_en[1].q),
// to register interface (read)
.qs (wkup_detector_en_1_qs)
@@ -12685,20 +12637,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[2].q ),
+ .q (reg2hw.wkup_detector_en[2].q),
// to register interface (read)
.qs (wkup_detector_en_2_qs)
@@ -12712,20 +12664,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[3].q ),
+ .q (reg2hw.wkup_detector_en[3].q),
// to register interface (read)
.qs (wkup_detector_en_3_qs)
@@ -12739,20 +12691,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[4].q ),
+ .q (reg2hw.wkup_detector_en[4].q),
// to register interface (read)
.qs (wkup_detector_en_4_qs)
@@ -12766,20 +12718,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[5].q ),
+ .q (reg2hw.wkup_detector_en[5].q),
// to register interface (read)
.qs (wkup_detector_en_5_qs)
@@ -12793,20 +12745,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[6].q ),
+ .q (reg2hw.wkup_detector_en[6].q),
// to register interface (read)
.qs (wkup_detector_en_6_qs)
@@ -12820,20 +12772,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[7].q ),
+ .q (reg2hw.wkup_detector_en[7].q),
// to register interface (read)
.qs (wkup_detector_en_7_qs)
@@ -12850,20 +12802,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_0_mode_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_0_mode_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_0_mode_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[0].mode.q ),
+ .q (reg2hw.wkup_detector[0].mode.q),
// to register interface (read)
.qs (wkup_detector_0_mode_0_qs)
@@ -12876,20 +12828,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_0_filter_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_0_filter_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_0_filter_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[0].filter.q ),
+ .q (reg2hw.wkup_detector[0].filter.q),
// to register interface (read)
.qs (wkup_detector_0_filter_0_qs)
@@ -12902,20 +12854,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_0_miodio_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_0_miodio_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_0_miodio_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[0].miodio.q ),
+ .q (reg2hw.wkup_detector[0].miodio.q),
// to register interface (read)
.qs (wkup_detector_0_miodio_0_qs)
@@ -12931,20 +12883,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_1_mode_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_1_mode_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_1_mode_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[1].mode.q ),
+ .q (reg2hw.wkup_detector[1].mode.q),
// to register interface (read)
.qs (wkup_detector_1_mode_1_qs)
@@ -12957,20 +12909,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_1_filter_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_1_filter_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_1_filter_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[1].filter.q ),
+ .q (reg2hw.wkup_detector[1].filter.q),
// to register interface (read)
.qs (wkup_detector_1_filter_1_qs)
@@ -12983,20 +12935,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_1_miodio_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_1_miodio_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_1_miodio_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[1].miodio.q ),
+ .q (reg2hw.wkup_detector[1].miodio.q),
// to register interface (read)
.qs (wkup_detector_1_miodio_1_qs)
@@ -13012,20 +12964,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_2_mode_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_2_mode_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_2_mode_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[2].mode.q ),
+ .q (reg2hw.wkup_detector[2].mode.q),
// to register interface (read)
.qs (wkup_detector_2_mode_2_qs)
@@ -13038,20 +12990,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_2_filter_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_2_filter_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_2_filter_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[2].filter.q ),
+ .q (reg2hw.wkup_detector[2].filter.q),
// to register interface (read)
.qs (wkup_detector_2_filter_2_qs)
@@ -13064,20 +13016,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_2_miodio_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_2_miodio_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_2_miodio_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[2].miodio.q ),
+ .q (reg2hw.wkup_detector[2].miodio.q),
// to register interface (read)
.qs (wkup_detector_2_miodio_2_qs)
@@ -13093,20 +13045,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_3_mode_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_3_mode_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_3_mode_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[3].mode.q ),
+ .q (reg2hw.wkup_detector[3].mode.q),
// to register interface (read)
.qs (wkup_detector_3_mode_3_qs)
@@ -13119,20 +13071,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_3_filter_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_3_filter_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_3_filter_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[3].filter.q ),
+ .q (reg2hw.wkup_detector[3].filter.q),
// to register interface (read)
.qs (wkup_detector_3_filter_3_qs)
@@ -13145,20 +13097,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_3_miodio_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_3_miodio_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_3_miodio_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[3].miodio.q ),
+ .q (reg2hw.wkup_detector[3].miodio.q),
// to register interface (read)
.qs (wkup_detector_3_miodio_3_qs)
@@ -13174,20 +13126,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_4_mode_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_4_mode_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_4_mode_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[4].mode.q ),
+ .q (reg2hw.wkup_detector[4].mode.q),
// to register interface (read)
.qs (wkup_detector_4_mode_4_qs)
@@ -13200,20 +13152,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_4_filter_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_4_filter_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_4_filter_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[4].filter.q ),
+ .q (reg2hw.wkup_detector[4].filter.q),
// to register interface (read)
.qs (wkup_detector_4_filter_4_qs)
@@ -13226,20 +13178,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_4_miodio_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_4_miodio_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_4_miodio_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[4].miodio.q ),
+ .q (reg2hw.wkup_detector[4].miodio.q),
// to register interface (read)
.qs (wkup_detector_4_miodio_4_qs)
@@ -13255,20 +13207,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_5_mode_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_5_mode_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_5_mode_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[5].mode.q ),
+ .q (reg2hw.wkup_detector[5].mode.q),
// to register interface (read)
.qs (wkup_detector_5_mode_5_qs)
@@ -13281,20 +13233,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_5_filter_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_5_filter_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_5_filter_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[5].filter.q ),
+ .q (reg2hw.wkup_detector[5].filter.q),
// to register interface (read)
.qs (wkup_detector_5_filter_5_qs)
@@ -13307,20 +13259,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_5_miodio_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_5_miodio_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_5_miodio_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[5].miodio.q ),
+ .q (reg2hw.wkup_detector[5].miodio.q),
// to register interface (read)
.qs (wkup_detector_5_miodio_5_qs)
@@ -13336,20 +13288,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_6_mode_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_6_mode_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_6_mode_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[6].mode.q ),
+ .q (reg2hw.wkup_detector[6].mode.q),
// to register interface (read)
.qs (wkup_detector_6_mode_6_qs)
@@ -13362,20 +13314,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_6_filter_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_6_filter_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_6_filter_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[6].filter.q ),
+ .q (reg2hw.wkup_detector[6].filter.q),
// to register interface (read)
.qs (wkup_detector_6_filter_6_qs)
@@ -13388,20 +13340,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_6_miodio_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_6_miodio_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_6_miodio_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[6].miodio.q ),
+ .q (reg2hw.wkup_detector[6].miodio.q),
// to register interface (read)
.qs (wkup_detector_6_miodio_6_qs)
@@ -13417,20 +13369,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_7_mode_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_7_mode_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_7_mode_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[7].mode.q ),
+ .q (reg2hw.wkup_detector[7].mode.q),
// to register interface (read)
.qs (wkup_detector_7_mode_7_qs)
@@ -13443,20 +13395,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_7_filter_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_7_filter_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_7_filter_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[7].filter.q ),
+ .q (reg2hw.wkup_detector[7].filter.q),
// to register interface (read)
.qs (wkup_detector_7_filter_7_qs)
@@ -13469,20 +13421,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_7_miodio_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_7_miodio_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_7_miodio_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[7].miodio.q ),
+ .q (reg2hw.wkup_detector[7].miodio.q),
// to register interface (read)
.qs (wkup_detector_7_miodio_7_qs)
@@ -13499,20 +13451,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_cnt_th_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[0].q ),
+ .q (reg2hw.wkup_detector_cnt_th[0].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_0_qs)
@@ -13526,20 +13478,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_cnt_th_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[1].q ),
+ .q (reg2hw.wkup_detector_cnt_th[1].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_1_qs)
@@ -13553,20 +13505,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_cnt_th_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[2].q ),
+ .q (reg2hw.wkup_detector_cnt_th[2].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_2_qs)
@@ -13580,20 +13532,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_cnt_th_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[3].q ),
+ .q (reg2hw.wkup_detector_cnt_th[3].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_3_qs)
@@ -13607,20 +13559,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_cnt_th_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[4].q ),
+ .q (reg2hw.wkup_detector_cnt_th[4].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_4_qs)
@@ -13634,20 +13586,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_cnt_th_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[5].q ),
+ .q (reg2hw.wkup_detector_cnt_th[5].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_5_qs)
@@ -13661,20 +13613,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_cnt_th_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[6].q ),
+ .q (reg2hw.wkup_detector_cnt_th[6].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_6_qs)
@@ -13688,20 +13640,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_cnt_th_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[7].q ),
+ .q (reg2hw.wkup_detector_cnt_th[7].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_7_qs)
@@ -13717,20 +13669,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_padsel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[0].q ),
+ .q (reg2hw.wkup_detector_padsel[0].q),
// to register interface (read)
.qs (wkup_detector_padsel_0_qs)
@@ -13744,20 +13696,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_padsel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[1].q ),
+ .q (reg2hw.wkup_detector_padsel[1].q),
// to register interface (read)
.qs (wkup_detector_padsel_1_qs)
@@ -13771,20 +13723,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_padsel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[2].q ),
+ .q (reg2hw.wkup_detector_padsel[2].q),
// to register interface (read)
.qs (wkup_detector_padsel_2_qs)
@@ -13798,20 +13750,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_padsel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[3].q ),
+ .q (reg2hw.wkup_detector_padsel[3].q),
// to register interface (read)
.qs (wkup_detector_padsel_3_qs)
@@ -13825,20 +13777,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_padsel_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[4].q ),
+ .q (reg2hw.wkup_detector_padsel[4].q),
// to register interface (read)
.qs (wkup_detector_padsel_4_qs)
@@ -13852,20 +13804,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_padsel_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[5].q ),
+ .q (reg2hw.wkup_detector_padsel[5].q),
// to register interface (read)
.qs (wkup_detector_padsel_5_qs)
@@ -13879,20 +13831,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_padsel_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[6].q ),
+ .q (reg2hw.wkup_detector_padsel[6].q),
// to register interface (read)
.qs (wkup_detector_padsel_6_qs)
@@ -13906,20 +13858,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_padsel_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[7].q ),
+ .q (reg2hw.wkup_detector_padsel[7].q),
// to register interface (read)
.qs (wkup_detector_padsel_7_qs)
@@ -13940,7 +13892,7 @@
.d (hw2reg.wkup_cause[0].d),
.qre (),
.qe (reg2hw.wkup_cause[0].qe),
- .q (reg2hw.wkup_cause[0].q ),
+ .q (reg2hw.wkup_cause[0].q),
.qs (wkup_cause_cause_0_qs)
);
@@ -13955,7 +13907,7 @@
.d (hw2reg.wkup_cause[1].d),
.qre (),
.qe (reg2hw.wkup_cause[1].qe),
- .q (reg2hw.wkup_cause[1].q ),
+ .q (reg2hw.wkup_cause[1].q),
.qs (wkup_cause_cause_1_qs)
);
@@ -13970,7 +13922,7 @@
.d (hw2reg.wkup_cause[2].d),
.qre (),
.qe (reg2hw.wkup_cause[2].qe),
- .q (reg2hw.wkup_cause[2].q ),
+ .q (reg2hw.wkup_cause[2].q),
.qs (wkup_cause_cause_2_qs)
);
@@ -13985,7 +13937,7 @@
.d (hw2reg.wkup_cause[3].d),
.qre (),
.qe (reg2hw.wkup_cause[3].qe),
- .q (reg2hw.wkup_cause[3].q ),
+ .q (reg2hw.wkup_cause[3].q),
.qs (wkup_cause_cause_3_qs)
);
@@ -14000,7 +13952,7 @@
.d (hw2reg.wkup_cause[4].d),
.qre (),
.qe (reg2hw.wkup_cause[4].qe),
- .q (reg2hw.wkup_cause[4].q ),
+ .q (reg2hw.wkup_cause[4].q),
.qs (wkup_cause_cause_4_qs)
);
@@ -14015,7 +13967,7 @@
.d (hw2reg.wkup_cause[5].d),
.qre (),
.qe (reg2hw.wkup_cause[5].qe),
- .q (reg2hw.wkup_cause[5].q ),
+ .q (reg2hw.wkup_cause[5].q),
.qs (wkup_cause_cause_5_qs)
);
@@ -14030,7 +13982,7 @@
.d (hw2reg.wkup_cause[6].d),
.qre (),
.qe (reg2hw.wkup_cause[6].qe),
- .q (reg2hw.wkup_cause[6].q ),
+ .q (reg2hw.wkup_cause[6].q),
.qs (wkup_cause_cause_6_qs)
);
@@ -14045,7 +13997,7 @@
.d (hw2reg.wkup_cause[7].d),
.qre (),
.qe (reg2hw.wkup_cause[7].qe),
- .q (reg2hw.wkup_cause[7].q ),
+ .q (reg2hw.wkup_cause[7].q),
.qs (wkup_cause_cause_7_qs)
);
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv b/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv
index fb90957..bdfe9f0 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv
@@ -173,8 +173,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
@@ -182,11 +182,11 @@
// from internal hardware
.de (hw2reg.intr_state.de),
- .d (hw2reg.intr_state.d ),
+ .d (hw2reg.intr_state.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.q ),
+ .q (reg2hw.intr_state.q),
// to register interface (read)
.qs (intr_state_qs)
@@ -200,8 +200,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
@@ -209,11 +209,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.q ),
+ .q (reg2hw.intr_enable.q),
// to register interface (read)
.qs (intr_enable_qs)
@@ -231,7 +231,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.qe),
- .q (reg2hw.intr_test.q ),
+ .q (reg2hw.intr_test.q),
.qs ()
);
@@ -260,20 +260,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_low_power_hint (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_low_power_hint_we & ctrl_cfg_regwen_qs),
.wd (control_low_power_hint_wd),
// from internal hardware
.de (hw2reg.control.low_power_hint.de),
- .d (hw2reg.control.low_power_hint.d ),
+ .d (hw2reg.control.low_power_hint.d),
// to internal hardware
.qe (),
- .q (reg2hw.control.low_power_hint.q ),
+ .q (reg2hw.control.low_power_hint.q),
// to register interface (read)
.qs (control_low_power_hint_qs)
@@ -286,20 +286,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_core_clk_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_core_clk_en_we & ctrl_cfg_regwen_qs),
.wd (control_core_clk_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.core_clk_en.q ),
+ .q (reg2hw.control.core_clk_en.q),
// to register interface (read)
.qs (control_core_clk_en_qs)
@@ -312,20 +312,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_io_clk_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_io_clk_en_we & ctrl_cfg_regwen_qs),
.wd (control_io_clk_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.io_clk_en.q ),
+ .q (reg2hw.control.io_clk_en.q),
// to register interface (read)
.qs (control_io_clk_en_qs)
@@ -338,20 +338,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_usb_clk_en_lp (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_usb_clk_en_lp_we & ctrl_cfg_regwen_qs),
.wd (control_usb_clk_en_lp_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.usb_clk_en_lp.q ),
+ .q (reg2hw.control.usb_clk_en_lp.q),
// to register interface (read)
.qs (control_usb_clk_en_lp_qs)
@@ -364,20 +364,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_control_usb_clk_en_active (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_usb_clk_en_active_we & ctrl_cfg_regwen_qs),
.wd (control_usb_clk_en_active_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.usb_clk_en_active.q ),
+ .q (reg2hw.control.usb_clk_en_active.q),
// to register interface (read)
.qs (control_usb_clk_en_active_qs)
@@ -390,20 +390,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_control_main_pd_n (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_main_pd_n_we & ctrl_cfg_regwen_qs),
.wd (control_main_pd_n_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.main_pd_n.q ),
+ .q (reg2hw.control.main_pd_n.q),
// to register interface (read)
.qs (control_main_pd_n_qs)
@@ -417,8 +417,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_cdc_sync (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg_cdc_sync_we),
@@ -426,11 +426,11 @@
// from internal hardware
.de (hw2reg.cfg_cdc_sync.de),
- .d (hw2reg.cfg_cdc_sync.d ),
+ .d (hw2reg.cfg_cdc_sync.d),
// to internal hardware
.qe (reg2hw.cfg_cdc_sync.qe),
- .q (reg2hw.cfg_cdc_sync.q ),
+ .q (reg2hw.cfg_cdc_sync.q),
// to register interface (read)
.qs (cfg_cdc_sync_qs)
@@ -444,8 +444,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wakeup_en_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wakeup_en_regwen_we),
@@ -453,7 +453,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -473,20 +473,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wakeup_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wakeup_en_we & wakeup_en_regwen_qs),
.wd (wakeup_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wakeup_en[0].q ),
+ .q (reg2hw.wakeup_en[0].q),
// to register interface (read)
.qs (wakeup_en_qs)
@@ -502,15 +502,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_wake_status (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.wake_status[0].de),
- .d (hw2reg.wake_status[0].d ),
+ .d (hw2reg.wake_status[0].d),
// to internal hardware
.qe (),
@@ -528,8 +529,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_reset_en_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_en_regwen_we),
@@ -537,7 +538,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -557,20 +558,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_reset_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (reset_en_we & reset_en_regwen_qs),
.wd (reset_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.reset_en[0].q ),
+ .q (reg2hw.reset_en[0].q),
// to register interface (read)
.qs (reset_en_qs)
@@ -586,15 +587,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_reset_status (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.reset_status[0].de),
- .d (hw2reg.reset_status[0].d ),
+ .d (hw2reg.reset_status[0].d),
// to internal hardware
.qe (),
@@ -612,8 +614,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wake_info_capture_dis (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wake_info_capture_dis_we),
@@ -621,11 +623,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wake_info_capture_dis.q ),
+ .q (reg2hw.wake_info_capture_dis.q),
// to register interface (read)
.qs (wake_info_capture_dis_qs)
@@ -644,7 +646,7 @@
.d (hw2reg.wake_info.reasons.d),
.qre (),
.qe (reg2hw.wake_info.reasons.qe),
- .q (reg2hw.wake_info.reasons.q ),
+ .q (reg2hw.wake_info.reasons.q),
.qs (wake_info_reasons_qs)
);
@@ -659,7 +661,7 @@
.d (hw2reg.wake_info.fall_through.d),
.qre (),
.qe (reg2hw.wake_info.fall_through.qe),
- .q (reg2hw.wake_info.fall_through.q ),
+ .q (reg2hw.wake_info.fall_through.q),
.qs (wake_info_fall_through_qs)
);
@@ -674,7 +676,7 @@
.d (hw2reg.wake_info.abort.d),
.qre (),
.qe (reg2hw.wake_info.abort.qe),
- .q (reg2hw.wake_info.abort.q ),
+ .q (reg2hw.wake_info.abort.q),
.qs (wake_info_abort_qs)
);
diff --git a/hw/ip/rom_ctrl/rtl/rom_ctrl_regs_reg_top.sv b/hw/ip/rom_ctrl/rtl/rom_ctrl_regs_reg_top.sv
index fb0781d..453c601 100644
--- a/hw/ip/rom_ctrl/rtl/rom_ctrl_regs_reg_top.sv
+++ b/hw/ip/rom_ctrl/rtl/rom_ctrl_regs_reg_top.sv
@@ -137,7 +137,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.qe),
- .q (reg2hw.alert_test.q ),
+ .q (reg2hw.alert_test.q),
.qs ()
);
@@ -150,15 +150,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_fatal_alert_cause_checker_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.fatal_alert_cause.checker_error.de),
- .d (hw2reg.fatal_alert_cause.checker_error.d ),
+ .d (hw2reg.fatal_alert_cause.checker_error.d),
// to internal hardware
.qe (),
@@ -175,15 +176,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_fatal_alert_cause_integrity_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.fatal_alert_cause.integrity_error.de),
- .d (hw2reg.fatal_alert_cause.integrity_error.d ),
+ .d (hw2reg.fatal_alert_cause.integrity_error.d),
// to internal hardware
.qe (),
@@ -203,19 +205,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_digest_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.digest[0].de),
- .d (hw2reg.digest[0].d ),
+ .d (hw2reg.digest[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.digest[0].q ),
+ .q (reg2hw.digest[0].q),
// to register interface (read)
.qs (digest_0_qs)
@@ -229,19 +232,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_digest_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.digest[1].de),
- .d (hw2reg.digest[1].d ),
+ .d (hw2reg.digest[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.digest[1].q ),
+ .q (reg2hw.digest[1].q),
// to register interface (read)
.qs (digest_1_qs)
@@ -255,19 +259,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_digest_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.digest[2].de),
- .d (hw2reg.digest[2].d ),
+ .d (hw2reg.digest[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.digest[2].q ),
+ .q (reg2hw.digest[2].q),
// to register interface (read)
.qs (digest_2_qs)
@@ -281,19 +286,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_digest_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.digest[3].de),
- .d (hw2reg.digest[3].d ),
+ .d (hw2reg.digest[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.digest[3].q ),
+ .q (reg2hw.digest[3].q),
// to register interface (read)
.qs (digest_3_qs)
@@ -307,19 +313,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_digest_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.digest[4].de),
- .d (hw2reg.digest[4].d ),
+ .d (hw2reg.digest[4].d),
// to internal hardware
.qe (),
- .q (reg2hw.digest[4].q ),
+ .q (reg2hw.digest[4].q),
// to register interface (read)
.qs (digest_4_qs)
@@ -333,19 +340,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_digest_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.digest[5].de),
- .d (hw2reg.digest[5].d ),
+ .d (hw2reg.digest[5].d),
// to internal hardware
.qe (),
- .q (reg2hw.digest[5].q ),
+ .q (reg2hw.digest[5].q),
// to register interface (read)
.qs (digest_5_qs)
@@ -359,19 +367,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_digest_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.digest[6].de),
- .d (hw2reg.digest[6].d ),
+ .d (hw2reg.digest[6].d),
// to internal hardware
.qe (),
- .q (reg2hw.digest[6].q ),
+ .q (reg2hw.digest[6].q),
// to register interface (read)
.qs (digest_6_qs)
@@ -385,19 +394,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_digest_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.digest[7].de),
- .d (hw2reg.digest[7].d ),
+ .d (hw2reg.digest[7].d),
// to internal hardware
.qe (),
- .q (reg2hw.digest[7].q ),
+ .q (reg2hw.digest[7].q),
// to register interface (read)
.qs (digest_7_qs)
@@ -413,19 +423,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_exp_digest_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.exp_digest[0].de),
- .d (hw2reg.exp_digest[0].d ),
+ .d (hw2reg.exp_digest[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.exp_digest[0].q ),
+ .q (reg2hw.exp_digest[0].q),
// to register interface (read)
.qs (exp_digest_0_qs)
@@ -439,19 +450,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_exp_digest_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.exp_digest[1].de),
- .d (hw2reg.exp_digest[1].d ),
+ .d (hw2reg.exp_digest[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.exp_digest[1].q ),
+ .q (reg2hw.exp_digest[1].q),
// to register interface (read)
.qs (exp_digest_1_qs)
@@ -465,19 +477,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_exp_digest_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.exp_digest[2].de),
- .d (hw2reg.exp_digest[2].d ),
+ .d (hw2reg.exp_digest[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.exp_digest[2].q ),
+ .q (reg2hw.exp_digest[2].q),
// to register interface (read)
.qs (exp_digest_2_qs)
@@ -491,19 +504,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_exp_digest_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.exp_digest[3].de),
- .d (hw2reg.exp_digest[3].d ),
+ .d (hw2reg.exp_digest[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.exp_digest[3].q ),
+ .q (reg2hw.exp_digest[3].q),
// to register interface (read)
.qs (exp_digest_3_qs)
@@ -517,19 +531,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_exp_digest_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.exp_digest[4].de),
- .d (hw2reg.exp_digest[4].d ),
+ .d (hw2reg.exp_digest[4].d),
// to internal hardware
.qe (),
- .q (reg2hw.exp_digest[4].q ),
+ .q (reg2hw.exp_digest[4].q),
// to register interface (read)
.qs (exp_digest_4_qs)
@@ -543,19 +558,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_exp_digest_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.exp_digest[5].de),
- .d (hw2reg.exp_digest[5].d ),
+ .d (hw2reg.exp_digest[5].d),
// to internal hardware
.qe (),
- .q (reg2hw.exp_digest[5].q ),
+ .q (reg2hw.exp_digest[5].q),
// to register interface (read)
.qs (exp_digest_5_qs)
@@ -569,19 +585,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_exp_digest_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.exp_digest[6].de),
- .d (hw2reg.exp_digest[6].d ),
+ .d (hw2reg.exp_digest[6].d),
// to internal hardware
.qe (),
- .q (reg2hw.exp_digest[6].q ),
+ .q (reg2hw.exp_digest[6].q),
// to register interface (read)
.qs (exp_digest_6_qs)
@@ -595,19 +612,20 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_exp_digest_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.exp_digest[7].de),
- .d (hw2reg.exp_digest[7].d ),
+ .d (hw2reg.exp_digest[7].d),
// to internal hardware
.qe (),
- .q (reg2hw.exp_digest[7].q ),
+ .q (reg2hw.exp_digest[7].q),
// to register interface (read)
.qs (exp_digest_7_qs)
diff --git a/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv b/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv
index 9c5df0f..78d7762 100644
--- a/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv
+++ b/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv
@@ -150,8 +150,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h1)
) u_reset_info_por (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_info_por_we),
@@ -159,7 +159,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -176,8 +176,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_reset_info_low_power_exit (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_info_low_power_exit_we),
@@ -185,7 +185,7 @@
// from internal hardware
.de (hw2reg.reset_info.low_power_exit.de),
- .d (hw2reg.reset_info.low_power_exit.d ),
+ .d (hw2reg.reset_info.low_power_exit.d),
// to internal hardware
.qe (),
@@ -202,8 +202,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_reset_info_ndm_reset (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_info_ndm_reset_we),
@@ -211,7 +211,7 @@
// from internal hardware
.de (hw2reg.reset_info.ndm_reset.de),
- .d (hw2reg.reset_info.ndm_reset.d ),
+ .d (hw2reg.reset_info.ndm_reset.d),
// to internal hardware
.qe (),
@@ -228,8 +228,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_reset_info_hw_req (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_info_hw_req_we),
@@ -237,11 +237,11 @@
// from internal hardware
.de (hw2reg.reset_info.hw_req.de),
- .d (hw2reg.reset_info.hw_req.d ),
+ .d (hw2reg.reset_info.hw_req.d),
// to internal hardware
.qe (),
- .q (reg2hw.reset_info.hw_req.q ),
+ .q (reg2hw.reset_info.hw_req.q),
// to register interface (read)
.qs (reset_info_hw_req_qs)
@@ -256,8 +256,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_info_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_info_ctrl_en_we),
@@ -265,11 +265,11 @@
// from internal hardware
.de (hw2reg.alert_info_ctrl.en.de),
- .d (hw2reg.alert_info_ctrl.en.d ),
+ .d (hw2reg.alert_info_ctrl.en.d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_info_ctrl.en.q ),
+ .q (reg2hw.alert_info_ctrl.en.q),
// to register interface (read)
.qs (alert_info_ctrl_en_qs)
@@ -282,8 +282,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_alert_info_ctrl_index (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_info_ctrl_index_we),
@@ -291,11 +291,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_info_ctrl.index.q ),
+ .q (reg2hw.alert_info_ctrl.index.q),
// to register interface (read)
.qs (alert_info_ctrl_index_qs)
@@ -344,8 +344,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_sw_rst_regen_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_rst_regen_en_0_we),
@@ -353,11 +353,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[0].q ),
+ .q (reg2hw.sw_rst_regen[0].q),
// to register interface (read)
.qs (sw_rst_regen_en_0_qs)
@@ -370,8 +370,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_sw_rst_regen_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_rst_regen_en_1_we),
@@ -379,11 +379,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[1].q ),
+ .q (reg2hw.sw_rst_regen[1].q),
// to register interface (read)
.qs (sw_rst_regen_en_1_qs)
@@ -405,7 +405,7 @@
.d (hw2reg.sw_rst_ctrl_n[0].d),
.qre (),
.qe (reg2hw.sw_rst_ctrl_n[0].qe),
- .q (reg2hw.sw_rst_ctrl_n[0].q ),
+ .q (reg2hw.sw_rst_ctrl_n[0].q),
.qs (sw_rst_ctrl_n_val_0_qs)
);
@@ -420,7 +420,7 @@
.d (hw2reg.sw_rst_ctrl_n[1].d),
.qre (),
.qe (reg2hw.sw_rst_ctrl_n[1].qe),
- .q (reg2hw.sw_rst_ctrl_n[1].q ),
+ .q (reg2hw.sw_rst_ctrl_n[1].q),
.qs (sw_rst_ctrl_n_val_1_qs)
);
diff --git a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
index ea99b23..a6a1900 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
@@ -446,15 +446,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[0].de),
- .d (hw2reg.ip[0].d ),
+ .d (hw2reg.ip[0].d),
// to internal hardware
.qe (),
@@ -471,15 +472,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[1].de),
- .d (hw2reg.ip[1].d ),
+ .d (hw2reg.ip[1].d),
// to internal hardware
.qe (),
@@ -496,15 +498,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[2].de),
- .d (hw2reg.ip[2].d ),
+ .d (hw2reg.ip[2].d),
// to internal hardware
.qe (),
@@ -521,15 +524,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[3].de),
- .d (hw2reg.ip[3].d ),
+ .d (hw2reg.ip[3].d),
// to internal hardware
.qe (),
@@ -546,15 +550,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[4].de),
- .d (hw2reg.ip[4].d ),
+ .d (hw2reg.ip[4].d),
// to internal hardware
.qe (),
@@ -571,15 +576,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[5].de),
- .d (hw2reg.ip[5].d ),
+ .d (hw2reg.ip[5].d),
// to internal hardware
.qe (),
@@ -596,15 +602,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[6].de),
- .d (hw2reg.ip[6].d ),
+ .d (hw2reg.ip[6].d),
// to internal hardware
.qe (),
@@ -621,15 +628,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[7].de),
- .d (hw2reg.ip[7].d ),
+ .d (hw2reg.ip[7].d),
// to internal hardware
.qe (),
@@ -646,15 +654,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[8].de),
- .d (hw2reg.ip[8].d ),
+ .d (hw2reg.ip[8].d),
// to internal hardware
.qe (),
@@ -671,15 +680,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[9].de),
- .d (hw2reg.ip[9].d ),
+ .d (hw2reg.ip[9].d),
// to internal hardware
.qe (),
@@ -696,15 +706,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[10].de),
- .d (hw2reg.ip[10].d ),
+ .d (hw2reg.ip[10].d),
// to internal hardware
.qe (),
@@ -721,15 +732,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[11].de),
- .d (hw2reg.ip[11].d ),
+ .d (hw2reg.ip[11].d),
// to internal hardware
.qe (),
@@ -746,15 +758,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[12].de),
- .d (hw2reg.ip[12].d ),
+ .d (hw2reg.ip[12].d),
// to internal hardware
.qe (),
@@ -771,15 +784,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[13].de),
- .d (hw2reg.ip[13].d ),
+ .d (hw2reg.ip[13].d),
// to internal hardware
.qe (),
@@ -796,15 +810,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[14].de),
- .d (hw2reg.ip[14].d ),
+ .d (hw2reg.ip[14].d),
// to internal hardware
.qe (),
@@ -821,15 +836,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[15].de),
- .d (hw2reg.ip[15].d ),
+ .d (hw2reg.ip[15].d),
// to internal hardware
.qe (),
@@ -846,15 +862,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[16].de),
- .d (hw2reg.ip[16].d ),
+ .d (hw2reg.ip[16].d),
// to internal hardware
.qe (),
@@ -871,15 +888,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[17].de),
- .d (hw2reg.ip[17].d ),
+ .d (hw2reg.ip[17].d),
// to internal hardware
.qe (),
@@ -896,15 +914,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[18].de),
- .d (hw2reg.ip[18].d ),
+ .d (hw2reg.ip[18].d),
// to internal hardware
.qe (),
@@ -921,15 +940,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[19].de),
- .d (hw2reg.ip[19].d ),
+ .d (hw2reg.ip[19].d),
// to internal hardware
.qe (),
@@ -946,15 +966,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[20].de),
- .d (hw2reg.ip[20].d ),
+ .d (hw2reg.ip[20].d),
// to internal hardware
.qe (),
@@ -971,15 +992,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[21].de),
- .d (hw2reg.ip[21].d ),
+ .d (hw2reg.ip[21].d),
// to internal hardware
.qe (),
@@ -996,15 +1018,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[22].de),
- .d (hw2reg.ip[22].d ),
+ .d (hw2reg.ip[22].d),
// to internal hardware
.qe (),
@@ -1021,15 +1044,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[23].de),
- .d (hw2reg.ip[23].d ),
+ .d (hw2reg.ip[23].d),
// to internal hardware
.qe (),
@@ -1046,15 +1070,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[24].de),
- .d (hw2reg.ip[24].d ),
+ .d (hw2reg.ip[24].d),
// to internal hardware
.qe (),
@@ -1071,15 +1096,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[25].de),
- .d (hw2reg.ip[25].d ),
+ .d (hw2reg.ip[25].d),
// to internal hardware
.qe (),
@@ -1096,15 +1122,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[26].de),
- .d (hw2reg.ip[26].d ),
+ .d (hw2reg.ip[26].d),
// to internal hardware
.qe (),
@@ -1121,15 +1148,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[27].de),
- .d (hw2reg.ip[27].d ),
+ .d (hw2reg.ip[27].d),
// to internal hardware
.qe (),
@@ -1146,15 +1174,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[28].de),
- .d (hw2reg.ip[28].d ),
+ .d (hw2reg.ip[28].d),
// to internal hardware
.qe (),
@@ -1171,15 +1200,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[29].de),
- .d (hw2reg.ip[29].d ),
+ .d (hw2reg.ip[29].d),
// to internal hardware
.qe (),
@@ -1196,15 +1226,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[30].de),
- .d (hw2reg.ip[30].d ),
+ .d (hw2reg.ip[30].d),
// to internal hardware
.qe (),
@@ -1221,15 +1252,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_p_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[31].de),
- .d (hw2reg.ip[31].d ),
+ .d (hw2reg.ip[31].d),
// to internal hardware
.qe (),
@@ -1251,8 +1283,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_0_we),
@@ -1260,11 +1292,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[0].q ),
+ .q (reg2hw.le[0].q),
// to register interface (read)
.qs (le_le_0_qs)
@@ -1277,8 +1309,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_1_we),
@@ -1286,11 +1318,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[1].q ),
+ .q (reg2hw.le[1].q),
// to register interface (read)
.qs (le_le_1_qs)
@@ -1303,8 +1335,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_2_we),
@@ -1312,11 +1344,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[2].q ),
+ .q (reg2hw.le[2].q),
// to register interface (read)
.qs (le_le_2_qs)
@@ -1329,8 +1361,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_3_we),
@@ -1338,11 +1370,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[3].q ),
+ .q (reg2hw.le[3].q),
// to register interface (read)
.qs (le_le_3_qs)
@@ -1355,8 +1387,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_4_we),
@@ -1364,11 +1396,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[4].q ),
+ .q (reg2hw.le[4].q),
// to register interface (read)
.qs (le_le_4_qs)
@@ -1381,8 +1413,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_5_we),
@@ -1390,11 +1422,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[5].q ),
+ .q (reg2hw.le[5].q),
// to register interface (read)
.qs (le_le_5_qs)
@@ -1407,8 +1439,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_6_we),
@@ -1416,11 +1448,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[6].q ),
+ .q (reg2hw.le[6].q),
// to register interface (read)
.qs (le_le_6_qs)
@@ -1433,8 +1465,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_7_we),
@@ -1442,11 +1474,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[7].q ),
+ .q (reg2hw.le[7].q),
// to register interface (read)
.qs (le_le_7_qs)
@@ -1459,8 +1491,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_8_we),
@@ -1468,11 +1500,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[8].q ),
+ .q (reg2hw.le[8].q),
// to register interface (read)
.qs (le_le_8_qs)
@@ -1485,8 +1517,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_9_we),
@@ -1494,11 +1526,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[9].q ),
+ .q (reg2hw.le[9].q),
// to register interface (read)
.qs (le_le_9_qs)
@@ -1511,8 +1543,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_10_we),
@@ -1520,11 +1552,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[10].q ),
+ .q (reg2hw.le[10].q),
// to register interface (read)
.qs (le_le_10_qs)
@@ -1537,8 +1569,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_11_we),
@@ -1546,11 +1578,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[11].q ),
+ .q (reg2hw.le[11].q),
// to register interface (read)
.qs (le_le_11_qs)
@@ -1563,8 +1595,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_12_we),
@@ -1572,11 +1604,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[12].q ),
+ .q (reg2hw.le[12].q),
// to register interface (read)
.qs (le_le_12_qs)
@@ -1589,8 +1621,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_13_we),
@@ -1598,11 +1630,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[13].q ),
+ .q (reg2hw.le[13].q),
// to register interface (read)
.qs (le_le_13_qs)
@@ -1615,8 +1647,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_14_we),
@@ -1624,11 +1656,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[14].q ),
+ .q (reg2hw.le[14].q),
// to register interface (read)
.qs (le_le_14_qs)
@@ -1641,8 +1673,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_15_we),
@@ -1650,11 +1682,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[15].q ),
+ .q (reg2hw.le[15].q),
// to register interface (read)
.qs (le_le_15_qs)
@@ -1667,8 +1699,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_16_we),
@@ -1676,11 +1708,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[16].q ),
+ .q (reg2hw.le[16].q),
// to register interface (read)
.qs (le_le_16_qs)
@@ -1693,8 +1725,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_17_we),
@@ -1702,11 +1734,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[17].q ),
+ .q (reg2hw.le[17].q),
// to register interface (read)
.qs (le_le_17_qs)
@@ -1719,8 +1751,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_18_we),
@@ -1728,11 +1760,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[18].q ),
+ .q (reg2hw.le[18].q),
// to register interface (read)
.qs (le_le_18_qs)
@@ -1745,8 +1777,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_19_we),
@@ -1754,11 +1786,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[19].q ),
+ .q (reg2hw.le[19].q),
// to register interface (read)
.qs (le_le_19_qs)
@@ -1771,8 +1803,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_20_we),
@@ -1780,11 +1812,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[20].q ),
+ .q (reg2hw.le[20].q),
// to register interface (read)
.qs (le_le_20_qs)
@@ -1797,8 +1829,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_21_we),
@@ -1806,11 +1838,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[21].q ),
+ .q (reg2hw.le[21].q),
// to register interface (read)
.qs (le_le_21_qs)
@@ -1823,8 +1855,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_22_we),
@@ -1832,11 +1864,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[22].q ),
+ .q (reg2hw.le[22].q),
// to register interface (read)
.qs (le_le_22_qs)
@@ -1849,8 +1881,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_23_we),
@@ -1858,11 +1890,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[23].q ),
+ .q (reg2hw.le[23].q),
// to register interface (read)
.qs (le_le_23_qs)
@@ -1875,8 +1907,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_24_we),
@@ -1884,11 +1916,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[24].q ),
+ .q (reg2hw.le[24].q),
// to register interface (read)
.qs (le_le_24_qs)
@@ -1901,8 +1933,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_25_we),
@@ -1910,11 +1942,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[25].q ),
+ .q (reg2hw.le[25].q),
// to register interface (read)
.qs (le_le_25_qs)
@@ -1927,8 +1959,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_26_we),
@@ -1936,11 +1968,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[26].q ),
+ .q (reg2hw.le[26].q),
// to register interface (read)
.qs (le_le_26_qs)
@@ -1953,8 +1985,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_27_we),
@@ -1962,11 +1994,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[27].q ),
+ .q (reg2hw.le[27].q),
// to register interface (read)
.qs (le_le_27_qs)
@@ -1979,8 +2011,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_28_we),
@@ -1988,11 +2020,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[28].q ),
+ .q (reg2hw.le[28].q),
// to register interface (read)
.qs (le_le_28_qs)
@@ -2005,8 +2037,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_29_we),
@@ -2014,11 +2046,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[29].q ),
+ .q (reg2hw.le[29].q),
// to register interface (read)
.qs (le_le_29_qs)
@@ -2031,8 +2063,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_30_we),
@@ -2040,11 +2072,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[30].q ),
+ .q (reg2hw.le[30].q),
// to register interface (read)
.qs (le_le_30_qs)
@@ -2057,8 +2089,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_le_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_le_31_we),
@@ -2066,11 +2098,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[31].q ),
+ .q (reg2hw.le[31].q),
// to register interface (read)
.qs (le_le_31_qs)
@@ -2085,8 +2117,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio0_we),
@@ -2094,11 +2126,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio0.q ),
+ .q (reg2hw.prio0.q),
// to register interface (read)
.qs (prio0_qs)
@@ -2112,8 +2144,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio1_we),
@@ -2121,11 +2153,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio1.q ),
+ .q (reg2hw.prio1.q),
// to register interface (read)
.qs (prio1_qs)
@@ -2139,8 +2171,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio2_we),
@@ -2148,11 +2180,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio2.q ),
+ .q (reg2hw.prio2.q),
// to register interface (read)
.qs (prio2_qs)
@@ -2166,8 +2198,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio3_we),
@@ -2175,11 +2207,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio3.q ),
+ .q (reg2hw.prio3.q),
// to register interface (read)
.qs (prio3_qs)
@@ -2193,8 +2225,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio4_we),
@@ -2202,11 +2234,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio4.q ),
+ .q (reg2hw.prio4.q),
// to register interface (read)
.qs (prio4_qs)
@@ -2220,8 +2252,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio5_we),
@@ -2229,11 +2261,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio5.q ),
+ .q (reg2hw.prio5.q),
// to register interface (read)
.qs (prio5_qs)
@@ -2247,8 +2279,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio6_we),
@@ -2256,11 +2288,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio6.q ),
+ .q (reg2hw.prio6.q),
// to register interface (read)
.qs (prio6_qs)
@@ -2274,8 +2306,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio7_we),
@@ -2283,11 +2315,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio7.q ),
+ .q (reg2hw.prio7.q),
// to register interface (read)
.qs (prio7_qs)
@@ -2301,8 +2333,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio8_we),
@@ -2310,11 +2342,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio8.q ),
+ .q (reg2hw.prio8.q),
// to register interface (read)
.qs (prio8_qs)
@@ -2328,8 +2360,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio9_we),
@@ -2337,11 +2369,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio9.q ),
+ .q (reg2hw.prio9.q),
// to register interface (read)
.qs (prio9_qs)
@@ -2355,8 +2387,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio10_we),
@@ -2364,11 +2396,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio10.q ),
+ .q (reg2hw.prio10.q),
// to register interface (read)
.qs (prio10_qs)
@@ -2382,8 +2414,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio11_we),
@@ -2391,11 +2423,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio11.q ),
+ .q (reg2hw.prio11.q),
// to register interface (read)
.qs (prio11_qs)
@@ -2409,8 +2441,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio12_we),
@@ -2418,11 +2450,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio12.q ),
+ .q (reg2hw.prio12.q),
// to register interface (read)
.qs (prio12_qs)
@@ -2436,8 +2468,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio13_we),
@@ -2445,11 +2477,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio13.q ),
+ .q (reg2hw.prio13.q),
// to register interface (read)
.qs (prio13_qs)
@@ -2463,8 +2495,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio14_we),
@@ -2472,11 +2504,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio14.q ),
+ .q (reg2hw.prio14.q),
// to register interface (read)
.qs (prio14_qs)
@@ -2490,8 +2522,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio15_we),
@@ -2499,11 +2531,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio15.q ),
+ .q (reg2hw.prio15.q),
// to register interface (read)
.qs (prio15_qs)
@@ -2517,8 +2549,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio16_we),
@@ -2526,11 +2558,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio16.q ),
+ .q (reg2hw.prio16.q),
// to register interface (read)
.qs (prio16_qs)
@@ -2544,8 +2576,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio17_we),
@@ -2553,11 +2585,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio17.q ),
+ .q (reg2hw.prio17.q),
// to register interface (read)
.qs (prio17_qs)
@@ -2571,8 +2603,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio18_we),
@@ -2580,11 +2612,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio18.q ),
+ .q (reg2hw.prio18.q),
// to register interface (read)
.qs (prio18_qs)
@@ -2598,8 +2630,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio19_we),
@@ -2607,11 +2639,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio19.q ),
+ .q (reg2hw.prio19.q),
// to register interface (read)
.qs (prio19_qs)
@@ -2625,8 +2657,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio20_we),
@@ -2634,11 +2666,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio20.q ),
+ .q (reg2hw.prio20.q),
// to register interface (read)
.qs (prio20_qs)
@@ -2652,8 +2684,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio21_we),
@@ -2661,11 +2693,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio21.q ),
+ .q (reg2hw.prio21.q),
// to register interface (read)
.qs (prio21_qs)
@@ -2679,8 +2711,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio22_we),
@@ -2688,11 +2720,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio22.q ),
+ .q (reg2hw.prio22.q),
// to register interface (read)
.qs (prio22_qs)
@@ -2706,8 +2738,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio23_we),
@@ -2715,11 +2747,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio23.q ),
+ .q (reg2hw.prio23.q),
// to register interface (read)
.qs (prio23_qs)
@@ -2733,8 +2765,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio24_we),
@@ -2742,11 +2774,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio24.q ),
+ .q (reg2hw.prio24.q),
// to register interface (read)
.qs (prio24_qs)
@@ -2760,8 +2792,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio25_we),
@@ -2769,11 +2801,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio25.q ),
+ .q (reg2hw.prio25.q),
// to register interface (read)
.qs (prio25_qs)
@@ -2787,8 +2819,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio26_we),
@@ -2796,11 +2828,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio26.q ),
+ .q (reg2hw.prio26.q),
// to register interface (read)
.qs (prio26_qs)
@@ -2814,8 +2846,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio27_we),
@@ -2823,11 +2855,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio27.q ),
+ .q (reg2hw.prio27.q),
// to register interface (read)
.qs (prio27_qs)
@@ -2841,8 +2873,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio28_we),
@@ -2850,11 +2882,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio28.q ),
+ .q (reg2hw.prio28.q),
// to register interface (read)
.qs (prio28_qs)
@@ -2868,8 +2900,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio29_we),
@@ -2877,11 +2909,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio29.q ),
+ .q (reg2hw.prio29.q),
// to register interface (read)
.qs (prio29_qs)
@@ -2895,8 +2927,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio30_we),
@@ -2904,11 +2936,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio30.q ),
+ .q (reg2hw.prio30.q),
// to register interface (read)
.qs (prio30_qs)
@@ -2922,8 +2954,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_prio31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio31_we),
@@ -2931,11 +2963,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio31.q ),
+ .q (reg2hw.prio31.q),
// to register interface (read)
.qs (prio31_qs)
@@ -2952,8 +2984,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_0_we),
@@ -2961,11 +2993,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[0].q ),
+ .q (reg2hw.ie0[0].q),
// to register interface (read)
.qs (ie0_e_0_qs)
@@ -2978,8 +3010,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_1_we),
@@ -2987,11 +3019,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[1].q ),
+ .q (reg2hw.ie0[1].q),
// to register interface (read)
.qs (ie0_e_1_qs)
@@ -3004,8 +3036,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_2_we),
@@ -3013,11 +3045,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[2].q ),
+ .q (reg2hw.ie0[2].q),
// to register interface (read)
.qs (ie0_e_2_qs)
@@ -3030,8 +3062,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_3_we),
@@ -3039,11 +3071,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[3].q ),
+ .q (reg2hw.ie0[3].q),
// to register interface (read)
.qs (ie0_e_3_qs)
@@ -3056,8 +3088,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_4_we),
@@ -3065,11 +3097,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[4].q ),
+ .q (reg2hw.ie0[4].q),
// to register interface (read)
.qs (ie0_e_4_qs)
@@ -3082,8 +3114,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_5_we),
@@ -3091,11 +3123,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[5].q ),
+ .q (reg2hw.ie0[5].q),
// to register interface (read)
.qs (ie0_e_5_qs)
@@ -3108,8 +3140,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_6_we),
@@ -3117,11 +3149,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[6].q ),
+ .q (reg2hw.ie0[6].q),
// to register interface (read)
.qs (ie0_e_6_qs)
@@ -3134,8 +3166,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_7_we),
@@ -3143,11 +3175,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[7].q ),
+ .q (reg2hw.ie0[7].q),
// to register interface (read)
.qs (ie0_e_7_qs)
@@ -3160,8 +3192,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_8_we),
@@ -3169,11 +3201,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[8].q ),
+ .q (reg2hw.ie0[8].q),
// to register interface (read)
.qs (ie0_e_8_qs)
@@ -3186,8 +3218,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_9_we),
@@ -3195,11 +3227,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[9].q ),
+ .q (reg2hw.ie0[9].q),
// to register interface (read)
.qs (ie0_e_9_qs)
@@ -3212,8 +3244,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_10_we),
@@ -3221,11 +3253,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[10].q ),
+ .q (reg2hw.ie0[10].q),
// to register interface (read)
.qs (ie0_e_10_qs)
@@ -3238,8 +3270,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_11_we),
@@ -3247,11 +3279,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[11].q ),
+ .q (reg2hw.ie0[11].q),
// to register interface (read)
.qs (ie0_e_11_qs)
@@ -3264,8 +3296,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_12_we),
@@ -3273,11 +3305,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[12].q ),
+ .q (reg2hw.ie0[12].q),
// to register interface (read)
.qs (ie0_e_12_qs)
@@ -3290,8 +3322,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_13_we),
@@ -3299,11 +3331,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[13].q ),
+ .q (reg2hw.ie0[13].q),
// to register interface (read)
.qs (ie0_e_13_qs)
@@ -3316,8 +3348,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_14_we),
@@ -3325,11 +3357,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[14].q ),
+ .q (reg2hw.ie0[14].q),
// to register interface (read)
.qs (ie0_e_14_qs)
@@ -3342,8 +3374,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_15_we),
@@ -3351,11 +3383,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[15].q ),
+ .q (reg2hw.ie0[15].q),
// to register interface (read)
.qs (ie0_e_15_qs)
@@ -3368,8 +3400,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_16_we),
@@ -3377,11 +3409,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[16].q ),
+ .q (reg2hw.ie0[16].q),
// to register interface (read)
.qs (ie0_e_16_qs)
@@ -3394,8 +3426,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_17_we),
@@ -3403,11 +3435,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[17].q ),
+ .q (reg2hw.ie0[17].q),
// to register interface (read)
.qs (ie0_e_17_qs)
@@ -3420,8 +3452,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_18_we),
@@ -3429,11 +3461,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[18].q ),
+ .q (reg2hw.ie0[18].q),
// to register interface (read)
.qs (ie0_e_18_qs)
@@ -3446,8 +3478,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_19_we),
@@ -3455,11 +3487,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[19].q ),
+ .q (reg2hw.ie0[19].q),
// to register interface (read)
.qs (ie0_e_19_qs)
@@ -3472,8 +3504,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_20_we),
@@ -3481,11 +3513,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[20].q ),
+ .q (reg2hw.ie0[20].q),
// to register interface (read)
.qs (ie0_e_20_qs)
@@ -3498,8 +3530,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_21_we),
@@ -3507,11 +3539,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[21].q ),
+ .q (reg2hw.ie0[21].q),
// to register interface (read)
.qs (ie0_e_21_qs)
@@ -3524,8 +3556,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_22_we),
@@ -3533,11 +3565,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[22].q ),
+ .q (reg2hw.ie0[22].q),
// to register interface (read)
.qs (ie0_e_22_qs)
@@ -3550,8 +3582,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_23_we),
@@ -3559,11 +3591,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[23].q ),
+ .q (reg2hw.ie0[23].q),
// to register interface (read)
.qs (ie0_e_23_qs)
@@ -3576,8 +3608,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_24_we),
@@ -3585,11 +3617,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[24].q ),
+ .q (reg2hw.ie0[24].q),
// to register interface (read)
.qs (ie0_e_24_qs)
@@ -3602,8 +3634,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_25_we),
@@ -3611,11 +3643,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[25].q ),
+ .q (reg2hw.ie0[25].q),
// to register interface (read)
.qs (ie0_e_25_qs)
@@ -3628,8 +3660,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_26_we),
@@ -3637,11 +3669,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[26].q ),
+ .q (reg2hw.ie0[26].q),
// to register interface (read)
.qs (ie0_e_26_qs)
@@ -3654,8 +3686,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_27_we),
@@ -3663,11 +3695,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[27].q ),
+ .q (reg2hw.ie0[27].q),
// to register interface (read)
.qs (ie0_e_27_qs)
@@ -3680,8 +3712,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_28_we),
@@ -3689,11 +3721,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[28].q ),
+ .q (reg2hw.ie0[28].q),
// to register interface (read)
.qs (ie0_e_28_qs)
@@ -3706,8 +3738,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_29_we),
@@ -3715,11 +3747,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[29].q ),
+ .q (reg2hw.ie0[29].q),
// to register interface (read)
.qs (ie0_e_29_qs)
@@ -3732,8 +3764,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_30_we),
@@ -3741,11 +3773,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[30].q ),
+ .q (reg2hw.ie0[30].q),
// to register interface (read)
.qs (ie0_e_30_qs)
@@ -3758,8 +3790,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_e_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_e_31_we),
@@ -3767,11 +3799,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[31].q ),
+ .q (reg2hw.ie0[31].q),
// to register interface (read)
.qs (ie0_e_31_qs)
@@ -3786,8 +3818,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_threshold0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (threshold0_we),
@@ -3795,11 +3827,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.threshold0.q ),
+ .q (reg2hw.threshold0.q),
// to register interface (read)
.qs (threshold0_qs)
@@ -3817,7 +3849,7 @@
.d (hw2reg.cc0.d),
.qre (reg2hw.cc0.re),
.qe (reg2hw.cc0.qe),
- .q (reg2hw.cc0.q ),
+ .q (reg2hw.cc0.q),
.qs (cc0_qs)
);
@@ -3829,8 +3861,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_msip0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (msip0_we),
@@ -3838,11 +3870,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.msip0.q ),
+ .q (reg2hw.msip0.q),
// to register interface (read)
.qs (msip0_qs)
diff --git a/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv b/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
index 5487720..47fa9fe 100644
--- a/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
+++ b/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
@@ -144,8 +144,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_we),
@@ -153,11 +153,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl[0].q ),
+ .q (reg2hw.ctrl[0].q),
// to register interface (read)
.qs (ctrl_qs)
@@ -172,8 +172,8 @@
.SWACCESS("RW"),
.RESVAL (12'h0)
) u_cfg0_prescale (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg0_prescale_we),
@@ -181,11 +181,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg0.prescale.q ),
+ .q (reg2hw.cfg0.prescale.q),
// to register interface (read)
.qs (cfg0_prescale_qs)
@@ -198,8 +198,8 @@
.SWACCESS("RW"),
.RESVAL (8'h1)
) u_cfg0_step (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg0_step_we),
@@ -207,11 +207,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg0.step.q ),
+ .q (reg2hw.cfg0.step.q),
// to register interface (read)
.qs (cfg0_step_qs)
@@ -225,8 +225,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_timer_v_lower0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timer_v_lower0_we),
@@ -234,11 +234,11 @@
// from internal hardware
.de (hw2reg.timer_v_lower0.de),
- .d (hw2reg.timer_v_lower0.d ),
+ .d (hw2reg.timer_v_lower0.d),
// to internal hardware
.qe (),
- .q (reg2hw.timer_v_lower0.q ),
+ .q (reg2hw.timer_v_lower0.q),
// to register interface (read)
.qs (timer_v_lower0_qs)
@@ -252,8 +252,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_timer_v_upper0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timer_v_upper0_we),
@@ -261,11 +261,11 @@
// from internal hardware
.de (hw2reg.timer_v_upper0.de),
- .d (hw2reg.timer_v_upper0.d ),
+ .d (hw2reg.timer_v_upper0.d),
// to internal hardware
.qe (),
- .q (reg2hw.timer_v_upper0.q ),
+ .q (reg2hw.timer_v_upper0.q),
// to register interface (read)
.qs (timer_v_upper0_qs)
@@ -279,8 +279,8 @@
.SWACCESS("RW"),
.RESVAL (32'hffffffff)
) u_compare_lower0_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (compare_lower0_0_we),
@@ -288,11 +288,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.compare_lower0_0.qe),
- .q (reg2hw.compare_lower0_0.q ),
+ .q (reg2hw.compare_lower0_0.q),
// to register interface (read)
.qs (compare_lower0_0_qs)
@@ -306,8 +306,8 @@
.SWACCESS("RW"),
.RESVAL (32'hffffffff)
) u_compare_upper0_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (compare_upper0_0_we),
@@ -315,11 +315,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.compare_upper0_0.qe),
- .q (reg2hw.compare_upper0_0.q ),
+ .q (reg2hw.compare_upper0_0.q),
// to register interface (read)
.qs (compare_upper0_0_qs)
@@ -335,8 +335,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable0_we),
@@ -344,11 +344,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable0[0].q ),
+ .q (reg2hw.intr_enable0[0].q),
// to register interface (read)
.qs (intr_enable0_qs)
@@ -364,8 +364,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state0_we),
@@ -373,11 +373,11 @@
// from internal hardware
.de (hw2reg.intr_state0[0].de),
- .d (hw2reg.intr_state0[0].d ),
+ .d (hw2reg.intr_state0[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state0[0].q ),
+ .q (reg2hw.intr_state0[0].q),
// to register interface (read)
.qs (intr_state0_qs)
@@ -397,7 +397,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test0[0].qe),
- .q (reg2hw.intr_test0[0].q ),
+ .q (reg2hw.intr_test0[0].q),
.qs ()
);
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_top.sv b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
index cd75fad..d1ccefb 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_top.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
@@ -1443,8 +1443,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rxf (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rxf_we),
@@ -1452,11 +1452,11 @@
// from internal hardware
.de (hw2reg.intr_state.rxf.de),
- .d (hw2reg.intr_state.rxf.d ),
+ .d (hw2reg.intr_state.rxf.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rxf.q ),
+ .q (reg2hw.intr_state.rxf.q),
// to register interface (read)
.qs (intr_state_rxf_qs)
@@ -1469,8 +1469,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rxlvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rxlvl_we),
@@ -1478,11 +1478,11 @@
// from internal hardware
.de (hw2reg.intr_state.rxlvl.de),
- .d (hw2reg.intr_state.rxlvl.d ),
+ .d (hw2reg.intr_state.rxlvl.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rxlvl.q ),
+ .q (reg2hw.intr_state.rxlvl.q),
// to register interface (read)
.qs (intr_state_rxlvl_qs)
@@ -1495,8 +1495,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_txlvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_txlvl_we),
@@ -1504,11 +1504,11 @@
// from internal hardware
.de (hw2reg.intr_state.txlvl.de),
- .d (hw2reg.intr_state.txlvl.d ),
+ .d (hw2reg.intr_state.txlvl.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.txlvl.q ),
+ .q (reg2hw.intr_state.txlvl.q),
// to register interface (read)
.qs (intr_state_txlvl_qs)
@@ -1521,8 +1521,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rxerr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rxerr_we),
@@ -1530,11 +1530,11 @@
// from internal hardware
.de (hw2reg.intr_state.rxerr.de),
- .d (hw2reg.intr_state.rxerr.d ),
+ .d (hw2reg.intr_state.rxerr.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rxerr.q ),
+ .q (reg2hw.intr_state.rxerr.q),
// to register interface (read)
.qs (intr_state_rxerr_qs)
@@ -1547,8 +1547,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rxoverflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rxoverflow_we),
@@ -1556,11 +1556,11 @@
// from internal hardware
.de (hw2reg.intr_state.rxoverflow.de),
- .d (hw2reg.intr_state.rxoverflow.d ),
+ .d (hw2reg.intr_state.rxoverflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rxoverflow.q ),
+ .q (reg2hw.intr_state.rxoverflow.q),
// to register interface (read)
.qs (intr_state_rxoverflow_qs)
@@ -1573,8 +1573,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_txunderflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_txunderflow_we),
@@ -1582,11 +1582,11 @@
// from internal hardware
.de (hw2reg.intr_state.txunderflow.de),
- .d (hw2reg.intr_state.txunderflow.d ),
+ .d (hw2reg.intr_state.txunderflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.txunderflow.q ),
+ .q (reg2hw.intr_state.txunderflow.q),
// to register interface (read)
.qs (intr_state_txunderflow_qs)
@@ -1601,8 +1601,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rxf (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rxf_we),
@@ -1610,11 +1610,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rxf.q ),
+ .q (reg2hw.intr_enable.rxf.q),
// to register interface (read)
.qs (intr_enable_rxf_qs)
@@ -1627,8 +1627,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rxlvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rxlvl_we),
@@ -1636,11 +1636,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rxlvl.q ),
+ .q (reg2hw.intr_enable.rxlvl.q),
// to register interface (read)
.qs (intr_enable_rxlvl_qs)
@@ -1653,8 +1653,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_txlvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_txlvl_we),
@@ -1662,11 +1662,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.txlvl.q ),
+ .q (reg2hw.intr_enable.txlvl.q),
// to register interface (read)
.qs (intr_enable_txlvl_qs)
@@ -1679,8 +1679,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rxerr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rxerr_we),
@@ -1688,11 +1688,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rxerr.q ),
+ .q (reg2hw.intr_enable.rxerr.q),
// to register interface (read)
.qs (intr_enable_rxerr_qs)
@@ -1705,8 +1705,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rxoverflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rxoverflow_we),
@@ -1714,11 +1714,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rxoverflow.q ),
+ .q (reg2hw.intr_enable.rxoverflow.q),
// to register interface (read)
.qs (intr_enable_rxoverflow_qs)
@@ -1731,8 +1731,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_txunderflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_txunderflow_we),
@@ -1740,11 +1740,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.txunderflow.q ),
+ .q (reg2hw.intr_enable.txunderflow.q),
// to register interface (read)
.qs (intr_enable_txunderflow_qs)
@@ -1763,7 +1763,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rxf.qe),
- .q (reg2hw.intr_test.rxf.q ),
+ .q (reg2hw.intr_test.rxf.q),
.qs ()
);
@@ -1778,7 +1778,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rxlvl.qe),
- .q (reg2hw.intr_test.rxlvl.q ),
+ .q (reg2hw.intr_test.rxlvl.q),
.qs ()
);
@@ -1793,7 +1793,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.txlvl.qe),
- .q (reg2hw.intr_test.txlvl.q ),
+ .q (reg2hw.intr_test.txlvl.q),
.qs ()
);
@@ -1808,7 +1808,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rxerr.qe),
- .q (reg2hw.intr_test.rxerr.q ),
+ .q (reg2hw.intr_test.rxerr.q),
.qs ()
);
@@ -1823,7 +1823,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rxoverflow.qe),
- .q (reg2hw.intr_test.rxoverflow.q ),
+ .q (reg2hw.intr_test.rxoverflow.q),
.qs ()
);
@@ -1838,7 +1838,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.txunderflow.qe),
- .q (reg2hw.intr_test.txunderflow.q ),
+ .q (reg2hw.intr_test.txunderflow.q),
.qs ()
);
@@ -1851,8 +1851,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_abort (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_abort_we),
@@ -1860,11 +1860,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.abort.q ),
+ .q (reg2hw.control.abort.q),
// to register interface (read)
.qs (control_abort_qs)
@@ -1877,8 +1877,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_control_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_mode_we),
@@ -1886,11 +1886,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.mode.q ),
+ .q (reg2hw.control.mode.q),
// to register interface (read)
.qs (control_mode_qs)
@@ -1903,8 +1903,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_rst_txfifo (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_rst_txfifo_we),
@@ -1912,11 +1912,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.rst_txfifo.q ),
+ .q (reg2hw.control.rst_txfifo.q),
// to register interface (read)
.qs (control_rst_txfifo_qs)
@@ -1929,8 +1929,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_rst_rxfifo (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_rst_rxfifo_we),
@@ -1938,11 +1938,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.rst_rxfifo.q ),
+ .q (reg2hw.control.rst_rxfifo.q),
// to register interface (read)
.qs (control_rst_rxfifo_qs)
@@ -1955,8 +1955,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_control_sram_clk_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_sram_clk_en_we),
@@ -1964,11 +1964,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.sram_clk_en.q ),
+ .q (reg2hw.control.sram_clk_en.q),
// to register interface (read)
.qs (control_sram_clk_en_qs)
@@ -1983,8 +1983,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_cpol (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg_cpol_we),
@@ -1992,11 +1992,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.cpol.q ),
+ .q (reg2hw.cfg.cpol.q),
// to register interface (read)
.qs (cfg_cpol_qs)
@@ -2009,8 +2009,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_cpha (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg_cpha_we),
@@ -2018,11 +2018,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.cpha.q ),
+ .q (reg2hw.cfg.cpha.q),
// to register interface (read)
.qs (cfg_cpha_qs)
@@ -2035,8 +2035,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_tx_order (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg_tx_order_we),
@@ -2044,11 +2044,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.tx_order.q ),
+ .q (reg2hw.cfg.tx_order.q),
// to register interface (read)
.qs (cfg_tx_order_qs)
@@ -2061,8 +2061,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_rx_order (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg_rx_order_we),
@@ -2070,11 +2070,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.rx_order.q ),
+ .q (reg2hw.cfg.rx_order.q),
// to register interface (read)
.qs (cfg_rx_order_qs)
@@ -2087,8 +2087,8 @@
.SWACCESS("RW"),
.RESVAL (8'h7f)
) u_cfg_timer_v (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg_timer_v_we),
@@ -2096,11 +2096,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.timer_v.q ),
+ .q (reg2hw.cfg.timer_v.q),
// to register interface (read)
.qs (cfg_timer_v_qs)
@@ -2113,8 +2113,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_addr_4b_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg_addr_4b_en_we),
@@ -2122,11 +2122,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cfg.addr_4b_en.q ),
+ .q (reg2hw.cfg.addr_4b_en.q),
// to register interface (read)
.qs (cfg_addr_4b_en_qs)
@@ -2141,8 +2141,8 @@
.SWACCESS("RW"),
.RESVAL (16'h80)
) u_fifo_level_rxlvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_level_rxlvl_we),
@@ -2150,11 +2150,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fifo_level.rxlvl.q ),
+ .q (reg2hw.fifo_level.rxlvl.q),
// to register interface (read)
.qs (fifo_level_rxlvl_qs)
@@ -2167,8 +2167,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_fifo_level_txlvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_level_txlvl_we),
@@ -2176,11 +2176,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fifo_level.txlvl.q ),
+ .q (reg2hw.fifo_level.txlvl.q),
// to register interface (read)
.qs (fifo_level_txlvl_qs)
@@ -2319,8 +2319,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_rxf_ptr_rptr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxf_ptr_rptr_we),
@@ -2328,11 +2328,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxf_ptr.rptr.q ),
+ .q (reg2hw.rxf_ptr.rptr.q),
// to register interface (read)
.qs (rxf_ptr_rptr_qs)
@@ -2345,15 +2345,16 @@
.SWACCESS("RO"),
.RESVAL (16'h0)
) u_rxf_ptr_wptr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.rxf_ptr.wptr.de),
- .d (hw2reg.rxf_ptr.wptr.d ),
+ .d (hw2reg.rxf_ptr.wptr.d),
// to internal hardware
.qe (),
@@ -2372,15 +2373,16 @@
.SWACCESS("RO"),
.RESVAL (16'h0)
) u_txf_ptr_rptr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.txf_ptr.rptr.de),
- .d (hw2reg.txf_ptr.rptr.d ),
+ .d (hw2reg.txf_ptr.rptr.d),
// to internal hardware
.qe (),
@@ -2397,8 +2399,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_txf_ptr_wptr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (txf_ptr_wptr_we),
@@ -2406,11 +2408,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.txf_ptr.wptr.q ),
+ .q (reg2hw.txf_ptr.wptr.q),
// to register interface (read)
.qs (txf_ptr_wptr_qs)
@@ -2425,8 +2427,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_rxf_addr_base (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxf_addr_base_we),
@@ -2434,11 +2436,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxf_addr.base.q ),
+ .q (reg2hw.rxf_addr.base.q),
// to register interface (read)
.qs (rxf_addr_base_qs)
@@ -2451,8 +2453,8 @@
.SWACCESS("RW"),
.RESVAL (16'h1fc)
) u_rxf_addr_limit (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxf_addr_limit_we),
@@ -2460,11 +2462,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxf_addr.limit.q ),
+ .q (reg2hw.rxf_addr.limit.q),
// to register interface (read)
.qs (rxf_addr_limit_qs)
@@ -2479,8 +2481,8 @@
.SWACCESS("RW"),
.RESVAL (16'h200)
) u_txf_addr_base (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (txf_addr_base_we),
@@ -2488,11 +2490,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.txf_addr.base.q ),
+ .q (reg2hw.txf_addr.base.q),
// to register interface (read)
.qs (txf_addr_base_qs)
@@ -2505,8 +2507,8 @@
.SWACCESS("RW"),
.RESVAL (16'h3fc)
) u_txf_addr_limit (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (txf_addr_limit_we),
@@ -2514,11 +2516,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.txf_addr.limit.q ),
+ .q (reg2hw.txf_addr.limit.q),
// to register interface (read)
.qs (txf_addr_limit_qs)
@@ -2535,8 +2537,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_0_we),
@@ -2544,11 +2546,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[0].q ),
+ .q (reg2hw.cmd_filter[0].q),
// to register interface (read)
.qs (cmd_filter_0_filter_0_qs)
@@ -2561,8 +2563,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_1_we),
@@ -2570,11 +2572,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[1].q ),
+ .q (reg2hw.cmd_filter[1].q),
// to register interface (read)
.qs (cmd_filter_0_filter_1_qs)
@@ -2587,8 +2589,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_2_we),
@@ -2596,11 +2598,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[2].q ),
+ .q (reg2hw.cmd_filter[2].q),
// to register interface (read)
.qs (cmd_filter_0_filter_2_qs)
@@ -2613,8 +2615,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_3_we),
@@ -2622,11 +2624,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[3].q ),
+ .q (reg2hw.cmd_filter[3].q),
// to register interface (read)
.qs (cmd_filter_0_filter_3_qs)
@@ -2639,8 +2641,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_4_we),
@@ -2648,11 +2650,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[4].q ),
+ .q (reg2hw.cmd_filter[4].q),
// to register interface (read)
.qs (cmd_filter_0_filter_4_qs)
@@ -2665,8 +2667,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_5_we),
@@ -2674,11 +2676,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[5].q ),
+ .q (reg2hw.cmd_filter[5].q),
// to register interface (read)
.qs (cmd_filter_0_filter_5_qs)
@@ -2691,8 +2693,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_6_we),
@@ -2700,11 +2702,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[6].q ),
+ .q (reg2hw.cmd_filter[6].q),
// to register interface (read)
.qs (cmd_filter_0_filter_6_qs)
@@ -2717,8 +2719,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_7_we),
@@ -2726,11 +2728,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[7].q ),
+ .q (reg2hw.cmd_filter[7].q),
// to register interface (read)
.qs (cmd_filter_0_filter_7_qs)
@@ -2743,8 +2745,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_8_we),
@@ -2752,11 +2754,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[8].q ),
+ .q (reg2hw.cmd_filter[8].q),
// to register interface (read)
.qs (cmd_filter_0_filter_8_qs)
@@ -2769,8 +2771,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_9_we),
@@ -2778,11 +2780,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[9].q ),
+ .q (reg2hw.cmd_filter[9].q),
// to register interface (read)
.qs (cmd_filter_0_filter_9_qs)
@@ -2795,8 +2797,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_10_we),
@@ -2804,11 +2806,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[10].q ),
+ .q (reg2hw.cmd_filter[10].q),
// to register interface (read)
.qs (cmd_filter_0_filter_10_qs)
@@ -2821,8 +2823,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_11_we),
@@ -2830,11 +2832,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[11].q ),
+ .q (reg2hw.cmd_filter[11].q),
// to register interface (read)
.qs (cmd_filter_0_filter_11_qs)
@@ -2847,8 +2849,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_12_we),
@@ -2856,11 +2858,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[12].q ),
+ .q (reg2hw.cmd_filter[12].q),
// to register interface (read)
.qs (cmd_filter_0_filter_12_qs)
@@ -2873,8 +2875,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_13_we),
@@ -2882,11 +2884,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[13].q ),
+ .q (reg2hw.cmd_filter[13].q),
// to register interface (read)
.qs (cmd_filter_0_filter_13_qs)
@@ -2899,8 +2901,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_14_we),
@@ -2908,11 +2910,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[14].q ),
+ .q (reg2hw.cmd_filter[14].q),
// to register interface (read)
.qs (cmd_filter_0_filter_14_qs)
@@ -2925,8 +2927,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_15_we),
@@ -2934,11 +2936,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[15].q ),
+ .q (reg2hw.cmd_filter[15].q),
// to register interface (read)
.qs (cmd_filter_0_filter_15_qs)
@@ -2951,8 +2953,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_16_we),
@@ -2960,11 +2962,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[16].q ),
+ .q (reg2hw.cmd_filter[16].q),
// to register interface (read)
.qs (cmd_filter_0_filter_16_qs)
@@ -2977,8 +2979,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_17_we),
@@ -2986,11 +2988,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[17].q ),
+ .q (reg2hw.cmd_filter[17].q),
// to register interface (read)
.qs (cmd_filter_0_filter_17_qs)
@@ -3003,8 +3005,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_18_we),
@@ -3012,11 +3014,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[18].q ),
+ .q (reg2hw.cmd_filter[18].q),
// to register interface (read)
.qs (cmd_filter_0_filter_18_qs)
@@ -3029,8 +3031,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_19_we),
@@ -3038,11 +3040,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[19].q ),
+ .q (reg2hw.cmd_filter[19].q),
// to register interface (read)
.qs (cmd_filter_0_filter_19_qs)
@@ -3055,8 +3057,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_20_we),
@@ -3064,11 +3066,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[20].q ),
+ .q (reg2hw.cmd_filter[20].q),
// to register interface (read)
.qs (cmd_filter_0_filter_20_qs)
@@ -3081,8 +3083,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_21_we),
@@ -3090,11 +3092,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[21].q ),
+ .q (reg2hw.cmd_filter[21].q),
// to register interface (read)
.qs (cmd_filter_0_filter_21_qs)
@@ -3107,8 +3109,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_22_we),
@@ -3116,11 +3118,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[22].q ),
+ .q (reg2hw.cmd_filter[22].q),
// to register interface (read)
.qs (cmd_filter_0_filter_22_qs)
@@ -3133,8 +3135,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_23_we),
@@ -3142,11 +3144,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[23].q ),
+ .q (reg2hw.cmd_filter[23].q),
// to register interface (read)
.qs (cmd_filter_0_filter_23_qs)
@@ -3159,8 +3161,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_24_we),
@@ -3168,11 +3170,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[24].q ),
+ .q (reg2hw.cmd_filter[24].q),
// to register interface (read)
.qs (cmd_filter_0_filter_24_qs)
@@ -3185,8 +3187,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_25_we),
@@ -3194,11 +3196,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[25].q ),
+ .q (reg2hw.cmd_filter[25].q),
// to register interface (read)
.qs (cmd_filter_0_filter_25_qs)
@@ -3211,8 +3213,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_26_we),
@@ -3220,11 +3222,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[26].q ),
+ .q (reg2hw.cmd_filter[26].q),
// to register interface (read)
.qs (cmd_filter_0_filter_26_qs)
@@ -3237,8 +3239,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_27_we),
@@ -3246,11 +3248,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[27].q ),
+ .q (reg2hw.cmd_filter[27].q),
// to register interface (read)
.qs (cmd_filter_0_filter_27_qs)
@@ -3263,8 +3265,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_28_we),
@@ -3272,11 +3274,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[28].q ),
+ .q (reg2hw.cmd_filter[28].q),
// to register interface (read)
.qs (cmd_filter_0_filter_28_qs)
@@ -3289,8 +3291,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_29_we),
@@ -3298,11 +3300,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[29].q ),
+ .q (reg2hw.cmd_filter[29].q),
// to register interface (read)
.qs (cmd_filter_0_filter_29_qs)
@@ -3315,8 +3317,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_30_we),
@@ -3324,11 +3326,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[30].q ),
+ .q (reg2hw.cmd_filter[30].q),
// to register interface (read)
.qs (cmd_filter_0_filter_30_qs)
@@ -3341,8 +3343,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_0_filter_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_0_filter_31_we),
@@ -3350,11 +3352,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[31].q ),
+ .q (reg2hw.cmd_filter[31].q),
// to register interface (read)
.qs (cmd_filter_0_filter_31_qs)
@@ -3370,8 +3372,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_32_we),
@@ -3379,11 +3381,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[32].q ),
+ .q (reg2hw.cmd_filter[32].q),
// to register interface (read)
.qs (cmd_filter_1_filter_32_qs)
@@ -3396,8 +3398,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_33_we),
@@ -3405,11 +3407,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[33].q ),
+ .q (reg2hw.cmd_filter[33].q),
// to register interface (read)
.qs (cmd_filter_1_filter_33_qs)
@@ -3422,8 +3424,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_34_we),
@@ -3431,11 +3433,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[34].q ),
+ .q (reg2hw.cmd_filter[34].q),
// to register interface (read)
.qs (cmd_filter_1_filter_34_qs)
@@ -3448,8 +3450,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_35_we),
@@ -3457,11 +3459,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[35].q ),
+ .q (reg2hw.cmd_filter[35].q),
// to register interface (read)
.qs (cmd_filter_1_filter_35_qs)
@@ -3474,8 +3476,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_36_we),
@@ -3483,11 +3485,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[36].q ),
+ .q (reg2hw.cmd_filter[36].q),
// to register interface (read)
.qs (cmd_filter_1_filter_36_qs)
@@ -3500,8 +3502,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_37_we),
@@ -3509,11 +3511,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[37].q ),
+ .q (reg2hw.cmd_filter[37].q),
// to register interface (read)
.qs (cmd_filter_1_filter_37_qs)
@@ -3526,8 +3528,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_38_we),
@@ -3535,11 +3537,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[38].q ),
+ .q (reg2hw.cmd_filter[38].q),
// to register interface (read)
.qs (cmd_filter_1_filter_38_qs)
@@ -3552,8 +3554,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_39_we),
@@ -3561,11 +3563,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[39].q ),
+ .q (reg2hw.cmd_filter[39].q),
// to register interface (read)
.qs (cmd_filter_1_filter_39_qs)
@@ -3578,8 +3580,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_40_we),
@@ -3587,11 +3589,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[40].q ),
+ .q (reg2hw.cmd_filter[40].q),
// to register interface (read)
.qs (cmd_filter_1_filter_40_qs)
@@ -3604,8 +3606,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_41_we),
@@ -3613,11 +3615,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[41].q ),
+ .q (reg2hw.cmd_filter[41].q),
// to register interface (read)
.qs (cmd_filter_1_filter_41_qs)
@@ -3630,8 +3632,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_42_we),
@@ -3639,11 +3641,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[42].q ),
+ .q (reg2hw.cmd_filter[42].q),
// to register interface (read)
.qs (cmd_filter_1_filter_42_qs)
@@ -3656,8 +3658,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_43_we),
@@ -3665,11 +3667,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[43].q ),
+ .q (reg2hw.cmd_filter[43].q),
// to register interface (read)
.qs (cmd_filter_1_filter_43_qs)
@@ -3682,8 +3684,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_44_we),
@@ -3691,11 +3693,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[44].q ),
+ .q (reg2hw.cmd_filter[44].q),
// to register interface (read)
.qs (cmd_filter_1_filter_44_qs)
@@ -3708,8 +3710,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_45_we),
@@ -3717,11 +3719,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[45].q ),
+ .q (reg2hw.cmd_filter[45].q),
// to register interface (read)
.qs (cmd_filter_1_filter_45_qs)
@@ -3734,8 +3736,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_46_we),
@@ -3743,11 +3745,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[46].q ),
+ .q (reg2hw.cmd_filter[46].q),
// to register interface (read)
.qs (cmd_filter_1_filter_46_qs)
@@ -3760,8 +3762,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_47 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_47_we),
@@ -3769,11 +3771,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[47].q ),
+ .q (reg2hw.cmd_filter[47].q),
// to register interface (read)
.qs (cmd_filter_1_filter_47_qs)
@@ -3786,8 +3788,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_48 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_48_we),
@@ -3795,11 +3797,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[48].q ),
+ .q (reg2hw.cmd_filter[48].q),
// to register interface (read)
.qs (cmd_filter_1_filter_48_qs)
@@ -3812,8 +3814,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_49 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_49_we),
@@ -3821,11 +3823,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[49].q ),
+ .q (reg2hw.cmd_filter[49].q),
// to register interface (read)
.qs (cmd_filter_1_filter_49_qs)
@@ -3838,8 +3840,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_50 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_50_we),
@@ -3847,11 +3849,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[50].q ),
+ .q (reg2hw.cmd_filter[50].q),
// to register interface (read)
.qs (cmd_filter_1_filter_50_qs)
@@ -3864,8 +3866,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_51 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_51_we),
@@ -3873,11 +3875,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[51].q ),
+ .q (reg2hw.cmd_filter[51].q),
// to register interface (read)
.qs (cmd_filter_1_filter_51_qs)
@@ -3890,8 +3892,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_52_we),
@@ -3899,11 +3901,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[52].q ),
+ .q (reg2hw.cmd_filter[52].q),
// to register interface (read)
.qs (cmd_filter_1_filter_52_qs)
@@ -3916,8 +3918,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_53_we),
@@ -3925,11 +3927,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[53].q ),
+ .q (reg2hw.cmd_filter[53].q),
// to register interface (read)
.qs (cmd_filter_1_filter_53_qs)
@@ -3942,8 +3944,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_54 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_54_we),
@@ -3951,11 +3953,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[54].q ),
+ .q (reg2hw.cmd_filter[54].q),
// to register interface (read)
.qs (cmd_filter_1_filter_54_qs)
@@ -3968,8 +3970,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_55 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_55_we),
@@ -3977,11 +3979,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[55].q ),
+ .q (reg2hw.cmd_filter[55].q),
// to register interface (read)
.qs (cmd_filter_1_filter_55_qs)
@@ -3994,8 +3996,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_56 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_56_we),
@@ -4003,11 +4005,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[56].q ),
+ .q (reg2hw.cmd_filter[56].q),
// to register interface (read)
.qs (cmd_filter_1_filter_56_qs)
@@ -4020,8 +4022,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_57 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_57_we),
@@ -4029,11 +4031,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[57].q ),
+ .q (reg2hw.cmd_filter[57].q),
// to register interface (read)
.qs (cmd_filter_1_filter_57_qs)
@@ -4046,8 +4048,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_58 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_58_we),
@@ -4055,11 +4057,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[58].q ),
+ .q (reg2hw.cmd_filter[58].q),
// to register interface (read)
.qs (cmd_filter_1_filter_58_qs)
@@ -4072,8 +4074,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_59 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_59_we),
@@ -4081,11 +4083,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[59].q ),
+ .q (reg2hw.cmd_filter[59].q),
// to register interface (read)
.qs (cmd_filter_1_filter_59_qs)
@@ -4098,8 +4100,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_60 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_60_we),
@@ -4107,11 +4109,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[60].q ),
+ .q (reg2hw.cmd_filter[60].q),
// to register interface (read)
.qs (cmd_filter_1_filter_60_qs)
@@ -4124,8 +4126,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_61 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_61_we),
@@ -4133,11 +4135,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[61].q ),
+ .q (reg2hw.cmd_filter[61].q),
// to register interface (read)
.qs (cmd_filter_1_filter_61_qs)
@@ -4150,8 +4152,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_62 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_62_we),
@@ -4159,11 +4161,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[62].q ),
+ .q (reg2hw.cmd_filter[62].q),
// to register interface (read)
.qs (cmd_filter_1_filter_62_qs)
@@ -4176,8 +4178,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_1_filter_63 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_1_filter_63_we),
@@ -4185,11 +4187,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[63].q ),
+ .q (reg2hw.cmd_filter[63].q),
// to register interface (read)
.qs (cmd_filter_1_filter_63_qs)
@@ -4205,8 +4207,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_64 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_64_we),
@@ -4214,11 +4216,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[64].q ),
+ .q (reg2hw.cmd_filter[64].q),
// to register interface (read)
.qs (cmd_filter_2_filter_64_qs)
@@ -4231,8 +4233,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_65 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_65_we),
@@ -4240,11 +4242,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[65].q ),
+ .q (reg2hw.cmd_filter[65].q),
// to register interface (read)
.qs (cmd_filter_2_filter_65_qs)
@@ -4257,8 +4259,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_66 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_66_we),
@@ -4266,11 +4268,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[66].q ),
+ .q (reg2hw.cmd_filter[66].q),
// to register interface (read)
.qs (cmd_filter_2_filter_66_qs)
@@ -4283,8 +4285,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_67 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_67_we),
@@ -4292,11 +4294,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[67].q ),
+ .q (reg2hw.cmd_filter[67].q),
// to register interface (read)
.qs (cmd_filter_2_filter_67_qs)
@@ -4309,8 +4311,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_68 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_68_we),
@@ -4318,11 +4320,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[68].q ),
+ .q (reg2hw.cmd_filter[68].q),
// to register interface (read)
.qs (cmd_filter_2_filter_68_qs)
@@ -4335,8 +4337,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_69 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_69_we),
@@ -4344,11 +4346,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[69].q ),
+ .q (reg2hw.cmd_filter[69].q),
// to register interface (read)
.qs (cmd_filter_2_filter_69_qs)
@@ -4361,8 +4363,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_70 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_70_we),
@@ -4370,11 +4372,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[70].q ),
+ .q (reg2hw.cmd_filter[70].q),
// to register interface (read)
.qs (cmd_filter_2_filter_70_qs)
@@ -4387,8 +4389,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_71 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_71_we),
@@ -4396,11 +4398,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[71].q ),
+ .q (reg2hw.cmd_filter[71].q),
// to register interface (read)
.qs (cmd_filter_2_filter_71_qs)
@@ -4413,8 +4415,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_72 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_72_we),
@@ -4422,11 +4424,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[72].q ),
+ .q (reg2hw.cmd_filter[72].q),
// to register interface (read)
.qs (cmd_filter_2_filter_72_qs)
@@ -4439,8 +4441,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_73 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_73_we),
@@ -4448,11 +4450,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[73].q ),
+ .q (reg2hw.cmd_filter[73].q),
// to register interface (read)
.qs (cmd_filter_2_filter_73_qs)
@@ -4465,8 +4467,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_74 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_74_we),
@@ -4474,11 +4476,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[74].q ),
+ .q (reg2hw.cmd_filter[74].q),
// to register interface (read)
.qs (cmd_filter_2_filter_74_qs)
@@ -4491,8 +4493,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_75 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_75_we),
@@ -4500,11 +4502,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[75].q ),
+ .q (reg2hw.cmd_filter[75].q),
// to register interface (read)
.qs (cmd_filter_2_filter_75_qs)
@@ -4517,8 +4519,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_76 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_76_we),
@@ -4526,11 +4528,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[76].q ),
+ .q (reg2hw.cmd_filter[76].q),
// to register interface (read)
.qs (cmd_filter_2_filter_76_qs)
@@ -4543,8 +4545,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_77 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_77_we),
@@ -4552,11 +4554,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[77].q ),
+ .q (reg2hw.cmd_filter[77].q),
// to register interface (read)
.qs (cmd_filter_2_filter_77_qs)
@@ -4569,8 +4571,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_78 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_78_we),
@@ -4578,11 +4580,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[78].q ),
+ .q (reg2hw.cmd_filter[78].q),
// to register interface (read)
.qs (cmd_filter_2_filter_78_qs)
@@ -4595,8 +4597,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_79 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_79_we),
@@ -4604,11 +4606,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[79].q ),
+ .q (reg2hw.cmd_filter[79].q),
// to register interface (read)
.qs (cmd_filter_2_filter_79_qs)
@@ -4621,8 +4623,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_80 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_80_we),
@@ -4630,11 +4632,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[80].q ),
+ .q (reg2hw.cmd_filter[80].q),
// to register interface (read)
.qs (cmd_filter_2_filter_80_qs)
@@ -4647,8 +4649,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_81 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_81_we),
@@ -4656,11 +4658,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[81].q ),
+ .q (reg2hw.cmd_filter[81].q),
// to register interface (read)
.qs (cmd_filter_2_filter_81_qs)
@@ -4673,8 +4675,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_82 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_82_we),
@@ -4682,11 +4684,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[82].q ),
+ .q (reg2hw.cmd_filter[82].q),
// to register interface (read)
.qs (cmd_filter_2_filter_82_qs)
@@ -4699,8 +4701,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_83 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_83_we),
@@ -4708,11 +4710,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[83].q ),
+ .q (reg2hw.cmd_filter[83].q),
// to register interface (read)
.qs (cmd_filter_2_filter_83_qs)
@@ -4725,8 +4727,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_84 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_84_we),
@@ -4734,11 +4736,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[84].q ),
+ .q (reg2hw.cmd_filter[84].q),
// to register interface (read)
.qs (cmd_filter_2_filter_84_qs)
@@ -4751,8 +4753,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_85 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_85_we),
@@ -4760,11 +4762,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[85].q ),
+ .q (reg2hw.cmd_filter[85].q),
// to register interface (read)
.qs (cmd_filter_2_filter_85_qs)
@@ -4777,8 +4779,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_86 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_86_we),
@@ -4786,11 +4788,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[86].q ),
+ .q (reg2hw.cmd_filter[86].q),
// to register interface (read)
.qs (cmd_filter_2_filter_86_qs)
@@ -4803,8 +4805,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_87 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_87_we),
@@ -4812,11 +4814,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[87].q ),
+ .q (reg2hw.cmd_filter[87].q),
// to register interface (read)
.qs (cmd_filter_2_filter_87_qs)
@@ -4829,8 +4831,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_88 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_88_we),
@@ -4838,11 +4840,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[88].q ),
+ .q (reg2hw.cmd_filter[88].q),
// to register interface (read)
.qs (cmd_filter_2_filter_88_qs)
@@ -4855,8 +4857,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_89 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_89_we),
@@ -4864,11 +4866,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[89].q ),
+ .q (reg2hw.cmd_filter[89].q),
// to register interface (read)
.qs (cmd_filter_2_filter_89_qs)
@@ -4881,8 +4883,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_90 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_90_we),
@@ -4890,11 +4892,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[90].q ),
+ .q (reg2hw.cmd_filter[90].q),
// to register interface (read)
.qs (cmd_filter_2_filter_90_qs)
@@ -4907,8 +4909,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_91 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_91_we),
@@ -4916,11 +4918,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[91].q ),
+ .q (reg2hw.cmd_filter[91].q),
// to register interface (read)
.qs (cmd_filter_2_filter_91_qs)
@@ -4933,8 +4935,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_92 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_92_we),
@@ -4942,11 +4944,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[92].q ),
+ .q (reg2hw.cmd_filter[92].q),
// to register interface (read)
.qs (cmd_filter_2_filter_92_qs)
@@ -4959,8 +4961,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_93 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_93_we),
@@ -4968,11 +4970,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[93].q ),
+ .q (reg2hw.cmd_filter[93].q),
// to register interface (read)
.qs (cmd_filter_2_filter_93_qs)
@@ -4985,8 +4987,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_94 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_94_we),
@@ -4994,11 +4996,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[94].q ),
+ .q (reg2hw.cmd_filter[94].q),
// to register interface (read)
.qs (cmd_filter_2_filter_94_qs)
@@ -5011,8 +5013,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_2_filter_95 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_2_filter_95_we),
@@ -5020,11 +5022,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[95].q ),
+ .q (reg2hw.cmd_filter[95].q),
// to register interface (read)
.qs (cmd_filter_2_filter_95_qs)
@@ -5040,8 +5042,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_96 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_96_we),
@@ -5049,11 +5051,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[96].q ),
+ .q (reg2hw.cmd_filter[96].q),
// to register interface (read)
.qs (cmd_filter_3_filter_96_qs)
@@ -5066,8 +5068,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_97 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_97_we),
@@ -5075,11 +5077,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[97].q ),
+ .q (reg2hw.cmd_filter[97].q),
// to register interface (read)
.qs (cmd_filter_3_filter_97_qs)
@@ -5092,8 +5094,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_98 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_98_we),
@@ -5101,11 +5103,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[98].q ),
+ .q (reg2hw.cmd_filter[98].q),
// to register interface (read)
.qs (cmd_filter_3_filter_98_qs)
@@ -5118,8 +5120,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_99 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_99_we),
@@ -5127,11 +5129,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[99].q ),
+ .q (reg2hw.cmd_filter[99].q),
// to register interface (read)
.qs (cmd_filter_3_filter_99_qs)
@@ -5144,8 +5146,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_100 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_100_we),
@@ -5153,11 +5155,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[100].q ),
+ .q (reg2hw.cmd_filter[100].q),
// to register interface (read)
.qs (cmd_filter_3_filter_100_qs)
@@ -5170,8 +5172,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_101 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_101_we),
@@ -5179,11 +5181,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[101].q ),
+ .q (reg2hw.cmd_filter[101].q),
// to register interface (read)
.qs (cmd_filter_3_filter_101_qs)
@@ -5196,8 +5198,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_102 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_102_we),
@@ -5205,11 +5207,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[102].q ),
+ .q (reg2hw.cmd_filter[102].q),
// to register interface (read)
.qs (cmd_filter_3_filter_102_qs)
@@ -5222,8 +5224,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_103 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_103_we),
@@ -5231,11 +5233,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[103].q ),
+ .q (reg2hw.cmd_filter[103].q),
// to register interface (read)
.qs (cmd_filter_3_filter_103_qs)
@@ -5248,8 +5250,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_104 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_104_we),
@@ -5257,11 +5259,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[104].q ),
+ .q (reg2hw.cmd_filter[104].q),
// to register interface (read)
.qs (cmd_filter_3_filter_104_qs)
@@ -5274,8 +5276,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_105 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_105_we),
@@ -5283,11 +5285,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[105].q ),
+ .q (reg2hw.cmd_filter[105].q),
// to register interface (read)
.qs (cmd_filter_3_filter_105_qs)
@@ -5300,8 +5302,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_106 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_106_we),
@@ -5309,11 +5311,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[106].q ),
+ .q (reg2hw.cmd_filter[106].q),
// to register interface (read)
.qs (cmd_filter_3_filter_106_qs)
@@ -5326,8 +5328,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_107 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_107_we),
@@ -5335,11 +5337,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[107].q ),
+ .q (reg2hw.cmd_filter[107].q),
// to register interface (read)
.qs (cmd_filter_3_filter_107_qs)
@@ -5352,8 +5354,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_108 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_108_we),
@@ -5361,11 +5363,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[108].q ),
+ .q (reg2hw.cmd_filter[108].q),
// to register interface (read)
.qs (cmd_filter_3_filter_108_qs)
@@ -5378,8 +5380,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_109 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_109_we),
@@ -5387,11 +5389,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[109].q ),
+ .q (reg2hw.cmd_filter[109].q),
// to register interface (read)
.qs (cmd_filter_3_filter_109_qs)
@@ -5404,8 +5406,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_110 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_110_we),
@@ -5413,11 +5415,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[110].q ),
+ .q (reg2hw.cmd_filter[110].q),
// to register interface (read)
.qs (cmd_filter_3_filter_110_qs)
@@ -5430,8 +5432,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_111 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_111_we),
@@ -5439,11 +5441,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[111].q ),
+ .q (reg2hw.cmd_filter[111].q),
// to register interface (read)
.qs (cmd_filter_3_filter_111_qs)
@@ -5456,8 +5458,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_112 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_112_we),
@@ -5465,11 +5467,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[112].q ),
+ .q (reg2hw.cmd_filter[112].q),
// to register interface (read)
.qs (cmd_filter_3_filter_112_qs)
@@ -5482,8 +5484,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_113 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_113_we),
@@ -5491,11 +5493,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[113].q ),
+ .q (reg2hw.cmd_filter[113].q),
// to register interface (read)
.qs (cmd_filter_3_filter_113_qs)
@@ -5508,8 +5510,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_114 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_114_we),
@@ -5517,11 +5519,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[114].q ),
+ .q (reg2hw.cmd_filter[114].q),
// to register interface (read)
.qs (cmd_filter_3_filter_114_qs)
@@ -5534,8 +5536,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_115 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_115_we),
@@ -5543,11 +5545,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[115].q ),
+ .q (reg2hw.cmd_filter[115].q),
// to register interface (read)
.qs (cmd_filter_3_filter_115_qs)
@@ -5560,8 +5562,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_116 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_116_we),
@@ -5569,11 +5571,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[116].q ),
+ .q (reg2hw.cmd_filter[116].q),
// to register interface (read)
.qs (cmd_filter_3_filter_116_qs)
@@ -5586,8 +5588,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_117 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_117_we),
@@ -5595,11 +5597,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[117].q ),
+ .q (reg2hw.cmd_filter[117].q),
// to register interface (read)
.qs (cmd_filter_3_filter_117_qs)
@@ -5612,8 +5614,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_118 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_118_we),
@@ -5621,11 +5623,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[118].q ),
+ .q (reg2hw.cmd_filter[118].q),
// to register interface (read)
.qs (cmd_filter_3_filter_118_qs)
@@ -5638,8 +5640,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_119 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_119_we),
@@ -5647,11 +5649,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[119].q ),
+ .q (reg2hw.cmd_filter[119].q),
// to register interface (read)
.qs (cmd_filter_3_filter_119_qs)
@@ -5664,8 +5666,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_120 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_120_we),
@@ -5673,11 +5675,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[120].q ),
+ .q (reg2hw.cmd_filter[120].q),
// to register interface (read)
.qs (cmd_filter_3_filter_120_qs)
@@ -5690,8 +5692,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_121 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_121_we),
@@ -5699,11 +5701,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[121].q ),
+ .q (reg2hw.cmd_filter[121].q),
// to register interface (read)
.qs (cmd_filter_3_filter_121_qs)
@@ -5716,8 +5718,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_122 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_122_we),
@@ -5725,11 +5727,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[122].q ),
+ .q (reg2hw.cmd_filter[122].q),
// to register interface (read)
.qs (cmd_filter_3_filter_122_qs)
@@ -5742,8 +5744,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_123 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_123_we),
@@ -5751,11 +5753,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[123].q ),
+ .q (reg2hw.cmd_filter[123].q),
// to register interface (read)
.qs (cmd_filter_3_filter_123_qs)
@@ -5768,8 +5770,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_124 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_124_we),
@@ -5777,11 +5779,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[124].q ),
+ .q (reg2hw.cmd_filter[124].q),
// to register interface (read)
.qs (cmd_filter_3_filter_124_qs)
@@ -5794,8 +5796,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_125 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_125_we),
@@ -5803,11 +5805,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[125].q ),
+ .q (reg2hw.cmd_filter[125].q),
// to register interface (read)
.qs (cmd_filter_3_filter_125_qs)
@@ -5820,8 +5822,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_126 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_126_we),
@@ -5829,11 +5831,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[126].q ),
+ .q (reg2hw.cmd_filter[126].q),
// to register interface (read)
.qs (cmd_filter_3_filter_126_qs)
@@ -5846,8 +5848,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_3_filter_127 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_3_filter_127_we),
@@ -5855,11 +5857,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[127].q ),
+ .q (reg2hw.cmd_filter[127].q),
// to register interface (read)
.qs (cmd_filter_3_filter_127_qs)
@@ -5875,8 +5877,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_128 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_128_we),
@@ -5884,11 +5886,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[128].q ),
+ .q (reg2hw.cmd_filter[128].q),
// to register interface (read)
.qs (cmd_filter_4_filter_128_qs)
@@ -5901,8 +5903,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_129 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_129_we),
@@ -5910,11 +5912,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[129].q ),
+ .q (reg2hw.cmd_filter[129].q),
// to register interface (read)
.qs (cmd_filter_4_filter_129_qs)
@@ -5927,8 +5929,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_130 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_130_we),
@@ -5936,11 +5938,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[130].q ),
+ .q (reg2hw.cmd_filter[130].q),
// to register interface (read)
.qs (cmd_filter_4_filter_130_qs)
@@ -5953,8 +5955,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_131 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_131_we),
@@ -5962,11 +5964,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[131].q ),
+ .q (reg2hw.cmd_filter[131].q),
// to register interface (read)
.qs (cmd_filter_4_filter_131_qs)
@@ -5979,8 +5981,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_132 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_132_we),
@@ -5988,11 +5990,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[132].q ),
+ .q (reg2hw.cmd_filter[132].q),
// to register interface (read)
.qs (cmd_filter_4_filter_132_qs)
@@ -6005,8 +6007,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_133 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_133_we),
@@ -6014,11 +6016,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[133].q ),
+ .q (reg2hw.cmd_filter[133].q),
// to register interface (read)
.qs (cmd_filter_4_filter_133_qs)
@@ -6031,8 +6033,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_134 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_134_we),
@@ -6040,11 +6042,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[134].q ),
+ .q (reg2hw.cmd_filter[134].q),
// to register interface (read)
.qs (cmd_filter_4_filter_134_qs)
@@ -6057,8 +6059,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_135 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_135_we),
@@ -6066,11 +6068,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[135].q ),
+ .q (reg2hw.cmd_filter[135].q),
// to register interface (read)
.qs (cmd_filter_4_filter_135_qs)
@@ -6083,8 +6085,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_136 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_136_we),
@@ -6092,11 +6094,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[136].q ),
+ .q (reg2hw.cmd_filter[136].q),
// to register interface (read)
.qs (cmd_filter_4_filter_136_qs)
@@ -6109,8 +6111,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_137 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_137_we),
@@ -6118,11 +6120,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[137].q ),
+ .q (reg2hw.cmd_filter[137].q),
// to register interface (read)
.qs (cmd_filter_4_filter_137_qs)
@@ -6135,8 +6137,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_138 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_138_we),
@@ -6144,11 +6146,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[138].q ),
+ .q (reg2hw.cmd_filter[138].q),
// to register interface (read)
.qs (cmd_filter_4_filter_138_qs)
@@ -6161,8 +6163,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_139 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_139_we),
@@ -6170,11 +6172,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[139].q ),
+ .q (reg2hw.cmd_filter[139].q),
// to register interface (read)
.qs (cmd_filter_4_filter_139_qs)
@@ -6187,8 +6189,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_140 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_140_we),
@@ -6196,11 +6198,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[140].q ),
+ .q (reg2hw.cmd_filter[140].q),
// to register interface (read)
.qs (cmd_filter_4_filter_140_qs)
@@ -6213,8 +6215,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_141 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_141_we),
@@ -6222,11 +6224,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[141].q ),
+ .q (reg2hw.cmd_filter[141].q),
// to register interface (read)
.qs (cmd_filter_4_filter_141_qs)
@@ -6239,8 +6241,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_142 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_142_we),
@@ -6248,11 +6250,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[142].q ),
+ .q (reg2hw.cmd_filter[142].q),
// to register interface (read)
.qs (cmd_filter_4_filter_142_qs)
@@ -6265,8 +6267,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_143 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_143_we),
@@ -6274,11 +6276,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[143].q ),
+ .q (reg2hw.cmd_filter[143].q),
// to register interface (read)
.qs (cmd_filter_4_filter_143_qs)
@@ -6291,8 +6293,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_144 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_144_we),
@@ -6300,11 +6302,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[144].q ),
+ .q (reg2hw.cmd_filter[144].q),
// to register interface (read)
.qs (cmd_filter_4_filter_144_qs)
@@ -6317,8 +6319,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_145 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_145_we),
@@ -6326,11 +6328,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[145].q ),
+ .q (reg2hw.cmd_filter[145].q),
// to register interface (read)
.qs (cmd_filter_4_filter_145_qs)
@@ -6343,8 +6345,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_146 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_146_we),
@@ -6352,11 +6354,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[146].q ),
+ .q (reg2hw.cmd_filter[146].q),
// to register interface (read)
.qs (cmd_filter_4_filter_146_qs)
@@ -6369,8 +6371,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_147 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_147_we),
@@ -6378,11 +6380,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[147].q ),
+ .q (reg2hw.cmd_filter[147].q),
// to register interface (read)
.qs (cmd_filter_4_filter_147_qs)
@@ -6395,8 +6397,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_148 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_148_we),
@@ -6404,11 +6406,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[148].q ),
+ .q (reg2hw.cmd_filter[148].q),
// to register interface (read)
.qs (cmd_filter_4_filter_148_qs)
@@ -6421,8 +6423,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_149 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_149_we),
@@ -6430,11 +6432,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[149].q ),
+ .q (reg2hw.cmd_filter[149].q),
// to register interface (read)
.qs (cmd_filter_4_filter_149_qs)
@@ -6447,8 +6449,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_150 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_150_we),
@@ -6456,11 +6458,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[150].q ),
+ .q (reg2hw.cmd_filter[150].q),
// to register interface (read)
.qs (cmd_filter_4_filter_150_qs)
@@ -6473,8 +6475,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_151 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_151_we),
@@ -6482,11 +6484,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[151].q ),
+ .q (reg2hw.cmd_filter[151].q),
// to register interface (read)
.qs (cmd_filter_4_filter_151_qs)
@@ -6499,8 +6501,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_152 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_152_we),
@@ -6508,11 +6510,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[152].q ),
+ .q (reg2hw.cmd_filter[152].q),
// to register interface (read)
.qs (cmd_filter_4_filter_152_qs)
@@ -6525,8 +6527,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_153 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_153_we),
@@ -6534,11 +6536,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[153].q ),
+ .q (reg2hw.cmd_filter[153].q),
// to register interface (read)
.qs (cmd_filter_4_filter_153_qs)
@@ -6551,8 +6553,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_154 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_154_we),
@@ -6560,11 +6562,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[154].q ),
+ .q (reg2hw.cmd_filter[154].q),
// to register interface (read)
.qs (cmd_filter_4_filter_154_qs)
@@ -6577,8 +6579,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_155 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_155_we),
@@ -6586,11 +6588,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[155].q ),
+ .q (reg2hw.cmd_filter[155].q),
// to register interface (read)
.qs (cmd_filter_4_filter_155_qs)
@@ -6603,8 +6605,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_156 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_156_we),
@@ -6612,11 +6614,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[156].q ),
+ .q (reg2hw.cmd_filter[156].q),
// to register interface (read)
.qs (cmd_filter_4_filter_156_qs)
@@ -6629,8 +6631,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_157 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_157_we),
@@ -6638,11 +6640,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[157].q ),
+ .q (reg2hw.cmd_filter[157].q),
// to register interface (read)
.qs (cmd_filter_4_filter_157_qs)
@@ -6655,8 +6657,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_158 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_158_we),
@@ -6664,11 +6666,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[158].q ),
+ .q (reg2hw.cmd_filter[158].q),
// to register interface (read)
.qs (cmd_filter_4_filter_158_qs)
@@ -6681,8 +6683,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_4_filter_159 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_4_filter_159_we),
@@ -6690,11 +6692,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[159].q ),
+ .q (reg2hw.cmd_filter[159].q),
// to register interface (read)
.qs (cmd_filter_4_filter_159_qs)
@@ -6710,8 +6712,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_160 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_160_we),
@@ -6719,11 +6721,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[160].q ),
+ .q (reg2hw.cmd_filter[160].q),
// to register interface (read)
.qs (cmd_filter_5_filter_160_qs)
@@ -6736,8 +6738,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_161 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_161_we),
@@ -6745,11 +6747,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[161].q ),
+ .q (reg2hw.cmd_filter[161].q),
// to register interface (read)
.qs (cmd_filter_5_filter_161_qs)
@@ -6762,8 +6764,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_162 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_162_we),
@@ -6771,11 +6773,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[162].q ),
+ .q (reg2hw.cmd_filter[162].q),
// to register interface (read)
.qs (cmd_filter_5_filter_162_qs)
@@ -6788,8 +6790,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_163 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_163_we),
@@ -6797,11 +6799,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[163].q ),
+ .q (reg2hw.cmd_filter[163].q),
// to register interface (read)
.qs (cmd_filter_5_filter_163_qs)
@@ -6814,8 +6816,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_164 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_164_we),
@@ -6823,11 +6825,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[164].q ),
+ .q (reg2hw.cmd_filter[164].q),
// to register interface (read)
.qs (cmd_filter_5_filter_164_qs)
@@ -6840,8 +6842,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_165 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_165_we),
@@ -6849,11 +6851,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[165].q ),
+ .q (reg2hw.cmd_filter[165].q),
// to register interface (read)
.qs (cmd_filter_5_filter_165_qs)
@@ -6866,8 +6868,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_166 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_166_we),
@@ -6875,11 +6877,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[166].q ),
+ .q (reg2hw.cmd_filter[166].q),
// to register interface (read)
.qs (cmd_filter_5_filter_166_qs)
@@ -6892,8 +6894,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_167 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_167_we),
@@ -6901,11 +6903,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[167].q ),
+ .q (reg2hw.cmd_filter[167].q),
// to register interface (read)
.qs (cmd_filter_5_filter_167_qs)
@@ -6918,8 +6920,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_168 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_168_we),
@@ -6927,11 +6929,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[168].q ),
+ .q (reg2hw.cmd_filter[168].q),
// to register interface (read)
.qs (cmd_filter_5_filter_168_qs)
@@ -6944,8 +6946,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_169 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_169_we),
@@ -6953,11 +6955,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[169].q ),
+ .q (reg2hw.cmd_filter[169].q),
// to register interface (read)
.qs (cmd_filter_5_filter_169_qs)
@@ -6970,8 +6972,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_170 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_170_we),
@@ -6979,11 +6981,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[170].q ),
+ .q (reg2hw.cmd_filter[170].q),
// to register interface (read)
.qs (cmd_filter_5_filter_170_qs)
@@ -6996,8 +6998,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_171 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_171_we),
@@ -7005,11 +7007,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[171].q ),
+ .q (reg2hw.cmd_filter[171].q),
// to register interface (read)
.qs (cmd_filter_5_filter_171_qs)
@@ -7022,8 +7024,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_172 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_172_we),
@@ -7031,11 +7033,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[172].q ),
+ .q (reg2hw.cmd_filter[172].q),
// to register interface (read)
.qs (cmd_filter_5_filter_172_qs)
@@ -7048,8 +7050,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_173 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_173_we),
@@ -7057,11 +7059,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[173].q ),
+ .q (reg2hw.cmd_filter[173].q),
// to register interface (read)
.qs (cmd_filter_5_filter_173_qs)
@@ -7074,8 +7076,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_174 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_174_we),
@@ -7083,11 +7085,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[174].q ),
+ .q (reg2hw.cmd_filter[174].q),
// to register interface (read)
.qs (cmd_filter_5_filter_174_qs)
@@ -7100,8 +7102,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_175 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_175_we),
@@ -7109,11 +7111,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[175].q ),
+ .q (reg2hw.cmd_filter[175].q),
// to register interface (read)
.qs (cmd_filter_5_filter_175_qs)
@@ -7126,8 +7128,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_176 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_176_we),
@@ -7135,11 +7137,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[176].q ),
+ .q (reg2hw.cmd_filter[176].q),
// to register interface (read)
.qs (cmd_filter_5_filter_176_qs)
@@ -7152,8 +7154,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_177 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_177_we),
@@ -7161,11 +7163,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[177].q ),
+ .q (reg2hw.cmd_filter[177].q),
// to register interface (read)
.qs (cmd_filter_5_filter_177_qs)
@@ -7178,8 +7180,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_178 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_178_we),
@@ -7187,11 +7189,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[178].q ),
+ .q (reg2hw.cmd_filter[178].q),
// to register interface (read)
.qs (cmd_filter_5_filter_178_qs)
@@ -7204,8 +7206,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_179 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_179_we),
@@ -7213,11 +7215,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[179].q ),
+ .q (reg2hw.cmd_filter[179].q),
// to register interface (read)
.qs (cmd_filter_5_filter_179_qs)
@@ -7230,8 +7232,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_180 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_180_we),
@@ -7239,11 +7241,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[180].q ),
+ .q (reg2hw.cmd_filter[180].q),
// to register interface (read)
.qs (cmd_filter_5_filter_180_qs)
@@ -7256,8 +7258,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_181 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_181_we),
@@ -7265,11 +7267,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[181].q ),
+ .q (reg2hw.cmd_filter[181].q),
// to register interface (read)
.qs (cmd_filter_5_filter_181_qs)
@@ -7282,8 +7284,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_182 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_182_we),
@@ -7291,11 +7293,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[182].q ),
+ .q (reg2hw.cmd_filter[182].q),
// to register interface (read)
.qs (cmd_filter_5_filter_182_qs)
@@ -7308,8 +7310,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_183 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_183_we),
@@ -7317,11 +7319,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[183].q ),
+ .q (reg2hw.cmd_filter[183].q),
// to register interface (read)
.qs (cmd_filter_5_filter_183_qs)
@@ -7334,8 +7336,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_184 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_184_we),
@@ -7343,11 +7345,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[184].q ),
+ .q (reg2hw.cmd_filter[184].q),
// to register interface (read)
.qs (cmd_filter_5_filter_184_qs)
@@ -7360,8 +7362,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_185 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_185_we),
@@ -7369,11 +7371,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[185].q ),
+ .q (reg2hw.cmd_filter[185].q),
// to register interface (read)
.qs (cmd_filter_5_filter_185_qs)
@@ -7386,8 +7388,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_186 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_186_we),
@@ -7395,11 +7397,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[186].q ),
+ .q (reg2hw.cmd_filter[186].q),
// to register interface (read)
.qs (cmd_filter_5_filter_186_qs)
@@ -7412,8 +7414,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_187 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_187_we),
@@ -7421,11 +7423,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[187].q ),
+ .q (reg2hw.cmd_filter[187].q),
// to register interface (read)
.qs (cmd_filter_5_filter_187_qs)
@@ -7438,8 +7440,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_188 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_188_we),
@@ -7447,11 +7449,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[188].q ),
+ .q (reg2hw.cmd_filter[188].q),
// to register interface (read)
.qs (cmd_filter_5_filter_188_qs)
@@ -7464,8 +7466,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_189 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_189_we),
@@ -7473,11 +7475,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[189].q ),
+ .q (reg2hw.cmd_filter[189].q),
// to register interface (read)
.qs (cmd_filter_5_filter_189_qs)
@@ -7490,8 +7492,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_190 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_190_we),
@@ -7499,11 +7501,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[190].q ),
+ .q (reg2hw.cmd_filter[190].q),
// to register interface (read)
.qs (cmd_filter_5_filter_190_qs)
@@ -7516,8 +7518,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_5_filter_191 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_5_filter_191_we),
@@ -7525,11 +7527,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[191].q ),
+ .q (reg2hw.cmd_filter[191].q),
// to register interface (read)
.qs (cmd_filter_5_filter_191_qs)
@@ -7545,8 +7547,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_192 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_192_we),
@@ -7554,11 +7556,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[192].q ),
+ .q (reg2hw.cmd_filter[192].q),
// to register interface (read)
.qs (cmd_filter_6_filter_192_qs)
@@ -7571,8 +7573,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_193 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_193_we),
@@ -7580,11 +7582,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[193].q ),
+ .q (reg2hw.cmd_filter[193].q),
// to register interface (read)
.qs (cmd_filter_6_filter_193_qs)
@@ -7597,8 +7599,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_194 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_194_we),
@@ -7606,11 +7608,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[194].q ),
+ .q (reg2hw.cmd_filter[194].q),
// to register interface (read)
.qs (cmd_filter_6_filter_194_qs)
@@ -7623,8 +7625,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_195 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_195_we),
@@ -7632,11 +7634,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[195].q ),
+ .q (reg2hw.cmd_filter[195].q),
// to register interface (read)
.qs (cmd_filter_6_filter_195_qs)
@@ -7649,8 +7651,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_196 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_196_we),
@@ -7658,11 +7660,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[196].q ),
+ .q (reg2hw.cmd_filter[196].q),
// to register interface (read)
.qs (cmd_filter_6_filter_196_qs)
@@ -7675,8 +7677,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_197 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_197_we),
@@ -7684,11 +7686,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[197].q ),
+ .q (reg2hw.cmd_filter[197].q),
// to register interface (read)
.qs (cmd_filter_6_filter_197_qs)
@@ -7701,8 +7703,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_198 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_198_we),
@@ -7710,11 +7712,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[198].q ),
+ .q (reg2hw.cmd_filter[198].q),
// to register interface (read)
.qs (cmd_filter_6_filter_198_qs)
@@ -7727,8 +7729,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_199 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_199_we),
@@ -7736,11 +7738,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[199].q ),
+ .q (reg2hw.cmd_filter[199].q),
// to register interface (read)
.qs (cmd_filter_6_filter_199_qs)
@@ -7753,8 +7755,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_200 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_200_we),
@@ -7762,11 +7764,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[200].q ),
+ .q (reg2hw.cmd_filter[200].q),
// to register interface (read)
.qs (cmd_filter_6_filter_200_qs)
@@ -7779,8 +7781,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_201 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_201_we),
@@ -7788,11 +7790,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[201].q ),
+ .q (reg2hw.cmd_filter[201].q),
// to register interface (read)
.qs (cmd_filter_6_filter_201_qs)
@@ -7805,8 +7807,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_202 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_202_we),
@@ -7814,11 +7816,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[202].q ),
+ .q (reg2hw.cmd_filter[202].q),
// to register interface (read)
.qs (cmd_filter_6_filter_202_qs)
@@ -7831,8 +7833,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_203 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_203_we),
@@ -7840,11 +7842,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[203].q ),
+ .q (reg2hw.cmd_filter[203].q),
// to register interface (read)
.qs (cmd_filter_6_filter_203_qs)
@@ -7857,8 +7859,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_204 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_204_we),
@@ -7866,11 +7868,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[204].q ),
+ .q (reg2hw.cmd_filter[204].q),
// to register interface (read)
.qs (cmd_filter_6_filter_204_qs)
@@ -7883,8 +7885,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_205 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_205_we),
@@ -7892,11 +7894,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[205].q ),
+ .q (reg2hw.cmd_filter[205].q),
// to register interface (read)
.qs (cmd_filter_6_filter_205_qs)
@@ -7909,8 +7911,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_206 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_206_we),
@@ -7918,11 +7920,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[206].q ),
+ .q (reg2hw.cmd_filter[206].q),
// to register interface (read)
.qs (cmd_filter_6_filter_206_qs)
@@ -7935,8 +7937,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_207 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_207_we),
@@ -7944,11 +7946,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[207].q ),
+ .q (reg2hw.cmd_filter[207].q),
// to register interface (read)
.qs (cmd_filter_6_filter_207_qs)
@@ -7961,8 +7963,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_208 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_208_we),
@@ -7970,11 +7972,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[208].q ),
+ .q (reg2hw.cmd_filter[208].q),
// to register interface (read)
.qs (cmd_filter_6_filter_208_qs)
@@ -7987,8 +7989,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_209 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_209_we),
@@ -7996,11 +7998,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[209].q ),
+ .q (reg2hw.cmd_filter[209].q),
// to register interface (read)
.qs (cmd_filter_6_filter_209_qs)
@@ -8013,8 +8015,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_210 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_210_we),
@@ -8022,11 +8024,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[210].q ),
+ .q (reg2hw.cmd_filter[210].q),
// to register interface (read)
.qs (cmd_filter_6_filter_210_qs)
@@ -8039,8 +8041,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_211 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_211_we),
@@ -8048,11 +8050,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[211].q ),
+ .q (reg2hw.cmd_filter[211].q),
// to register interface (read)
.qs (cmd_filter_6_filter_211_qs)
@@ -8065,8 +8067,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_212 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_212_we),
@@ -8074,11 +8076,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[212].q ),
+ .q (reg2hw.cmd_filter[212].q),
// to register interface (read)
.qs (cmd_filter_6_filter_212_qs)
@@ -8091,8 +8093,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_213 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_213_we),
@@ -8100,11 +8102,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[213].q ),
+ .q (reg2hw.cmd_filter[213].q),
// to register interface (read)
.qs (cmd_filter_6_filter_213_qs)
@@ -8117,8 +8119,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_214 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_214_we),
@@ -8126,11 +8128,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[214].q ),
+ .q (reg2hw.cmd_filter[214].q),
// to register interface (read)
.qs (cmd_filter_6_filter_214_qs)
@@ -8143,8 +8145,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_215 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_215_we),
@@ -8152,11 +8154,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[215].q ),
+ .q (reg2hw.cmd_filter[215].q),
// to register interface (read)
.qs (cmd_filter_6_filter_215_qs)
@@ -8169,8 +8171,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_216 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_216_we),
@@ -8178,11 +8180,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[216].q ),
+ .q (reg2hw.cmd_filter[216].q),
// to register interface (read)
.qs (cmd_filter_6_filter_216_qs)
@@ -8195,8 +8197,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_217 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_217_we),
@@ -8204,11 +8206,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[217].q ),
+ .q (reg2hw.cmd_filter[217].q),
// to register interface (read)
.qs (cmd_filter_6_filter_217_qs)
@@ -8221,8 +8223,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_218 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_218_we),
@@ -8230,11 +8232,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[218].q ),
+ .q (reg2hw.cmd_filter[218].q),
// to register interface (read)
.qs (cmd_filter_6_filter_218_qs)
@@ -8247,8 +8249,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_219 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_219_we),
@@ -8256,11 +8258,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[219].q ),
+ .q (reg2hw.cmd_filter[219].q),
// to register interface (read)
.qs (cmd_filter_6_filter_219_qs)
@@ -8273,8 +8275,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_220 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_220_we),
@@ -8282,11 +8284,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[220].q ),
+ .q (reg2hw.cmd_filter[220].q),
// to register interface (read)
.qs (cmd_filter_6_filter_220_qs)
@@ -8299,8 +8301,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_221 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_221_we),
@@ -8308,11 +8310,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[221].q ),
+ .q (reg2hw.cmd_filter[221].q),
// to register interface (read)
.qs (cmd_filter_6_filter_221_qs)
@@ -8325,8 +8327,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_222 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_222_we),
@@ -8334,11 +8336,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[222].q ),
+ .q (reg2hw.cmd_filter[222].q),
// to register interface (read)
.qs (cmd_filter_6_filter_222_qs)
@@ -8351,8 +8353,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_6_filter_223 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_6_filter_223_we),
@@ -8360,11 +8362,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[223].q ),
+ .q (reg2hw.cmd_filter[223].q),
// to register interface (read)
.qs (cmd_filter_6_filter_223_qs)
@@ -8380,8 +8382,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_224 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_224_we),
@@ -8389,11 +8391,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[224].q ),
+ .q (reg2hw.cmd_filter[224].q),
// to register interface (read)
.qs (cmd_filter_7_filter_224_qs)
@@ -8406,8 +8408,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_225 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_225_we),
@@ -8415,11 +8417,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[225].q ),
+ .q (reg2hw.cmd_filter[225].q),
// to register interface (read)
.qs (cmd_filter_7_filter_225_qs)
@@ -8432,8 +8434,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_226 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_226_we),
@@ -8441,11 +8443,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[226].q ),
+ .q (reg2hw.cmd_filter[226].q),
// to register interface (read)
.qs (cmd_filter_7_filter_226_qs)
@@ -8458,8 +8460,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_227 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_227_we),
@@ -8467,11 +8469,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[227].q ),
+ .q (reg2hw.cmd_filter[227].q),
// to register interface (read)
.qs (cmd_filter_7_filter_227_qs)
@@ -8484,8 +8486,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_228 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_228_we),
@@ -8493,11 +8495,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[228].q ),
+ .q (reg2hw.cmd_filter[228].q),
// to register interface (read)
.qs (cmd_filter_7_filter_228_qs)
@@ -8510,8 +8512,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_229 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_229_we),
@@ -8519,11 +8521,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[229].q ),
+ .q (reg2hw.cmd_filter[229].q),
// to register interface (read)
.qs (cmd_filter_7_filter_229_qs)
@@ -8536,8 +8538,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_230 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_230_we),
@@ -8545,11 +8547,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[230].q ),
+ .q (reg2hw.cmd_filter[230].q),
// to register interface (read)
.qs (cmd_filter_7_filter_230_qs)
@@ -8562,8 +8564,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_231 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_231_we),
@@ -8571,11 +8573,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[231].q ),
+ .q (reg2hw.cmd_filter[231].q),
// to register interface (read)
.qs (cmd_filter_7_filter_231_qs)
@@ -8588,8 +8590,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_232 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_232_we),
@@ -8597,11 +8599,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[232].q ),
+ .q (reg2hw.cmd_filter[232].q),
// to register interface (read)
.qs (cmd_filter_7_filter_232_qs)
@@ -8614,8 +8616,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_233 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_233_we),
@@ -8623,11 +8625,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[233].q ),
+ .q (reg2hw.cmd_filter[233].q),
// to register interface (read)
.qs (cmd_filter_7_filter_233_qs)
@@ -8640,8 +8642,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_234 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_234_we),
@@ -8649,11 +8651,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[234].q ),
+ .q (reg2hw.cmd_filter[234].q),
// to register interface (read)
.qs (cmd_filter_7_filter_234_qs)
@@ -8666,8 +8668,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_235 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_235_we),
@@ -8675,11 +8677,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[235].q ),
+ .q (reg2hw.cmd_filter[235].q),
// to register interface (read)
.qs (cmd_filter_7_filter_235_qs)
@@ -8692,8 +8694,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_236 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_236_we),
@@ -8701,11 +8703,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[236].q ),
+ .q (reg2hw.cmd_filter[236].q),
// to register interface (read)
.qs (cmd_filter_7_filter_236_qs)
@@ -8718,8 +8720,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_237 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_237_we),
@@ -8727,11 +8729,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[237].q ),
+ .q (reg2hw.cmd_filter[237].q),
// to register interface (read)
.qs (cmd_filter_7_filter_237_qs)
@@ -8744,8 +8746,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_238 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_238_we),
@@ -8753,11 +8755,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[238].q ),
+ .q (reg2hw.cmd_filter[238].q),
// to register interface (read)
.qs (cmd_filter_7_filter_238_qs)
@@ -8770,8 +8772,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_239 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_239_we),
@@ -8779,11 +8781,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[239].q ),
+ .q (reg2hw.cmd_filter[239].q),
// to register interface (read)
.qs (cmd_filter_7_filter_239_qs)
@@ -8796,8 +8798,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_240 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_240_we),
@@ -8805,11 +8807,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[240].q ),
+ .q (reg2hw.cmd_filter[240].q),
// to register interface (read)
.qs (cmd_filter_7_filter_240_qs)
@@ -8822,8 +8824,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_241 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_241_we),
@@ -8831,11 +8833,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[241].q ),
+ .q (reg2hw.cmd_filter[241].q),
// to register interface (read)
.qs (cmd_filter_7_filter_241_qs)
@@ -8848,8 +8850,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_242 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_242_we),
@@ -8857,11 +8859,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[242].q ),
+ .q (reg2hw.cmd_filter[242].q),
// to register interface (read)
.qs (cmd_filter_7_filter_242_qs)
@@ -8874,8 +8876,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_243 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_243_we),
@@ -8883,11 +8885,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[243].q ),
+ .q (reg2hw.cmd_filter[243].q),
// to register interface (read)
.qs (cmd_filter_7_filter_243_qs)
@@ -8900,8 +8902,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_244 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_244_we),
@@ -8909,11 +8911,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[244].q ),
+ .q (reg2hw.cmd_filter[244].q),
// to register interface (read)
.qs (cmd_filter_7_filter_244_qs)
@@ -8926,8 +8928,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_245 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_245_we),
@@ -8935,11 +8937,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[245].q ),
+ .q (reg2hw.cmd_filter[245].q),
// to register interface (read)
.qs (cmd_filter_7_filter_245_qs)
@@ -8952,8 +8954,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_246 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_246_we),
@@ -8961,11 +8963,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[246].q ),
+ .q (reg2hw.cmd_filter[246].q),
// to register interface (read)
.qs (cmd_filter_7_filter_246_qs)
@@ -8978,8 +8980,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_247 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_247_we),
@@ -8987,11 +8989,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[247].q ),
+ .q (reg2hw.cmd_filter[247].q),
// to register interface (read)
.qs (cmd_filter_7_filter_247_qs)
@@ -9004,8 +9006,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_248 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_248_we),
@@ -9013,11 +9015,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[248].q ),
+ .q (reg2hw.cmd_filter[248].q),
// to register interface (read)
.qs (cmd_filter_7_filter_248_qs)
@@ -9030,8 +9032,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_249 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_249_we),
@@ -9039,11 +9041,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[249].q ),
+ .q (reg2hw.cmd_filter[249].q),
// to register interface (read)
.qs (cmd_filter_7_filter_249_qs)
@@ -9056,8 +9058,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_250 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_250_we),
@@ -9065,11 +9067,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[250].q ),
+ .q (reg2hw.cmd_filter[250].q),
// to register interface (read)
.qs (cmd_filter_7_filter_250_qs)
@@ -9082,8 +9084,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_251 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_251_we),
@@ -9091,11 +9093,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[251].q ),
+ .q (reg2hw.cmd_filter[251].q),
// to register interface (read)
.qs (cmd_filter_7_filter_251_qs)
@@ -9108,8 +9110,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_252 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_252_we),
@@ -9117,11 +9119,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[252].q ),
+ .q (reg2hw.cmd_filter[252].q),
// to register interface (read)
.qs (cmd_filter_7_filter_252_qs)
@@ -9134,8 +9136,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_253 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_253_we),
@@ -9143,11 +9145,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[253].q ),
+ .q (reg2hw.cmd_filter[253].q),
// to register interface (read)
.qs (cmd_filter_7_filter_253_qs)
@@ -9160,8 +9162,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_254 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_254_we),
@@ -9169,11 +9171,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[254].q ),
+ .q (reg2hw.cmd_filter[254].q),
// to register interface (read)
.qs (cmd_filter_7_filter_254_qs)
@@ -9186,8 +9188,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_filter_7_filter_255 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_filter_7_filter_255_we),
@@ -9195,11 +9197,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_filter[255].q ),
+ .q (reg2hw.cmd_filter[255].q),
// to register interface (read)
.qs (cmd_filter_7_filter_255_qs)
@@ -9214,8 +9216,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_addr_swap_mask (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (addr_swap_mask_we),
@@ -9223,11 +9225,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.addr_swap_mask.q ),
+ .q (reg2hw.addr_swap_mask.q),
// to register interface (read)
.qs (addr_swap_mask_qs)
@@ -9241,8 +9243,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_addr_swap_data (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (addr_swap_data_we),
@@ -9250,11 +9252,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.addr_swap_data.q ),
+ .q (reg2hw.addr_swap_data.q),
// to register interface (read)
.qs (addr_swap_data_qs)
@@ -9271,8 +9273,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_0_opcode_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_0_opcode_0_we),
@@ -9280,11 +9282,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[0].opcode.q ),
+ .q (reg2hw.cmd_info[0].opcode.q),
// to register interface (read)
.qs (cmd_info_0_opcode_0_qs)
@@ -9297,8 +9299,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_0_addr_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_0_addr_en_0_we),
@@ -9306,11 +9308,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[0].addr_en.q ),
+ .q (reg2hw.cmd_info[0].addr_en.q),
// to register interface (read)
.qs (cmd_info_0_addr_en_0_qs)
@@ -9323,8 +9325,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_0_addr_swap_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_0_addr_swap_en_0_we),
@@ -9332,11 +9334,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[0].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[0].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_0_addr_swap_en_0_qs)
@@ -9349,8 +9351,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_0_addr_4b_affected_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_0_addr_4b_affected_0_we),
@@ -9358,11 +9360,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[0].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[0].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_0_addr_4b_affected_0_qs)
@@ -9375,8 +9377,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_0_dummy_size_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_0_dummy_size_0_we),
@@ -9384,11 +9386,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[0].dummy_size.q ),
+ .q (reg2hw.cmd_info[0].dummy_size.q),
// to register interface (read)
.qs (cmd_info_0_dummy_size_0_qs)
@@ -9401,8 +9403,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_0_dummy_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_0_dummy_en_0_we),
@@ -9410,11 +9412,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[0].dummy_en.q ),
+ .q (reg2hw.cmd_info[0].dummy_en.q),
// to register interface (read)
.qs (cmd_info_0_dummy_en_0_qs)
@@ -9427,8 +9429,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_0_payload_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_0_payload_en_0_we),
@@ -9436,11 +9438,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[0].payload_en.q ),
+ .q (reg2hw.cmd_info[0].payload_en.q),
// to register interface (read)
.qs (cmd_info_0_payload_en_0_qs)
@@ -9453,8 +9455,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_0_payload_dir_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_0_payload_dir_0_we),
@@ -9462,11 +9464,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[0].payload_dir.q ),
+ .q (reg2hw.cmd_info[0].payload_dir.q),
// to register interface (read)
.qs (cmd_info_0_payload_dir_0_qs)
@@ -9482,8 +9484,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_1_opcode_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_1_opcode_1_we),
@@ -9491,11 +9493,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[1].opcode.q ),
+ .q (reg2hw.cmd_info[1].opcode.q),
// to register interface (read)
.qs (cmd_info_1_opcode_1_qs)
@@ -9508,8 +9510,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_1_addr_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_1_addr_en_1_we),
@@ -9517,11 +9519,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[1].addr_en.q ),
+ .q (reg2hw.cmd_info[1].addr_en.q),
// to register interface (read)
.qs (cmd_info_1_addr_en_1_qs)
@@ -9534,8 +9536,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_1_addr_swap_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_1_addr_swap_en_1_we),
@@ -9543,11 +9545,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[1].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[1].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_1_addr_swap_en_1_qs)
@@ -9560,8 +9562,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_1_addr_4b_affected_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_1_addr_4b_affected_1_we),
@@ -9569,11 +9571,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[1].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[1].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_1_addr_4b_affected_1_qs)
@@ -9586,8 +9588,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_1_dummy_size_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_1_dummy_size_1_we),
@@ -9595,11 +9597,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[1].dummy_size.q ),
+ .q (reg2hw.cmd_info[1].dummy_size.q),
// to register interface (read)
.qs (cmd_info_1_dummy_size_1_qs)
@@ -9612,8 +9614,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_1_dummy_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_1_dummy_en_1_we),
@@ -9621,11 +9623,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[1].dummy_en.q ),
+ .q (reg2hw.cmd_info[1].dummy_en.q),
// to register interface (read)
.qs (cmd_info_1_dummy_en_1_qs)
@@ -9638,8 +9640,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_1_payload_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_1_payload_en_1_we),
@@ -9647,11 +9649,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[1].payload_en.q ),
+ .q (reg2hw.cmd_info[1].payload_en.q),
// to register interface (read)
.qs (cmd_info_1_payload_en_1_qs)
@@ -9664,8 +9666,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_1_payload_dir_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_1_payload_dir_1_we),
@@ -9673,11 +9675,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[1].payload_dir.q ),
+ .q (reg2hw.cmd_info[1].payload_dir.q),
// to register interface (read)
.qs (cmd_info_1_payload_dir_1_qs)
@@ -9693,8 +9695,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_2_opcode_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_2_opcode_2_we),
@@ -9702,11 +9704,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[2].opcode.q ),
+ .q (reg2hw.cmd_info[2].opcode.q),
// to register interface (read)
.qs (cmd_info_2_opcode_2_qs)
@@ -9719,8 +9721,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_2_addr_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_2_addr_en_2_we),
@@ -9728,11 +9730,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[2].addr_en.q ),
+ .q (reg2hw.cmd_info[2].addr_en.q),
// to register interface (read)
.qs (cmd_info_2_addr_en_2_qs)
@@ -9745,8 +9747,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_2_addr_swap_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_2_addr_swap_en_2_we),
@@ -9754,11 +9756,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[2].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[2].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_2_addr_swap_en_2_qs)
@@ -9771,8 +9773,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_2_addr_4b_affected_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_2_addr_4b_affected_2_we),
@@ -9780,11 +9782,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[2].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[2].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_2_addr_4b_affected_2_qs)
@@ -9797,8 +9799,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_2_dummy_size_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_2_dummy_size_2_we),
@@ -9806,11 +9808,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[2].dummy_size.q ),
+ .q (reg2hw.cmd_info[2].dummy_size.q),
// to register interface (read)
.qs (cmd_info_2_dummy_size_2_qs)
@@ -9823,8 +9825,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_2_dummy_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_2_dummy_en_2_we),
@@ -9832,11 +9834,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[2].dummy_en.q ),
+ .q (reg2hw.cmd_info[2].dummy_en.q),
// to register interface (read)
.qs (cmd_info_2_dummy_en_2_qs)
@@ -9849,8 +9851,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_2_payload_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_2_payload_en_2_we),
@@ -9858,11 +9860,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[2].payload_en.q ),
+ .q (reg2hw.cmd_info[2].payload_en.q),
// to register interface (read)
.qs (cmd_info_2_payload_en_2_qs)
@@ -9875,8 +9877,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_2_payload_dir_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_2_payload_dir_2_we),
@@ -9884,11 +9886,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[2].payload_dir.q ),
+ .q (reg2hw.cmd_info[2].payload_dir.q),
// to register interface (read)
.qs (cmd_info_2_payload_dir_2_qs)
@@ -9904,8 +9906,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_3_opcode_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_3_opcode_3_we),
@@ -9913,11 +9915,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[3].opcode.q ),
+ .q (reg2hw.cmd_info[3].opcode.q),
// to register interface (read)
.qs (cmd_info_3_opcode_3_qs)
@@ -9930,8 +9932,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_3_addr_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_3_addr_en_3_we),
@@ -9939,11 +9941,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[3].addr_en.q ),
+ .q (reg2hw.cmd_info[3].addr_en.q),
// to register interface (read)
.qs (cmd_info_3_addr_en_3_qs)
@@ -9956,8 +9958,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_3_addr_swap_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_3_addr_swap_en_3_we),
@@ -9965,11 +9967,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[3].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[3].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_3_addr_swap_en_3_qs)
@@ -9982,8 +9984,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_3_addr_4b_affected_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_3_addr_4b_affected_3_we),
@@ -9991,11 +9993,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[3].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[3].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_3_addr_4b_affected_3_qs)
@@ -10008,8 +10010,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_3_dummy_size_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_3_dummy_size_3_we),
@@ -10017,11 +10019,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[3].dummy_size.q ),
+ .q (reg2hw.cmd_info[3].dummy_size.q),
// to register interface (read)
.qs (cmd_info_3_dummy_size_3_qs)
@@ -10034,8 +10036,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_3_dummy_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_3_dummy_en_3_we),
@@ -10043,11 +10045,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[3].dummy_en.q ),
+ .q (reg2hw.cmd_info[3].dummy_en.q),
// to register interface (read)
.qs (cmd_info_3_dummy_en_3_qs)
@@ -10060,8 +10062,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_3_payload_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_3_payload_en_3_we),
@@ -10069,11 +10071,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[3].payload_en.q ),
+ .q (reg2hw.cmd_info[3].payload_en.q),
// to register interface (read)
.qs (cmd_info_3_payload_en_3_qs)
@@ -10086,8 +10088,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_3_payload_dir_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_3_payload_dir_3_we),
@@ -10095,11 +10097,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[3].payload_dir.q ),
+ .q (reg2hw.cmd_info[3].payload_dir.q),
// to register interface (read)
.qs (cmd_info_3_payload_dir_3_qs)
@@ -10115,8 +10117,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_4_opcode_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_4_opcode_4_we),
@@ -10124,11 +10126,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[4].opcode.q ),
+ .q (reg2hw.cmd_info[4].opcode.q),
// to register interface (read)
.qs (cmd_info_4_opcode_4_qs)
@@ -10141,8 +10143,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_4_addr_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_4_addr_en_4_we),
@@ -10150,11 +10152,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[4].addr_en.q ),
+ .q (reg2hw.cmd_info[4].addr_en.q),
// to register interface (read)
.qs (cmd_info_4_addr_en_4_qs)
@@ -10167,8 +10169,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_4_addr_swap_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_4_addr_swap_en_4_we),
@@ -10176,11 +10178,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[4].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[4].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_4_addr_swap_en_4_qs)
@@ -10193,8 +10195,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_4_addr_4b_affected_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_4_addr_4b_affected_4_we),
@@ -10202,11 +10204,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[4].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[4].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_4_addr_4b_affected_4_qs)
@@ -10219,8 +10221,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_4_dummy_size_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_4_dummy_size_4_we),
@@ -10228,11 +10230,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[4].dummy_size.q ),
+ .q (reg2hw.cmd_info[4].dummy_size.q),
// to register interface (read)
.qs (cmd_info_4_dummy_size_4_qs)
@@ -10245,8 +10247,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_4_dummy_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_4_dummy_en_4_we),
@@ -10254,11 +10256,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[4].dummy_en.q ),
+ .q (reg2hw.cmd_info[4].dummy_en.q),
// to register interface (read)
.qs (cmd_info_4_dummy_en_4_qs)
@@ -10271,8 +10273,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_4_payload_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_4_payload_en_4_we),
@@ -10280,11 +10282,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[4].payload_en.q ),
+ .q (reg2hw.cmd_info[4].payload_en.q),
// to register interface (read)
.qs (cmd_info_4_payload_en_4_qs)
@@ -10297,8 +10299,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_4_payload_dir_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_4_payload_dir_4_we),
@@ -10306,11 +10308,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[4].payload_dir.q ),
+ .q (reg2hw.cmd_info[4].payload_dir.q),
// to register interface (read)
.qs (cmd_info_4_payload_dir_4_qs)
@@ -10326,8 +10328,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_5_opcode_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_5_opcode_5_we),
@@ -10335,11 +10337,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[5].opcode.q ),
+ .q (reg2hw.cmd_info[5].opcode.q),
// to register interface (read)
.qs (cmd_info_5_opcode_5_qs)
@@ -10352,8 +10354,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_5_addr_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_5_addr_en_5_we),
@@ -10361,11 +10363,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[5].addr_en.q ),
+ .q (reg2hw.cmd_info[5].addr_en.q),
// to register interface (read)
.qs (cmd_info_5_addr_en_5_qs)
@@ -10378,8 +10380,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_5_addr_swap_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_5_addr_swap_en_5_we),
@@ -10387,11 +10389,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[5].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[5].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_5_addr_swap_en_5_qs)
@@ -10404,8 +10406,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_5_addr_4b_affected_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_5_addr_4b_affected_5_we),
@@ -10413,11 +10415,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[5].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[5].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_5_addr_4b_affected_5_qs)
@@ -10430,8 +10432,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_5_dummy_size_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_5_dummy_size_5_we),
@@ -10439,11 +10441,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[5].dummy_size.q ),
+ .q (reg2hw.cmd_info[5].dummy_size.q),
// to register interface (read)
.qs (cmd_info_5_dummy_size_5_qs)
@@ -10456,8 +10458,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_5_dummy_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_5_dummy_en_5_we),
@@ -10465,11 +10467,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[5].dummy_en.q ),
+ .q (reg2hw.cmd_info[5].dummy_en.q),
// to register interface (read)
.qs (cmd_info_5_dummy_en_5_qs)
@@ -10482,8 +10484,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_5_payload_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_5_payload_en_5_we),
@@ -10491,11 +10493,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[5].payload_en.q ),
+ .q (reg2hw.cmd_info[5].payload_en.q),
// to register interface (read)
.qs (cmd_info_5_payload_en_5_qs)
@@ -10508,8 +10510,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_5_payload_dir_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_5_payload_dir_5_we),
@@ -10517,11 +10519,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[5].payload_dir.q ),
+ .q (reg2hw.cmd_info[5].payload_dir.q),
// to register interface (read)
.qs (cmd_info_5_payload_dir_5_qs)
@@ -10537,8 +10539,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_6_opcode_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_6_opcode_6_we),
@@ -10546,11 +10548,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[6].opcode.q ),
+ .q (reg2hw.cmd_info[6].opcode.q),
// to register interface (read)
.qs (cmd_info_6_opcode_6_qs)
@@ -10563,8 +10565,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_6_addr_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_6_addr_en_6_we),
@@ -10572,11 +10574,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[6].addr_en.q ),
+ .q (reg2hw.cmd_info[6].addr_en.q),
// to register interface (read)
.qs (cmd_info_6_addr_en_6_qs)
@@ -10589,8 +10591,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_6_addr_swap_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_6_addr_swap_en_6_we),
@@ -10598,11 +10600,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[6].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[6].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_6_addr_swap_en_6_qs)
@@ -10615,8 +10617,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_6_addr_4b_affected_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_6_addr_4b_affected_6_we),
@@ -10624,11 +10626,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[6].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[6].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_6_addr_4b_affected_6_qs)
@@ -10641,8 +10643,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_6_dummy_size_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_6_dummy_size_6_we),
@@ -10650,11 +10652,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[6].dummy_size.q ),
+ .q (reg2hw.cmd_info[6].dummy_size.q),
// to register interface (read)
.qs (cmd_info_6_dummy_size_6_qs)
@@ -10667,8 +10669,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_6_dummy_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_6_dummy_en_6_we),
@@ -10676,11 +10678,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[6].dummy_en.q ),
+ .q (reg2hw.cmd_info[6].dummy_en.q),
// to register interface (read)
.qs (cmd_info_6_dummy_en_6_qs)
@@ -10693,8 +10695,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_6_payload_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_6_payload_en_6_we),
@@ -10702,11 +10704,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[6].payload_en.q ),
+ .q (reg2hw.cmd_info[6].payload_en.q),
// to register interface (read)
.qs (cmd_info_6_payload_en_6_qs)
@@ -10719,8 +10721,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_6_payload_dir_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_6_payload_dir_6_we),
@@ -10728,11 +10730,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[6].payload_dir.q ),
+ .q (reg2hw.cmd_info[6].payload_dir.q),
// to register interface (read)
.qs (cmd_info_6_payload_dir_6_qs)
@@ -10748,8 +10750,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_7_opcode_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_7_opcode_7_we),
@@ -10757,11 +10759,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[7].opcode.q ),
+ .q (reg2hw.cmd_info[7].opcode.q),
// to register interface (read)
.qs (cmd_info_7_opcode_7_qs)
@@ -10774,8 +10776,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_7_addr_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_7_addr_en_7_we),
@@ -10783,11 +10785,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[7].addr_en.q ),
+ .q (reg2hw.cmd_info[7].addr_en.q),
// to register interface (read)
.qs (cmd_info_7_addr_en_7_qs)
@@ -10800,8 +10802,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_7_addr_swap_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_7_addr_swap_en_7_we),
@@ -10809,11 +10811,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[7].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[7].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_7_addr_swap_en_7_qs)
@@ -10826,8 +10828,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_7_addr_4b_affected_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_7_addr_4b_affected_7_we),
@@ -10835,11 +10837,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[7].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[7].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_7_addr_4b_affected_7_qs)
@@ -10852,8 +10854,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_7_dummy_size_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_7_dummy_size_7_we),
@@ -10861,11 +10863,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[7].dummy_size.q ),
+ .q (reg2hw.cmd_info[7].dummy_size.q),
// to register interface (read)
.qs (cmd_info_7_dummy_size_7_qs)
@@ -10878,8 +10880,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_7_dummy_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_7_dummy_en_7_we),
@@ -10887,11 +10889,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[7].dummy_en.q ),
+ .q (reg2hw.cmd_info[7].dummy_en.q),
// to register interface (read)
.qs (cmd_info_7_dummy_en_7_qs)
@@ -10904,8 +10906,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_7_payload_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_7_payload_en_7_we),
@@ -10913,11 +10915,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[7].payload_en.q ),
+ .q (reg2hw.cmd_info[7].payload_en.q),
// to register interface (read)
.qs (cmd_info_7_payload_en_7_qs)
@@ -10930,8 +10932,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_7_payload_dir_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_7_payload_dir_7_we),
@@ -10939,11 +10941,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[7].payload_dir.q ),
+ .q (reg2hw.cmd_info[7].payload_dir.q),
// to register interface (read)
.qs (cmd_info_7_payload_dir_7_qs)
@@ -10959,8 +10961,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_8_opcode_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_8_opcode_8_we),
@@ -10968,11 +10970,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[8].opcode.q ),
+ .q (reg2hw.cmd_info[8].opcode.q),
// to register interface (read)
.qs (cmd_info_8_opcode_8_qs)
@@ -10985,8 +10987,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_8_addr_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_8_addr_en_8_we),
@@ -10994,11 +10996,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[8].addr_en.q ),
+ .q (reg2hw.cmd_info[8].addr_en.q),
// to register interface (read)
.qs (cmd_info_8_addr_en_8_qs)
@@ -11011,8 +11013,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_8_addr_swap_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_8_addr_swap_en_8_we),
@@ -11020,11 +11022,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[8].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[8].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_8_addr_swap_en_8_qs)
@@ -11037,8 +11039,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_8_addr_4b_affected_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_8_addr_4b_affected_8_we),
@@ -11046,11 +11048,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[8].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[8].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_8_addr_4b_affected_8_qs)
@@ -11063,8 +11065,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_8_dummy_size_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_8_dummy_size_8_we),
@@ -11072,11 +11074,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[8].dummy_size.q ),
+ .q (reg2hw.cmd_info[8].dummy_size.q),
// to register interface (read)
.qs (cmd_info_8_dummy_size_8_qs)
@@ -11089,8 +11091,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_8_dummy_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_8_dummy_en_8_we),
@@ -11098,11 +11100,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[8].dummy_en.q ),
+ .q (reg2hw.cmd_info[8].dummy_en.q),
// to register interface (read)
.qs (cmd_info_8_dummy_en_8_qs)
@@ -11115,8 +11117,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_8_payload_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_8_payload_en_8_we),
@@ -11124,11 +11126,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[8].payload_en.q ),
+ .q (reg2hw.cmd_info[8].payload_en.q),
// to register interface (read)
.qs (cmd_info_8_payload_en_8_qs)
@@ -11141,8 +11143,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_8_payload_dir_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_8_payload_dir_8_we),
@@ -11150,11 +11152,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[8].payload_dir.q ),
+ .q (reg2hw.cmd_info[8].payload_dir.q),
// to register interface (read)
.qs (cmd_info_8_payload_dir_8_qs)
@@ -11170,8 +11172,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_9_opcode_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_9_opcode_9_we),
@@ -11179,11 +11181,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[9].opcode.q ),
+ .q (reg2hw.cmd_info[9].opcode.q),
// to register interface (read)
.qs (cmd_info_9_opcode_9_qs)
@@ -11196,8 +11198,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_9_addr_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_9_addr_en_9_we),
@@ -11205,11 +11207,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[9].addr_en.q ),
+ .q (reg2hw.cmd_info[9].addr_en.q),
// to register interface (read)
.qs (cmd_info_9_addr_en_9_qs)
@@ -11222,8 +11224,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_9_addr_swap_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_9_addr_swap_en_9_we),
@@ -11231,11 +11233,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[9].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[9].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_9_addr_swap_en_9_qs)
@@ -11248,8 +11250,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_9_addr_4b_affected_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_9_addr_4b_affected_9_we),
@@ -11257,11 +11259,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[9].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[9].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_9_addr_4b_affected_9_qs)
@@ -11274,8 +11276,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_9_dummy_size_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_9_dummy_size_9_we),
@@ -11283,11 +11285,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[9].dummy_size.q ),
+ .q (reg2hw.cmd_info[9].dummy_size.q),
// to register interface (read)
.qs (cmd_info_9_dummy_size_9_qs)
@@ -11300,8 +11302,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_9_dummy_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_9_dummy_en_9_we),
@@ -11309,11 +11311,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[9].dummy_en.q ),
+ .q (reg2hw.cmd_info[9].dummy_en.q),
// to register interface (read)
.qs (cmd_info_9_dummy_en_9_qs)
@@ -11326,8 +11328,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_9_payload_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_9_payload_en_9_we),
@@ -11335,11 +11337,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[9].payload_en.q ),
+ .q (reg2hw.cmd_info[9].payload_en.q),
// to register interface (read)
.qs (cmd_info_9_payload_en_9_qs)
@@ -11352,8 +11354,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_9_payload_dir_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_9_payload_dir_9_we),
@@ -11361,11 +11363,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[9].payload_dir.q ),
+ .q (reg2hw.cmd_info[9].payload_dir.q),
// to register interface (read)
.qs (cmd_info_9_payload_dir_9_qs)
@@ -11381,8 +11383,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_10_opcode_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_10_opcode_10_we),
@@ -11390,11 +11392,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[10].opcode.q ),
+ .q (reg2hw.cmd_info[10].opcode.q),
// to register interface (read)
.qs (cmd_info_10_opcode_10_qs)
@@ -11407,8 +11409,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_10_addr_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_10_addr_en_10_we),
@@ -11416,11 +11418,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[10].addr_en.q ),
+ .q (reg2hw.cmd_info[10].addr_en.q),
// to register interface (read)
.qs (cmd_info_10_addr_en_10_qs)
@@ -11433,8 +11435,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_10_addr_swap_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_10_addr_swap_en_10_we),
@@ -11442,11 +11444,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[10].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[10].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_10_addr_swap_en_10_qs)
@@ -11459,8 +11461,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_10_addr_4b_affected_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_10_addr_4b_affected_10_we),
@@ -11468,11 +11470,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[10].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[10].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_10_addr_4b_affected_10_qs)
@@ -11485,8 +11487,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_10_dummy_size_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_10_dummy_size_10_we),
@@ -11494,11 +11496,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[10].dummy_size.q ),
+ .q (reg2hw.cmd_info[10].dummy_size.q),
// to register interface (read)
.qs (cmd_info_10_dummy_size_10_qs)
@@ -11511,8 +11513,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_10_dummy_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_10_dummy_en_10_we),
@@ -11520,11 +11522,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[10].dummy_en.q ),
+ .q (reg2hw.cmd_info[10].dummy_en.q),
// to register interface (read)
.qs (cmd_info_10_dummy_en_10_qs)
@@ -11537,8 +11539,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_10_payload_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_10_payload_en_10_we),
@@ -11546,11 +11548,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[10].payload_en.q ),
+ .q (reg2hw.cmd_info[10].payload_en.q),
// to register interface (read)
.qs (cmd_info_10_payload_en_10_qs)
@@ -11563,8 +11565,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_10_payload_dir_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_10_payload_dir_10_we),
@@ -11572,11 +11574,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[10].payload_dir.q ),
+ .q (reg2hw.cmd_info[10].payload_dir.q),
// to register interface (read)
.qs (cmd_info_10_payload_dir_10_qs)
@@ -11592,8 +11594,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_11_opcode_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_11_opcode_11_we),
@@ -11601,11 +11603,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[11].opcode.q ),
+ .q (reg2hw.cmd_info[11].opcode.q),
// to register interface (read)
.qs (cmd_info_11_opcode_11_qs)
@@ -11618,8 +11620,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_11_addr_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_11_addr_en_11_we),
@@ -11627,11 +11629,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[11].addr_en.q ),
+ .q (reg2hw.cmd_info[11].addr_en.q),
// to register interface (read)
.qs (cmd_info_11_addr_en_11_qs)
@@ -11644,8 +11646,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_11_addr_swap_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_11_addr_swap_en_11_we),
@@ -11653,11 +11655,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[11].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[11].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_11_addr_swap_en_11_qs)
@@ -11670,8 +11672,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_11_addr_4b_affected_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_11_addr_4b_affected_11_we),
@@ -11679,11 +11681,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[11].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[11].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_11_addr_4b_affected_11_qs)
@@ -11696,8 +11698,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_11_dummy_size_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_11_dummy_size_11_we),
@@ -11705,11 +11707,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[11].dummy_size.q ),
+ .q (reg2hw.cmd_info[11].dummy_size.q),
// to register interface (read)
.qs (cmd_info_11_dummy_size_11_qs)
@@ -11722,8 +11724,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_11_dummy_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_11_dummy_en_11_we),
@@ -11731,11 +11733,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[11].dummy_en.q ),
+ .q (reg2hw.cmd_info[11].dummy_en.q),
// to register interface (read)
.qs (cmd_info_11_dummy_en_11_qs)
@@ -11748,8 +11750,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_11_payload_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_11_payload_en_11_we),
@@ -11757,11 +11759,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[11].payload_en.q ),
+ .q (reg2hw.cmd_info[11].payload_en.q),
// to register interface (read)
.qs (cmd_info_11_payload_en_11_qs)
@@ -11774,8 +11776,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_11_payload_dir_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_11_payload_dir_11_we),
@@ -11783,11 +11785,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[11].payload_dir.q ),
+ .q (reg2hw.cmd_info[11].payload_dir.q),
// to register interface (read)
.qs (cmd_info_11_payload_dir_11_qs)
@@ -11803,8 +11805,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_12_opcode_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_12_opcode_12_we),
@@ -11812,11 +11814,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[12].opcode.q ),
+ .q (reg2hw.cmd_info[12].opcode.q),
// to register interface (read)
.qs (cmd_info_12_opcode_12_qs)
@@ -11829,8 +11831,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_12_addr_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_12_addr_en_12_we),
@@ -11838,11 +11840,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[12].addr_en.q ),
+ .q (reg2hw.cmd_info[12].addr_en.q),
// to register interface (read)
.qs (cmd_info_12_addr_en_12_qs)
@@ -11855,8 +11857,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_12_addr_swap_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_12_addr_swap_en_12_we),
@@ -11864,11 +11866,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[12].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[12].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_12_addr_swap_en_12_qs)
@@ -11881,8 +11883,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_12_addr_4b_affected_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_12_addr_4b_affected_12_we),
@@ -11890,11 +11892,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[12].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[12].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_12_addr_4b_affected_12_qs)
@@ -11907,8 +11909,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_12_dummy_size_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_12_dummy_size_12_we),
@@ -11916,11 +11918,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[12].dummy_size.q ),
+ .q (reg2hw.cmd_info[12].dummy_size.q),
// to register interface (read)
.qs (cmd_info_12_dummy_size_12_qs)
@@ -11933,8 +11935,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_12_dummy_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_12_dummy_en_12_we),
@@ -11942,11 +11944,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[12].dummy_en.q ),
+ .q (reg2hw.cmd_info[12].dummy_en.q),
// to register interface (read)
.qs (cmd_info_12_dummy_en_12_qs)
@@ -11959,8 +11961,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_12_payload_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_12_payload_en_12_we),
@@ -11968,11 +11970,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[12].payload_en.q ),
+ .q (reg2hw.cmd_info[12].payload_en.q),
// to register interface (read)
.qs (cmd_info_12_payload_en_12_qs)
@@ -11985,8 +11987,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_12_payload_dir_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_12_payload_dir_12_we),
@@ -11994,11 +11996,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[12].payload_dir.q ),
+ .q (reg2hw.cmd_info[12].payload_dir.q),
// to register interface (read)
.qs (cmd_info_12_payload_dir_12_qs)
@@ -12014,8 +12016,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_13_opcode_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_13_opcode_13_we),
@@ -12023,11 +12025,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[13].opcode.q ),
+ .q (reg2hw.cmd_info[13].opcode.q),
// to register interface (read)
.qs (cmd_info_13_opcode_13_qs)
@@ -12040,8 +12042,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_13_addr_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_13_addr_en_13_we),
@@ -12049,11 +12051,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[13].addr_en.q ),
+ .q (reg2hw.cmd_info[13].addr_en.q),
// to register interface (read)
.qs (cmd_info_13_addr_en_13_qs)
@@ -12066,8 +12068,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_13_addr_swap_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_13_addr_swap_en_13_we),
@@ -12075,11 +12077,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[13].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[13].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_13_addr_swap_en_13_qs)
@@ -12092,8 +12094,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_13_addr_4b_affected_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_13_addr_4b_affected_13_we),
@@ -12101,11 +12103,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[13].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[13].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_13_addr_4b_affected_13_qs)
@@ -12118,8 +12120,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_13_dummy_size_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_13_dummy_size_13_we),
@@ -12127,11 +12129,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[13].dummy_size.q ),
+ .q (reg2hw.cmd_info[13].dummy_size.q),
// to register interface (read)
.qs (cmd_info_13_dummy_size_13_qs)
@@ -12144,8 +12146,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_13_dummy_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_13_dummy_en_13_we),
@@ -12153,11 +12155,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[13].dummy_en.q ),
+ .q (reg2hw.cmd_info[13].dummy_en.q),
// to register interface (read)
.qs (cmd_info_13_dummy_en_13_qs)
@@ -12170,8 +12172,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_13_payload_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_13_payload_en_13_we),
@@ -12179,11 +12181,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[13].payload_en.q ),
+ .q (reg2hw.cmd_info[13].payload_en.q),
// to register interface (read)
.qs (cmd_info_13_payload_en_13_qs)
@@ -12196,8 +12198,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_13_payload_dir_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_13_payload_dir_13_we),
@@ -12205,11 +12207,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[13].payload_dir.q ),
+ .q (reg2hw.cmd_info[13].payload_dir.q),
// to register interface (read)
.qs (cmd_info_13_payload_dir_13_qs)
@@ -12225,8 +12227,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_14_opcode_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_14_opcode_14_we),
@@ -12234,11 +12236,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[14].opcode.q ),
+ .q (reg2hw.cmd_info[14].opcode.q),
// to register interface (read)
.qs (cmd_info_14_opcode_14_qs)
@@ -12251,8 +12253,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_14_addr_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_14_addr_en_14_we),
@@ -12260,11 +12262,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[14].addr_en.q ),
+ .q (reg2hw.cmd_info[14].addr_en.q),
// to register interface (read)
.qs (cmd_info_14_addr_en_14_qs)
@@ -12277,8 +12279,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_14_addr_swap_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_14_addr_swap_en_14_we),
@@ -12286,11 +12288,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[14].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[14].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_14_addr_swap_en_14_qs)
@@ -12303,8 +12305,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_14_addr_4b_affected_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_14_addr_4b_affected_14_we),
@@ -12312,11 +12314,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[14].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[14].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_14_addr_4b_affected_14_qs)
@@ -12329,8 +12331,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_14_dummy_size_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_14_dummy_size_14_we),
@@ -12338,11 +12340,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[14].dummy_size.q ),
+ .q (reg2hw.cmd_info[14].dummy_size.q),
// to register interface (read)
.qs (cmd_info_14_dummy_size_14_qs)
@@ -12355,8 +12357,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_14_dummy_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_14_dummy_en_14_we),
@@ -12364,11 +12366,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[14].dummy_en.q ),
+ .q (reg2hw.cmd_info[14].dummy_en.q),
// to register interface (read)
.qs (cmd_info_14_dummy_en_14_qs)
@@ -12381,8 +12383,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_14_payload_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_14_payload_en_14_we),
@@ -12390,11 +12392,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[14].payload_en.q ),
+ .q (reg2hw.cmd_info[14].payload_en.q),
// to register interface (read)
.qs (cmd_info_14_payload_en_14_qs)
@@ -12407,8 +12409,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_14_payload_dir_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_14_payload_dir_14_we),
@@ -12416,11 +12418,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[14].payload_dir.q ),
+ .q (reg2hw.cmd_info[14].payload_dir.q),
// to register interface (read)
.qs (cmd_info_14_payload_dir_14_qs)
@@ -12436,8 +12438,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_cmd_info_15_opcode_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_15_opcode_15_we),
@@ -12445,11 +12447,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[15].opcode.q ),
+ .q (reg2hw.cmd_info[15].opcode.q),
// to register interface (read)
.qs (cmd_info_15_opcode_15_qs)
@@ -12462,8 +12464,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_15_addr_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_15_addr_en_15_we),
@@ -12471,11 +12473,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[15].addr_en.q ),
+ .q (reg2hw.cmd_info[15].addr_en.q),
// to register interface (read)
.qs (cmd_info_15_addr_en_15_qs)
@@ -12488,8 +12490,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_15_addr_swap_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_15_addr_swap_en_15_we),
@@ -12497,11 +12499,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[15].addr_swap_en.q ),
+ .q (reg2hw.cmd_info[15].addr_swap_en.q),
// to register interface (read)
.qs (cmd_info_15_addr_swap_en_15_qs)
@@ -12514,8 +12516,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_15_addr_4b_affected_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_15_addr_4b_affected_15_we),
@@ -12523,11 +12525,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[15].addr_4b_affected.q ),
+ .q (reg2hw.cmd_info[15].addr_4b_affected.q),
// to register interface (read)
.qs (cmd_info_15_addr_4b_affected_15_qs)
@@ -12540,8 +12542,8 @@
.SWACCESS("RW"),
.RESVAL (3'h7)
) u_cmd_info_15_dummy_size_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_15_dummy_size_15_we),
@@ -12549,11 +12551,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[15].dummy_size.q ),
+ .q (reg2hw.cmd_info[15].dummy_size.q),
// to register interface (read)
.qs (cmd_info_15_dummy_size_15_qs)
@@ -12566,8 +12568,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_15_dummy_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_15_dummy_en_15_we),
@@ -12575,11 +12577,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[15].dummy_en.q ),
+ .q (reg2hw.cmd_info[15].dummy_en.q),
// to register interface (read)
.qs (cmd_info_15_dummy_en_15_qs)
@@ -12592,8 +12594,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cmd_info_15_payload_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_15_payload_en_15_we),
@@ -12601,11 +12603,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[15].payload_en.q ),
+ .q (reg2hw.cmd_info[15].payload_en.q),
// to register interface (read)
.qs (cmd_info_15_payload_en_15_qs)
@@ -12618,8 +12620,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cmd_info_15_payload_dir_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cmd_info_15_payload_dir_15_we),
@@ -12627,11 +12629,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cmd_info[15].payload_dir.q ),
+ .q (reg2hw.cmd_info[15].payload_dir.q),
// to register interface (read)
.qs (cmd_info_15_payload_dir_15_qs)
diff --git a/hw/ip/spi_host/rtl/spi_host_reg_top.sv b/hw/ip/spi_host/rtl/spi_host_reg_top.sv
index 82b9855..3e86bca 100644
--- a/hw/ip/spi_host/rtl/spi_host_reg_top.sv
+++ b/hw/ip/spi_host/rtl/spi_host_reg_top.sv
@@ -292,8 +292,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_error_we),
@@ -301,11 +301,11 @@
// from internal hardware
.de (hw2reg.intr_state.error.de),
- .d (hw2reg.intr_state.error.d ),
+ .d (hw2reg.intr_state.error.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.error.q ),
+ .q (reg2hw.intr_state.error.q),
// to register interface (read)
.qs (intr_state_error_qs)
@@ -318,8 +318,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_spi_event (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_spi_event_we),
@@ -327,11 +327,11 @@
// from internal hardware
.de (hw2reg.intr_state.spi_event.de),
- .d (hw2reg.intr_state.spi_event.d ),
+ .d (hw2reg.intr_state.spi_event.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.spi_event.q ),
+ .q (reg2hw.intr_state.spi_event.q),
// to register interface (read)
.qs (intr_state_spi_event_qs)
@@ -346,8 +346,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_error (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_error_we),
@@ -355,11 +355,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.error.q ),
+ .q (reg2hw.intr_enable.error.q),
// to register interface (read)
.qs (intr_enable_error_qs)
@@ -372,8 +372,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_spi_event (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_spi_event_we),
@@ -381,11 +381,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.spi_event.q ),
+ .q (reg2hw.intr_enable.spi_event.q),
// to register interface (read)
.qs (intr_enable_spi_event_qs)
@@ -404,7 +404,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.error.qe),
- .q (reg2hw.intr_test.error.q ),
+ .q (reg2hw.intr_test.error.q),
.qs ()
);
@@ -419,7 +419,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.spi_event.qe),
- .q (reg2hw.intr_test.spi_event.q ),
+ .q (reg2hw.intr_test.spi_event.q),
.qs ()
);
@@ -435,7 +435,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.qe),
- .q (reg2hw.alert_test.q ),
+ .q (reg2hw.alert_test.q),
.qs ()
);
@@ -448,8 +448,8 @@
.SWACCESS("RW"),
.RESVAL (8'h7f)
) u_control_rx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_rx_watermark_we),
@@ -457,11 +457,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.rx_watermark.q ),
+ .q (reg2hw.control.rx_watermark.q),
// to register interface (read)
.qs (control_rx_watermark_qs)
@@ -474,8 +474,8 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_control_tx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_tx_watermark_we),
@@ -483,11 +483,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.tx_watermark.q ),
+ .q (reg2hw.control.tx_watermark.q),
// to register interface (read)
.qs (control_tx_watermark_qs)
@@ -500,8 +500,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_passthru (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_passthru_we),
@@ -509,11 +509,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.passthru.q ),
+ .q (reg2hw.control.passthru.q),
// to register interface (read)
.qs (control_passthru_qs)
@@ -526,8 +526,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_sw_rst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_sw_rst_we),
@@ -535,11 +535,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.sw_rst.q ),
+ .q (reg2hw.control.sw_rst.q),
// to register interface (read)
.qs (control_sw_rst_qs)
@@ -552,8 +552,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_spien (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (control_spien_we),
@@ -561,11 +561,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.spien.q ),
+ .q (reg2hw.control.spien.q),
// to register interface (read)
.qs (control_spien_qs)
@@ -580,15 +580,16 @@
.SWACCESS("RO"),
.RESVAL (8'h0)
) u_status_txqd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.txqd.de),
- .d (hw2reg.status.txqd.d ),
+ .d (hw2reg.status.txqd.d),
// to internal hardware
.qe (),
@@ -605,15 +606,16 @@
.SWACCESS("RO"),
.RESVAL (8'h0)
) u_status_rxqd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.rxqd.de),
- .d (hw2reg.status.rxqd.d ),
+ .d (hw2reg.status.rxqd.d),
// to internal hardware
.qe (),
@@ -630,15 +632,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_rxwm (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.rxwm.de),
- .d (hw2reg.status.rxwm.d ),
+ .d (hw2reg.status.rxwm.d),
// to internal hardware
.qe (),
@@ -655,15 +658,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_byteorder (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.byteorder.de),
- .d (hw2reg.status.byteorder.d ),
+ .d (hw2reg.status.byteorder.d),
// to internal hardware
.qe (),
@@ -680,15 +684,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_rxstall (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.rxstall.de),
- .d (hw2reg.status.rxstall.d ),
+ .d (hw2reg.status.rxstall.d),
// to internal hardware
.qe (),
@@ -705,15 +710,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_rxempty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.rxempty.de),
- .d (hw2reg.status.rxempty.d ),
+ .d (hw2reg.status.rxempty.d),
// to internal hardware
.qe (),
@@ -730,15 +736,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_rxfull (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.rxfull.de),
- .d (hw2reg.status.rxfull.d ),
+ .d (hw2reg.status.rxfull.d),
// to internal hardware
.qe (),
@@ -755,15 +762,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_txwm (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.txwm.de),
- .d (hw2reg.status.txwm.d ),
+ .d (hw2reg.status.txwm.d),
// to internal hardware
.qe (),
@@ -780,15 +788,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_txstall (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.txstall.de),
- .d (hw2reg.status.txstall.d ),
+ .d (hw2reg.status.txstall.d),
// to internal hardware
.qe (),
@@ -805,15 +814,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_txempty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.txempty.de),
- .d (hw2reg.status.txempty.d ),
+ .d (hw2reg.status.txempty.d),
// to internal hardware
.qe (),
@@ -830,15 +840,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_txfull (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.txfull.de),
- .d (hw2reg.status.txfull.d ),
+ .d (hw2reg.status.txfull.d),
// to internal hardware
.qe (),
@@ -855,15 +866,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_active (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.active.de),
- .d (hw2reg.status.active.d ),
+ .d (hw2reg.status.active.d),
// to internal hardware
.qe (),
@@ -880,15 +892,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_ready (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.ready.de),
- .d (hw2reg.status.ready.d ),
+ .d (hw2reg.status.ready.d),
// to internal hardware
.qe (),
@@ -909,8 +922,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_configopts_clkdiv_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configopts_clkdiv_0_we),
@@ -918,11 +931,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configopts[0].clkdiv.q ),
+ .q (reg2hw.configopts[0].clkdiv.q),
// to register interface (read)
.qs (configopts_clkdiv_0_qs)
@@ -935,8 +948,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_configopts_csnidle_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configopts_csnidle_0_we),
@@ -944,11 +957,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configopts[0].csnidle.q ),
+ .q (reg2hw.configopts[0].csnidle.q),
// to register interface (read)
.qs (configopts_csnidle_0_qs)
@@ -961,8 +974,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_configopts_csntrail_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configopts_csntrail_0_we),
@@ -970,11 +983,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configopts[0].csntrail.q ),
+ .q (reg2hw.configopts[0].csntrail.q),
// to register interface (read)
.qs (configopts_csntrail_0_qs)
@@ -987,8 +1000,8 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_configopts_csnlead_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configopts_csnlead_0_we),
@@ -996,11 +1009,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configopts[0].csnlead.q ),
+ .q (reg2hw.configopts[0].csnlead.q),
// to register interface (read)
.qs (configopts_csnlead_0_qs)
@@ -1013,8 +1026,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configopts_fullcyc_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configopts_fullcyc_0_we),
@@ -1022,11 +1035,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configopts[0].fullcyc.q ),
+ .q (reg2hw.configopts[0].fullcyc.q),
// to register interface (read)
.qs (configopts_fullcyc_0_qs)
@@ -1039,8 +1052,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configopts_cpha_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configopts_cpha_0_we),
@@ -1048,11 +1061,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configopts[0].cpha.q ),
+ .q (reg2hw.configopts[0].cpha.q),
// to register interface (read)
.qs (configopts_cpha_0_qs)
@@ -1065,8 +1078,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configopts_cpol_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configopts_cpol_0_we),
@@ -1074,11 +1087,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configopts[0].cpol.q ),
+ .q (reg2hw.configopts[0].cpol.q),
// to register interface (read)
.qs (configopts_cpol_0_qs)
@@ -1093,8 +1106,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_csid (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (csid_we),
@@ -1102,11 +1115,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.csid.q ),
+ .q (reg2hw.csid.q),
// to register interface (read)
.qs (csid_qs)
@@ -1121,8 +1134,8 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_command_len (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (command_len_we),
@@ -1130,11 +1143,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.command.len.qe),
- .q (reg2hw.command.len.q ),
+ .q (reg2hw.command.len.q),
// to register interface (read)
.qs (command_len_qs)
@@ -1147,8 +1160,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_command_csaat (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (command_csaat_we),
@@ -1156,11 +1169,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.command.csaat.qe),
- .q (reg2hw.command.csaat.q ),
+ .q (reg2hw.command.csaat.q),
// to register interface (read)
.qs (command_csaat_qs)
@@ -1173,8 +1186,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_command_speed (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (command_speed_we),
@@ -1182,11 +1195,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.command.speed.qe),
- .q (reg2hw.command.speed.q ),
+ .q (reg2hw.command.speed.q),
// to register interface (read)
.qs (command_speed_qs)
@@ -1199,8 +1212,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_command_direction (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (command_direction_we),
@@ -1208,11 +1221,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.command.direction.qe),
- .q (reg2hw.command.direction.q ),
+ .q (reg2hw.command.direction.q),
// to register interface (read)
.qs (command_direction_qs)
@@ -1227,8 +1240,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_error_enable_cmdbusy (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_enable_cmdbusy_we),
@@ -1236,11 +1249,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.error_enable.cmdbusy.q ),
+ .q (reg2hw.error_enable.cmdbusy.q),
// to register interface (read)
.qs (error_enable_cmdbusy_qs)
@@ -1253,8 +1266,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_error_enable_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_enable_overflow_we),
@@ -1262,11 +1275,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.error_enable.overflow.q ),
+ .q (reg2hw.error_enable.overflow.q),
// to register interface (read)
.qs (error_enable_overflow_qs)
@@ -1279,8 +1292,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_error_enable_underflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_enable_underflow_we),
@@ -1288,11 +1301,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.error_enable.underflow.q ),
+ .q (reg2hw.error_enable.underflow.q),
// to register interface (read)
.qs (error_enable_underflow_qs)
@@ -1305,8 +1318,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_error_enable_cmdinval (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_enable_cmdinval_we),
@@ -1314,11 +1327,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.error_enable.cmdinval.q ),
+ .q (reg2hw.error_enable.cmdinval.q),
// to register interface (read)
.qs (error_enable_cmdinval_qs)
@@ -1331,8 +1344,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_error_enable_csidinval (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_enable_csidinval_we),
@@ -1340,11 +1353,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.error_enable.csidinval.q ),
+ .q (reg2hw.error_enable.csidinval.q),
// to register interface (read)
.qs (error_enable_csidinval_qs)
@@ -1359,8 +1372,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_error_status_cmdbusy (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_status_cmdbusy_we),
@@ -1368,11 +1381,11 @@
// from internal hardware
.de (hw2reg.error_status.cmdbusy.de),
- .d (hw2reg.error_status.cmdbusy.d ),
+ .d (hw2reg.error_status.cmdbusy.d),
// to internal hardware
.qe (),
- .q (reg2hw.error_status.cmdbusy.q ),
+ .q (reg2hw.error_status.cmdbusy.q),
// to register interface (read)
.qs (error_status_cmdbusy_qs)
@@ -1385,8 +1398,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_error_status_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_status_overflow_we),
@@ -1394,11 +1407,11 @@
// from internal hardware
.de (hw2reg.error_status.overflow.de),
- .d (hw2reg.error_status.overflow.d ),
+ .d (hw2reg.error_status.overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.error_status.overflow.q ),
+ .q (reg2hw.error_status.overflow.q),
// to register interface (read)
.qs (error_status_overflow_qs)
@@ -1411,8 +1424,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_error_status_underflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_status_underflow_we),
@@ -1420,11 +1433,11 @@
// from internal hardware
.de (hw2reg.error_status.underflow.de),
- .d (hw2reg.error_status.underflow.d ),
+ .d (hw2reg.error_status.underflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.error_status.underflow.q ),
+ .q (reg2hw.error_status.underflow.q),
// to register interface (read)
.qs (error_status_underflow_qs)
@@ -1437,8 +1450,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_error_status_cmdinval (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_status_cmdinval_we),
@@ -1446,11 +1459,11 @@
// from internal hardware
.de (hw2reg.error_status.cmdinval.de),
- .d (hw2reg.error_status.cmdinval.d ),
+ .d (hw2reg.error_status.cmdinval.d),
// to internal hardware
.qe (),
- .q (reg2hw.error_status.cmdinval.q ),
+ .q (reg2hw.error_status.cmdinval.q),
// to register interface (read)
.qs (error_status_cmdinval_qs)
@@ -1463,8 +1476,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_error_status_csidinval (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (error_status_csidinval_we),
@@ -1472,11 +1485,11 @@
// from internal hardware
.de (hw2reg.error_status.csidinval.de),
- .d (hw2reg.error_status.csidinval.d ),
+ .d (hw2reg.error_status.csidinval.d),
// to internal hardware
.qe (),
- .q (reg2hw.error_status.csidinval.q ),
+ .q (reg2hw.error_status.csidinval.q),
// to register interface (read)
.qs (error_status_csidinval_qs)
@@ -1491,8 +1504,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_event_enable_rxfull (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (event_enable_rxfull_we),
@@ -1500,11 +1513,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.event_enable.rxfull.q ),
+ .q (reg2hw.event_enable.rxfull.q),
// to register interface (read)
.qs (event_enable_rxfull_qs)
@@ -1517,8 +1530,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_event_enable_txempty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (event_enable_txempty_we),
@@ -1526,11 +1539,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.event_enable.txempty.q ),
+ .q (reg2hw.event_enable.txempty.q),
// to register interface (read)
.qs (event_enable_txempty_qs)
@@ -1543,8 +1556,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_event_enable_rxwm (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (event_enable_rxwm_we),
@@ -1552,11 +1565,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.event_enable.rxwm.q ),
+ .q (reg2hw.event_enable.rxwm.q),
// to register interface (read)
.qs (event_enable_rxwm_qs)
@@ -1569,8 +1582,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_event_enable_txwm (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (event_enable_txwm_we),
@@ -1578,11 +1591,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.event_enable.txwm.q ),
+ .q (reg2hw.event_enable.txwm.q),
// to register interface (read)
.qs (event_enable_txwm_qs)
@@ -1595,8 +1608,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_event_enable_ready (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (event_enable_ready_we),
@@ -1604,11 +1617,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.event_enable.ready.q ),
+ .q (reg2hw.event_enable.ready.q),
// to register interface (read)
.qs (event_enable_ready_qs)
@@ -1621,8 +1634,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_event_enable_idle (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (event_enable_idle_we),
@@ -1630,11 +1643,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.event_enable.idle.q ),
+ .q (reg2hw.event_enable.idle.q),
// to register interface (read)
.qs (event_enable_idle_qs)
diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_top.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_top.sv
index d7d2ca0..cffe237 100644
--- a/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_top.sv
+++ b/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_top.sv
@@ -148,7 +148,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_intg_error.qe),
- .q (reg2hw.alert_test.fatal_intg_error.q ),
+ .q (reg2hw.alert_test.fatal_intg_error.q),
.qs ()
);
@@ -163,7 +163,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_parity_error.qe),
- .q (reg2hw.alert_test.fatal_parity_error.q ),
+ .q (reg2hw.alert_test.fatal_parity_error.q),
.qs ()
);
@@ -237,8 +237,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_exec_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (exec_regwen_we),
@@ -246,7 +246,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -264,20 +264,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_exec (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (exec_we & exec_regwen_qs),
.wd (exec_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.exec.q ),
+ .q (reg2hw.exec.q),
// to register interface (read)
.qs (exec_qs)
@@ -291,8 +291,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_ctrl_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_regwen_we),
@@ -300,7 +300,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -318,13 +318,12 @@
.DW (1)
) u_ctrl_renew_scr_key (
.re (ctrl_renew_scr_key_re),
- // qualified with register enable
.we (ctrl_renew_scr_key_we & ctrl_regwen_qs),
.wd (ctrl_renew_scr_key_wd),
.d (hw2reg.ctrl.renew_scr_key.d),
.qre (),
.qe (reg2hw.ctrl.renew_scr_key.qe),
- .q (reg2hw.ctrl.renew_scr_key.q ),
+ .q (reg2hw.ctrl.renew_scr_key.q),
.qs (ctrl_renew_scr_key_qs)
);
@@ -334,13 +333,12 @@
.DW (1)
) u_ctrl_init (
.re (ctrl_init_re),
- // qualified with register enable
.we (ctrl_init_we & ctrl_regwen_qs),
.wd (ctrl_init_wd),
.d (hw2reg.ctrl.init.d),
.qre (),
.qe (reg2hw.ctrl.init.qe),
- .q (reg2hw.ctrl.init.q ),
+ .q (reg2hw.ctrl.init.q),
.qs (ctrl_init_qs)
);
@@ -352,15 +350,16 @@
.SWACCESS("RO"),
.RESVAL (32'h0)
) u_error_address (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.error_address.de),
- .d (hw2reg.error_address.d ),
+ .d (hw2reg.error_address.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv
index 7c380c8..942e8b9 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv
@@ -466,8 +466,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
@@ -475,11 +475,11 @@
// from internal hardware
.de (hw2reg.intr_state.de),
- .d (hw2reg.intr_state.d ),
+ .d (hw2reg.intr_state.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.q ),
+ .q (reg2hw.intr_state.q),
// to register interface (read)
.qs (intr_state_qs)
@@ -493,8 +493,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
@@ -502,11 +502,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.q ),
+ .q (reg2hw.intr_enable.q),
// to register interface (read)
.qs (intr_enable_qs)
@@ -524,7 +524,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.qe),
- .q (reg2hw.intr_test.q ),
+ .q (reg2hw.intr_test.q),
.qs ()
);
@@ -536,8 +536,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regwen_we),
@@ -545,7 +545,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -563,20 +563,20 @@
.SWACCESS("RW"),
.RESVAL (16'h7d0)
) u_ec_rst_ctl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ec_rst_ctl_we & regwen_qs),
.wd (ec_rst_ctl_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.ec_rst_ctl.qe),
- .q (reg2hw.ec_rst_ctl.q ),
+ .q (reg2hw.ec_rst_ctl.q),
// to register interface (read)
.qs (ec_rst_ctl_qs)
@@ -591,20 +591,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_key0_in (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_key0_in_we & regwen_qs),
.wd (key_invert_ctl_key0_in_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.key0_in.q ),
+ .q (reg2hw.key_invert_ctl.key0_in.q),
// to register interface (read)
.qs (key_invert_ctl_key0_in_qs)
@@ -617,20 +617,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_key0_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_key0_out_we & regwen_qs),
.wd (key_invert_ctl_key0_out_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.key0_out.q ),
+ .q (reg2hw.key_invert_ctl.key0_out.q),
// to register interface (read)
.qs (key_invert_ctl_key0_out_qs)
@@ -643,20 +643,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_key1_in (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_key1_in_we & regwen_qs),
.wd (key_invert_ctl_key1_in_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.key1_in.q ),
+ .q (reg2hw.key_invert_ctl.key1_in.q),
// to register interface (read)
.qs (key_invert_ctl_key1_in_qs)
@@ -669,20 +669,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_key1_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_key1_out_we & regwen_qs),
.wd (key_invert_ctl_key1_out_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.key1_out.q ),
+ .q (reg2hw.key_invert_ctl.key1_out.q),
// to register interface (read)
.qs (key_invert_ctl_key1_out_qs)
@@ -695,20 +695,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_key2_in (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_key2_in_we & regwen_qs),
.wd (key_invert_ctl_key2_in_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.key2_in.q ),
+ .q (reg2hw.key_invert_ctl.key2_in.q),
// to register interface (read)
.qs (key_invert_ctl_key2_in_qs)
@@ -721,20 +721,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_key2_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_key2_out_we & regwen_qs),
.wd (key_invert_ctl_key2_out_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.key2_out.q ),
+ .q (reg2hw.key_invert_ctl.key2_out.q),
// to register interface (read)
.qs (key_invert_ctl_key2_out_qs)
@@ -747,20 +747,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_pwrb_in (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_pwrb_in_we & regwen_qs),
.wd (key_invert_ctl_pwrb_in_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.pwrb_in.q ),
+ .q (reg2hw.key_invert_ctl.pwrb_in.q),
// to register interface (read)
.qs (key_invert_ctl_pwrb_in_qs)
@@ -773,20 +773,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_pwrb_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_pwrb_out_we & regwen_qs),
.wd (key_invert_ctl_pwrb_out_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.pwrb_out.q ),
+ .q (reg2hw.key_invert_ctl.pwrb_out.q),
// to register interface (read)
.qs (key_invert_ctl_pwrb_out_qs)
@@ -799,20 +799,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_ac_present (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_ac_present_we & regwen_qs),
.wd (key_invert_ctl_ac_present_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.ac_present.q ),
+ .q (reg2hw.key_invert_ctl.ac_present.q),
// to register interface (read)
.qs (key_invert_ctl_ac_present_qs)
@@ -825,20 +825,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_invert_ctl_bat_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_invert_ctl_bat_disable_we & regwen_qs),
.wd (key_invert_ctl_bat_disable_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_invert_ctl.bat_disable.q ),
+ .q (reg2hw.key_invert_ctl.bat_disable.q),
// to register interface (read)
.qs (key_invert_ctl_bat_disable_qs)
@@ -853,20 +853,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_bat_disable_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_bat_disable_0_we & regwen_qs),
.wd (pin_allowed_ctl_bat_disable_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.bat_disable_0.q ),
+ .q (reg2hw.pin_allowed_ctl.bat_disable_0.q),
// to register interface (read)
.qs (pin_allowed_ctl_bat_disable_0_qs)
@@ -879,20 +879,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_pin_allowed_ctl_ec_rst_l_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_ec_rst_l_0_we & regwen_qs),
.wd (pin_allowed_ctl_ec_rst_l_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.ec_rst_l_0.q ),
+ .q (reg2hw.pin_allowed_ctl.ec_rst_l_0.q),
// to register interface (read)
.qs (pin_allowed_ctl_ec_rst_l_0_qs)
@@ -905,20 +905,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_pwrb_out_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_pwrb_out_0_we & regwen_qs),
.wd (pin_allowed_ctl_pwrb_out_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.pwrb_out_0.q ),
+ .q (reg2hw.pin_allowed_ctl.pwrb_out_0.q),
// to register interface (read)
.qs (pin_allowed_ctl_pwrb_out_0_qs)
@@ -931,20 +931,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key0_out_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_key0_out_0_we & regwen_qs),
.wd (pin_allowed_ctl_key0_out_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.key0_out_0.q ),
+ .q (reg2hw.pin_allowed_ctl.key0_out_0.q),
// to register interface (read)
.qs (pin_allowed_ctl_key0_out_0_qs)
@@ -957,20 +957,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key1_out_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_key1_out_0_we & regwen_qs),
.wd (pin_allowed_ctl_key1_out_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.key1_out_0.q ),
+ .q (reg2hw.pin_allowed_ctl.key1_out_0.q),
// to register interface (read)
.qs (pin_allowed_ctl_key1_out_0_qs)
@@ -983,20 +983,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key2_out_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_key2_out_0_we & regwen_qs),
.wd (pin_allowed_ctl_key2_out_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.key2_out_0.q ),
+ .q (reg2hw.pin_allowed_ctl.key2_out_0.q),
// to register interface (read)
.qs (pin_allowed_ctl_key2_out_0_qs)
@@ -1009,20 +1009,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_bat_disable_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_bat_disable_1_we & regwen_qs),
.wd (pin_allowed_ctl_bat_disable_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.bat_disable_1.q ),
+ .q (reg2hw.pin_allowed_ctl.bat_disable_1.q),
// to register interface (read)
.qs (pin_allowed_ctl_bat_disable_1_qs)
@@ -1035,20 +1035,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_ec_rst_l_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_ec_rst_l_1_we & regwen_qs),
.wd (pin_allowed_ctl_ec_rst_l_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.ec_rst_l_1.q ),
+ .q (reg2hw.pin_allowed_ctl.ec_rst_l_1.q),
// to register interface (read)
.qs (pin_allowed_ctl_ec_rst_l_1_qs)
@@ -1061,20 +1061,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_pwrb_out_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_pwrb_out_1_we & regwen_qs),
.wd (pin_allowed_ctl_pwrb_out_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.pwrb_out_1.q ),
+ .q (reg2hw.pin_allowed_ctl.pwrb_out_1.q),
// to register interface (read)
.qs (pin_allowed_ctl_pwrb_out_1_qs)
@@ -1087,20 +1087,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key0_out_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_key0_out_1_we & regwen_qs),
.wd (pin_allowed_ctl_key0_out_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.key0_out_1.q ),
+ .q (reg2hw.pin_allowed_ctl.key0_out_1.q),
// to register interface (read)
.qs (pin_allowed_ctl_key0_out_1_qs)
@@ -1113,20 +1113,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key1_out_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_key1_out_1_we & regwen_qs),
.wd (pin_allowed_ctl_key1_out_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.key1_out_1.q ),
+ .q (reg2hw.pin_allowed_ctl.key1_out_1.q),
// to register interface (read)
.qs (pin_allowed_ctl_key1_out_1_qs)
@@ -1139,20 +1139,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_allowed_ctl_key2_out_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (pin_allowed_ctl_key2_out_1_we & regwen_qs),
.wd (pin_allowed_ctl_key2_out_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_allowed_ctl.key2_out_1.q ),
+ .q (reg2hw.pin_allowed_ctl.key2_out_1.q),
// to register interface (read)
.qs (pin_allowed_ctl_key2_out_1_qs)
@@ -1167,8 +1167,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_ctl_bat_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_ctl_bat_disable_we),
@@ -1176,11 +1176,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_ctl.bat_disable.q ),
+ .q (reg2hw.pin_out_ctl.bat_disable.q),
// to register interface (read)
.qs (pin_out_ctl_bat_disable_qs)
@@ -1193,8 +1193,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_pin_out_ctl_ec_rst_l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_ctl_ec_rst_l_we),
@@ -1202,11 +1202,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_ctl.ec_rst_l.q ),
+ .q (reg2hw.pin_out_ctl.ec_rst_l.q),
// to register interface (read)
.qs (pin_out_ctl_ec_rst_l_qs)
@@ -1219,8 +1219,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_ctl_pwrb_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_ctl_pwrb_out_we),
@@ -1228,11 +1228,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_ctl.pwrb_out.q ),
+ .q (reg2hw.pin_out_ctl.pwrb_out.q),
// to register interface (read)
.qs (pin_out_ctl_pwrb_out_qs)
@@ -1245,8 +1245,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_ctl_key0_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_ctl_key0_out_we),
@@ -1254,11 +1254,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_ctl.key0_out.q ),
+ .q (reg2hw.pin_out_ctl.key0_out.q),
// to register interface (read)
.qs (pin_out_ctl_key0_out_qs)
@@ -1271,8 +1271,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_ctl_key1_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_ctl_key1_out_we),
@@ -1280,11 +1280,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_ctl.key1_out.q ),
+ .q (reg2hw.pin_out_ctl.key1_out.q),
// to register interface (read)
.qs (pin_out_ctl_key1_out_qs)
@@ -1297,8 +1297,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_ctl_key2_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_ctl_key2_out_we),
@@ -1306,11 +1306,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_ctl.key2_out.q ),
+ .q (reg2hw.pin_out_ctl.key2_out.q),
// to register interface (read)
.qs (pin_out_ctl_key2_out_qs)
@@ -1325,8 +1325,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_value_bat_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_value_bat_disable_we),
@@ -1334,11 +1334,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_value.bat_disable.q ),
+ .q (reg2hw.pin_out_value.bat_disable.q),
// to register interface (read)
.qs (pin_out_value_bat_disable_qs)
@@ -1351,8 +1351,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_value_ec_rst_l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_value_ec_rst_l_we),
@@ -1360,11 +1360,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_value.ec_rst_l.q ),
+ .q (reg2hw.pin_out_value.ec_rst_l.q),
// to register interface (read)
.qs (pin_out_value_ec_rst_l_qs)
@@ -1377,8 +1377,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_value_pwrb_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_value_pwrb_out_we),
@@ -1386,11 +1386,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_value.pwrb_out.q ),
+ .q (reg2hw.pin_out_value.pwrb_out.q),
// to register interface (read)
.qs (pin_out_value_pwrb_out_qs)
@@ -1403,8 +1403,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_value_key0_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_value_key0_out_we),
@@ -1412,11 +1412,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_value.key0_out.q ),
+ .q (reg2hw.pin_out_value.key0_out.q),
// to register interface (read)
.qs (pin_out_value_key0_out_qs)
@@ -1429,8 +1429,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_value_key1_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_value_key1_out_we),
@@ -1438,11 +1438,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_value.key1_out.q ),
+ .q (reg2hw.pin_out_value.key1_out.q),
// to register interface (read)
.qs (pin_out_value_key1_out_qs)
@@ -1455,8 +1455,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_pin_out_value_key2_out (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (pin_out_value_key2_out_we),
@@ -1464,11 +1464,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.pin_out_value.key2_out.q ),
+ .q (reg2hw.pin_out_value.key2_out.q),
// to register interface (read)
.qs (pin_out_value_key2_out_qs)
@@ -1483,15 +1483,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_pin_in_value_ac_present (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.pin_in_value.ac_present.de),
- .d (hw2reg.pin_in_value.ac_present.d ),
+ .d (hw2reg.pin_in_value.ac_present.d),
// to internal hardware
.qe (),
@@ -1508,15 +1509,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_pin_in_value_ec_rst_l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.pin_in_value.ec_rst_l.de),
- .d (hw2reg.pin_in_value.ec_rst_l.d ),
+ .d (hw2reg.pin_in_value.ec_rst_l.d),
// to internal hardware
.qe (),
@@ -1533,15 +1535,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_pin_in_value_pwrb_in (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.pin_in_value.pwrb_in.de),
- .d (hw2reg.pin_in_value.pwrb_in.d ),
+ .d (hw2reg.pin_in_value.pwrb_in.d),
// to internal hardware
.qe (),
@@ -1558,15 +1561,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_pin_in_value_key0_in (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.pin_in_value.key0_in.de),
- .d (hw2reg.pin_in_value.key0_in.d ),
+ .d (hw2reg.pin_in_value.key0_in.d),
// to internal hardware
.qe (),
@@ -1583,15 +1587,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_pin_in_value_key1_in (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.pin_in_value.key1_in.de),
- .d (hw2reg.pin_in_value.key1_in.d ),
+ .d (hw2reg.pin_in_value.key1_in.d),
// to internal hardware
.qe (),
@@ -1608,15 +1613,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_pin_in_value_key2_in (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.pin_in_value.key2_in.de),
- .d (hw2reg.pin_in_value.key2_in.d ),
+ .d (hw2reg.pin_in_value.key2_in.d),
// to internal hardware
.qe (),
@@ -1635,20 +1641,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_pwrb_in_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_pwrb_in_h2l_we & regwen_qs),
.wd (key_intr_ctl_pwrb_in_h2l_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.pwrb_in_h2l.q ),
+ .q (reg2hw.key_intr_ctl.pwrb_in_h2l.q),
// to register interface (read)
.qs (key_intr_ctl_pwrb_in_h2l_qs)
@@ -1661,20 +1667,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_key0_in_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_key0_in_h2l_we & regwen_qs),
.wd (key_intr_ctl_key0_in_h2l_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.key0_in_h2l.q ),
+ .q (reg2hw.key_intr_ctl.key0_in_h2l.q),
// to register interface (read)
.qs (key_intr_ctl_key0_in_h2l_qs)
@@ -1687,20 +1693,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_key1_in_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_key1_in_h2l_we & regwen_qs),
.wd (key_intr_ctl_key1_in_h2l_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.key1_in_h2l.q ),
+ .q (reg2hw.key_intr_ctl.key1_in_h2l.q),
// to register interface (read)
.qs (key_intr_ctl_key1_in_h2l_qs)
@@ -1713,20 +1719,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_key2_in_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_key2_in_h2l_we & regwen_qs),
.wd (key_intr_ctl_key2_in_h2l_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.key2_in_h2l.q ),
+ .q (reg2hw.key_intr_ctl.key2_in_h2l.q),
// to register interface (read)
.qs (key_intr_ctl_key2_in_h2l_qs)
@@ -1739,20 +1745,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_ac_present_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_ac_present_h2l_we & regwen_qs),
.wd (key_intr_ctl_ac_present_h2l_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.ac_present_h2l.q ),
+ .q (reg2hw.key_intr_ctl.ac_present_h2l.q),
// to register interface (read)
.qs (key_intr_ctl_ac_present_h2l_qs)
@@ -1765,20 +1771,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_ec_rst_l_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_ec_rst_l_h2l_we & regwen_qs),
.wd (key_intr_ctl_ec_rst_l_h2l_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.ec_rst_l_h2l.q ),
+ .q (reg2hw.key_intr_ctl.ec_rst_l_h2l.q),
// to register interface (read)
.qs (key_intr_ctl_ec_rst_l_h2l_qs)
@@ -1791,20 +1797,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_pwrb_in_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_pwrb_in_l2h_we & regwen_qs),
.wd (key_intr_ctl_pwrb_in_l2h_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.pwrb_in_l2h.q ),
+ .q (reg2hw.key_intr_ctl.pwrb_in_l2h.q),
// to register interface (read)
.qs (key_intr_ctl_pwrb_in_l2h_qs)
@@ -1817,20 +1823,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_key0_in_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_key0_in_l2h_we & regwen_qs),
.wd (key_intr_ctl_key0_in_l2h_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.key0_in_l2h.q ),
+ .q (reg2hw.key_intr_ctl.key0_in_l2h.q),
// to register interface (read)
.qs (key_intr_ctl_key0_in_l2h_qs)
@@ -1843,20 +1849,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_key1_in_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_key1_in_l2h_we & regwen_qs),
.wd (key_intr_ctl_key1_in_l2h_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.key1_in_l2h.q ),
+ .q (reg2hw.key_intr_ctl.key1_in_l2h.q),
// to register interface (read)
.qs (key_intr_ctl_key1_in_l2h_qs)
@@ -1869,20 +1875,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_key2_in_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_key2_in_l2h_we & regwen_qs),
.wd (key_intr_ctl_key2_in_l2h_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.key2_in_l2h.q ),
+ .q (reg2hw.key_intr_ctl.key2_in_l2h.q),
// to register interface (read)
.qs (key_intr_ctl_key2_in_l2h_qs)
@@ -1895,20 +1901,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_ac_present_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_ac_present_l2h_we & regwen_qs),
.wd (key_intr_ctl_ac_present_l2h_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.ac_present_l2h.q ),
+ .q (reg2hw.key_intr_ctl.ac_present_l2h.q),
// to register interface (read)
.qs (key_intr_ctl_ac_present_l2h_qs)
@@ -1921,20 +1927,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_key_intr_ctl_ec_rst_l_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_ctl_ec_rst_l_l2h_we & regwen_qs),
.wd (key_intr_ctl_ec_rst_l_l2h_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.key_intr_ctl.ec_rst_l_l2h.q ),
+ .q (reg2hw.key_intr_ctl.ec_rst_l_l2h.q),
// to register interface (read)
.qs (key_intr_ctl_ec_rst_l_l2h_qs)
@@ -1948,20 +1954,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_key_intr_debounce_ctl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (key_intr_debounce_ctl_we & regwen_qs),
.wd (key_intr_debounce_ctl_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.key_intr_debounce_ctl.qe),
- .q (reg2hw.key_intr_debounce_ctl.q ),
+ .q (reg2hw.key_intr_debounce_ctl.q),
// to register interface (read)
.qs (key_intr_debounce_ctl_qs)
@@ -1976,20 +1982,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_auto_block_debounce_ctl_debounce_timer (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (auto_block_debounce_ctl_debounce_timer_we & regwen_qs),
.wd (auto_block_debounce_ctl_debounce_timer_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.auto_block_debounce_ctl.debounce_timer.qe),
- .q (reg2hw.auto_block_debounce_ctl.debounce_timer.q ),
+ .q (reg2hw.auto_block_debounce_ctl.debounce_timer.q),
// to register interface (read)
.qs (auto_block_debounce_ctl_debounce_timer_qs)
@@ -2002,20 +2008,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_auto_block_debounce_ctl_auto_block_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (auto_block_debounce_ctl_auto_block_enable_we & regwen_qs),
.wd (auto_block_debounce_ctl_auto_block_enable_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.auto_block_debounce_ctl.auto_block_enable.qe),
- .q (reg2hw.auto_block_debounce_ctl.auto_block_enable.q ),
+ .q (reg2hw.auto_block_debounce_ctl.auto_block_enable.q),
// to register interface (read)
.qs (auto_block_debounce_ctl_auto_block_enable_qs)
@@ -2030,20 +2036,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key0_out_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (auto_block_out_ctl_key0_out_sel_we & regwen_qs),
.wd (auto_block_out_ctl_key0_out_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.auto_block_out_ctl.key0_out_sel.q ),
+ .q (reg2hw.auto_block_out_ctl.key0_out_sel.q),
// to register interface (read)
.qs (auto_block_out_ctl_key0_out_sel_qs)
@@ -2056,20 +2062,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key1_out_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (auto_block_out_ctl_key1_out_sel_we & regwen_qs),
.wd (auto_block_out_ctl_key1_out_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.auto_block_out_ctl.key1_out_sel.q ),
+ .q (reg2hw.auto_block_out_ctl.key1_out_sel.q),
// to register interface (read)
.qs (auto_block_out_ctl_key1_out_sel_qs)
@@ -2082,20 +2088,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key2_out_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (auto_block_out_ctl_key2_out_sel_we & regwen_qs),
.wd (auto_block_out_ctl_key2_out_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.auto_block_out_ctl.key2_out_sel.q ),
+ .q (reg2hw.auto_block_out_ctl.key2_out_sel.q),
// to register interface (read)
.qs (auto_block_out_ctl_key2_out_sel_qs)
@@ -2108,20 +2114,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key0_out_value (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (auto_block_out_ctl_key0_out_value_we & regwen_qs),
.wd (auto_block_out_ctl_key0_out_value_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.auto_block_out_ctl.key0_out_value.q ),
+ .q (reg2hw.auto_block_out_ctl.key0_out_value.q),
// to register interface (read)
.qs (auto_block_out_ctl_key0_out_value_qs)
@@ -2134,20 +2140,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key1_out_value (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (auto_block_out_ctl_key1_out_value_we & regwen_qs),
.wd (auto_block_out_ctl_key1_out_value_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.auto_block_out_ctl.key1_out_value.q ),
+ .q (reg2hw.auto_block_out_ctl.key1_out_value.q),
// to register interface (read)
.qs (auto_block_out_ctl_key1_out_value_qs)
@@ -2160,20 +2166,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_auto_block_out_ctl_key2_out_value (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (auto_block_out_ctl_key2_out_value_we & regwen_qs),
.wd (auto_block_out_ctl_key2_out_value_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.auto_block_out_ctl.key2_out_value.q ),
+ .q (reg2hw.auto_block_out_ctl.key2_out_value.q),
// to register interface (read)
.qs (auto_block_out_ctl_key2_out_value_qs)
@@ -2190,20 +2196,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_0_key0_in_sel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_0_key0_in_sel_0_we & regwen_qs),
.wd (com_sel_ctl_0_key0_in_sel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[0].key0_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[0].key0_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_0_key0_in_sel_0_qs)
@@ -2216,20 +2222,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_0_key1_in_sel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_0_key1_in_sel_0_we & regwen_qs),
.wd (com_sel_ctl_0_key1_in_sel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[0].key1_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[0].key1_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_0_key1_in_sel_0_qs)
@@ -2242,20 +2248,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_0_key2_in_sel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_0_key2_in_sel_0_we & regwen_qs),
.wd (com_sel_ctl_0_key2_in_sel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[0].key2_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[0].key2_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_0_key2_in_sel_0_qs)
@@ -2268,20 +2274,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_0_pwrb_in_sel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_0_pwrb_in_sel_0_we & regwen_qs),
.wd (com_sel_ctl_0_pwrb_in_sel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[0].pwrb_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[0].pwrb_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_0_pwrb_in_sel_0_qs)
@@ -2294,20 +2300,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_0_ac_present_sel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_0_ac_present_sel_0_we & regwen_qs),
.wd (com_sel_ctl_0_ac_present_sel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[0].ac_present_sel.q ),
+ .q (reg2hw.com_sel_ctl[0].ac_present_sel.q),
// to register interface (read)
.qs (com_sel_ctl_0_ac_present_sel_0_qs)
@@ -2323,20 +2329,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_1_key0_in_sel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_1_key0_in_sel_1_we & regwen_qs),
.wd (com_sel_ctl_1_key0_in_sel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[1].key0_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[1].key0_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_1_key0_in_sel_1_qs)
@@ -2349,20 +2355,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_1_key1_in_sel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_1_key1_in_sel_1_we & regwen_qs),
.wd (com_sel_ctl_1_key1_in_sel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[1].key1_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[1].key1_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_1_key1_in_sel_1_qs)
@@ -2375,20 +2381,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_1_key2_in_sel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_1_key2_in_sel_1_we & regwen_qs),
.wd (com_sel_ctl_1_key2_in_sel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[1].key2_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[1].key2_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_1_key2_in_sel_1_qs)
@@ -2401,20 +2407,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_1_pwrb_in_sel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_1_pwrb_in_sel_1_we & regwen_qs),
.wd (com_sel_ctl_1_pwrb_in_sel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[1].pwrb_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[1].pwrb_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_1_pwrb_in_sel_1_qs)
@@ -2427,20 +2433,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_1_ac_present_sel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_1_ac_present_sel_1_we & regwen_qs),
.wd (com_sel_ctl_1_ac_present_sel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[1].ac_present_sel.q ),
+ .q (reg2hw.com_sel_ctl[1].ac_present_sel.q),
// to register interface (read)
.qs (com_sel_ctl_1_ac_present_sel_1_qs)
@@ -2456,20 +2462,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_2_key0_in_sel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_2_key0_in_sel_2_we & regwen_qs),
.wd (com_sel_ctl_2_key0_in_sel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[2].key0_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[2].key0_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_2_key0_in_sel_2_qs)
@@ -2482,20 +2488,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_2_key1_in_sel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_2_key1_in_sel_2_we & regwen_qs),
.wd (com_sel_ctl_2_key1_in_sel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[2].key1_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[2].key1_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_2_key1_in_sel_2_qs)
@@ -2508,20 +2514,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_2_key2_in_sel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_2_key2_in_sel_2_we & regwen_qs),
.wd (com_sel_ctl_2_key2_in_sel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[2].key2_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[2].key2_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_2_key2_in_sel_2_qs)
@@ -2534,20 +2540,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_2_pwrb_in_sel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_2_pwrb_in_sel_2_we & regwen_qs),
.wd (com_sel_ctl_2_pwrb_in_sel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[2].pwrb_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[2].pwrb_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_2_pwrb_in_sel_2_qs)
@@ -2560,20 +2566,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_2_ac_present_sel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_2_ac_present_sel_2_we & regwen_qs),
.wd (com_sel_ctl_2_ac_present_sel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[2].ac_present_sel.q ),
+ .q (reg2hw.com_sel_ctl[2].ac_present_sel.q),
// to register interface (read)
.qs (com_sel_ctl_2_ac_present_sel_2_qs)
@@ -2589,20 +2595,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_3_key0_in_sel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_3_key0_in_sel_3_we & regwen_qs),
.wd (com_sel_ctl_3_key0_in_sel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[3].key0_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[3].key0_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_3_key0_in_sel_3_qs)
@@ -2615,20 +2621,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_3_key1_in_sel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_3_key1_in_sel_3_we & regwen_qs),
.wd (com_sel_ctl_3_key1_in_sel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[3].key1_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[3].key1_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_3_key1_in_sel_3_qs)
@@ -2641,20 +2647,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_3_key2_in_sel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_3_key2_in_sel_3_we & regwen_qs),
.wd (com_sel_ctl_3_key2_in_sel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[3].key2_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[3].key2_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_3_key2_in_sel_3_qs)
@@ -2667,20 +2673,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_3_pwrb_in_sel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_3_pwrb_in_sel_3_we & regwen_qs),
.wd (com_sel_ctl_3_pwrb_in_sel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[3].pwrb_in_sel.q ),
+ .q (reg2hw.com_sel_ctl[3].pwrb_in_sel.q),
// to register interface (read)
.qs (com_sel_ctl_3_pwrb_in_sel_3_qs)
@@ -2693,20 +2699,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_sel_ctl_3_ac_present_sel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_sel_ctl_3_ac_present_sel_3_we & regwen_qs),
.wd (com_sel_ctl_3_ac_present_sel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_sel_ctl[3].ac_present_sel.q ),
+ .q (reg2hw.com_sel_ctl[3].ac_present_sel.q),
// to register interface (read)
.qs (com_sel_ctl_3_ac_present_sel_3_qs)
@@ -2723,20 +2729,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_com_det_ctl_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_det_ctl_0_we & regwen_qs),
.wd (com_det_ctl_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.com_det_ctl[0].qe),
- .q (reg2hw.com_det_ctl[0].q ),
+ .q (reg2hw.com_det_ctl[0].q),
// to register interface (read)
.qs (com_det_ctl_0_qs)
@@ -2750,20 +2756,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_com_det_ctl_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_det_ctl_1_we & regwen_qs),
.wd (com_det_ctl_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.com_det_ctl[1].qe),
- .q (reg2hw.com_det_ctl[1].q ),
+ .q (reg2hw.com_det_ctl[1].q),
// to register interface (read)
.qs (com_det_ctl_1_qs)
@@ -2777,20 +2783,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_com_det_ctl_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_det_ctl_2_we & regwen_qs),
.wd (com_det_ctl_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.com_det_ctl[2].qe),
- .q (reg2hw.com_det_ctl[2].q ),
+ .q (reg2hw.com_det_ctl[2].q),
// to register interface (read)
.qs (com_det_ctl_2_qs)
@@ -2804,20 +2810,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_com_det_ctl_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_det_ctl_3_we & regwen_qs),
.wd (com_det_ctl_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.com_det_ctl[3].qe),
- .q (reg2hw.com_det_ctl[3].q ),
+ .q (reg2hw.com_det_ctl[3].q),
// to register interface (read)
.qs (com_det_ctl_3_qs)
@@ -2834,20 +2840,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_0_bat_disable_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_0_bat_disable_0_we & regwen_qs),
.wd (com_out_ctl_0_bat_disable_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[0].bat_disable.q ),
+ .q (reg2hw.com_out_ctl[0].bat_disable.q),
// to register interface (read)
.qs (com_out_ctl_0_bat_disable_0_qs)
@@ -2860,20 +2866,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_0_interrupt_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_0_interrupt_0_we & regwen_qs),
.wd (com_out_ctl_0_interrupt_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[0].interrupt.q ),
+ .q (reg2hw.com_out_ctl[0].interrupt.q),
// to register interface (read)
.qs (com_out_ctl_0_interrupt_0_qs)
@@ -2886,20 +2892,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_0_ec_rst_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_0_ec_rst_0_we & regwen_qs),
.wd (com_out_ctl_0_ec_rst_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[0].ec_rst.q ),
+ .q (reg2hw.com_out_ctl[0].ec_rst.q),
// to register interface (read)
.qs (com_out_ctl_0_ec_rst_0_qs)
@@ -2912,20 +2918,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_0_gsc_rst_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_0_gsc_rst_0_we & regwen_qs),
.wd (com_out_ctl_0_gsc_rst_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[0].gsc_rst.q ),
+ .q (reg2hw.com_out_ctl[0].gsc_rst.q),
// to register interface (read)
.qs (com_out_ctl_0_gsc_rst_0_qs)
@@ -2941,20 +2947,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_1_bat_disable_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_1_bat_disable_1_we & regwen_qs),
.wd (com_out_ctl_1_bat_disable_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[1].bat_disable.q ),
+ .q (reg2hw.com_out_ctl[1].bat_disable.q),
// to register interface (read)
.qs (com_out_ctl_1_bat_disable_1_qs)
@@ -2967,20 +2973,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_1_interrupt_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_1_interrupt_1_we & regwen_qs),
.wd (com_out_ctl_1_interrupt_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[1].interrupt.q ),
+ .q (reg2hw.com_out_ctl[1].interrupt.q),
// to register interface (read)
.qs (com_out_ctl_1_interrupt_1_qs)
@@ -2993,20 +2999,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_1_ec_rst_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_1_ec_rst_1_we & regwen_qs),
.wd (com_out_ctl_1_ec_rst_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[1].ec_rst.q ),
+ .q (reg2hw.com_out_ctl[1].ec_rst.q),
// to register interface (read)
.qs (com_out_ctl_1_ec_rst_1_qs)
@@ -3019,20 +3025,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_1_gsc_rst_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_1_gsc_rst_1_we & regwen_qs),
.wd (com_out_ctl_1_gsc_rst_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[1].gsc_rst.q ),
+ .q (reg2hw.com_out_ctl[1].gsc_rst.q),
// to register interface (read)
.qs (com_out_ctl_1_gsc_rst_1_qs)
@@ -3048,20 +3054,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_2_bat_disable_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_2_bat_disable_2_we & regwen_qs),
.wd (com_out_ctl_2_bat_disable_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[2].bat_disable.q ),
+ .q (reg2hw.com_out_ctl[2].bat_disable.q),
// to register interface (read)
.qs (com_out_ctl_2_bat_disable_2_qs)
@@ -3074,20 +3080,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_2_interrupt_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_2_interrupt_2_we & regwen_qs),
.wd (com_out_ctl_2_interrupt_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[2].interrupt.q ),
+ .q (reg2hw.com_out_ctl[2].interrupt.q),
// to register interface (read)
.qs (com_out_ctl_2_interrupt_2_qs)
@@ -3100,20 +3106,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_2_ec_rst_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_2_ec_rst_2_we & regwen_qs),
.wd (com_out_ctl_2_ec_rst_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[2].ec_rst.q ),
+ .q (reg2hw.com_out_ctl[2].ec_rst.q),
// to register interface (read)
.qs (com_out_ctl_2_ec_rst_2_qs)
@@ -3126,20 +3132,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_2_gsc_rst_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_2_gsc_rst_2_we & regwen_qs),
.wd (com_out_ctl_2_gsc_rst_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[2].gsc_rst.q ),
+ .q (reg2hw.com_out_ctl[2].gsc_rst.q),
// to register interface (read)
.qs (com_out_ctl_2_gsc_rst_2_qs)
@@ -3155,20 +3161,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_3_bat_disable_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_3_bat_disable_3_we & regwen_qs),
.wd (com_out_ctl_3_bat_disable_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[3].bat_disable.q ),
+ .q (reg2hw.com_out_ctl[3].bat_disable.q),
// to register interface (read)
.qs (com_out_ctl_3_bat_disable_3_qs)
@@ -3181,20 +3187,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_3_interrupt_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_3_interrupt_3_we & regwen_qs),
.wd (com_out_ctl_3_interrupt_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[3].interrupt.q ),
+ .q (reg2hw.com_out_ctl[3].interrupt.q),
// to register interface (read)
.qs (com_out_ctl_3_interrupt_3_qs)
@@ -3207,20 +3213,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_3_ec_rst_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_3_ec_rst_3_we & regwen_qs),
.wd (com_out_ctl_3_ec_rst_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[3].ec_rst.q ),
+ .q (reg2hw.com_out_ctl[3].ec_rst.q),
// to register interface (read)
.qs (com_out_ctl_3_ec_rst_3_qs)
@@ -3233,20 +3239,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_com_out_ctl_3_gsc_rst_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (com_out_ctl_3_gsc_rst_3_we & regwen_qs),
.wd (com_out_ctl_3_gsc_rst_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.com_out_ctl[3].gsc_rst.q ),
+ .q (reg2hw.com_out_ctl[3].gsc_rst.q),
// to register interface (read)
.qs (com_out_ctl_3_gsc_rst_3_qs)
@@ -3262,8 +3268,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_combo_intr_status_combo0_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (combo_intr_status_combo0_h2l_we),
@@ -3271,7 +3277,7 @@
// from internal hardware
.de (hw2reg.combo_intr_status.combo0_h2l.de),
- .d (hw2reg.combo_intr_status.combo0_h2l.d ),
+ .d (hw2reg.combo_intr_status.combo0_h2l.d),
// to internal hardware
.qe (),
@@ -3288,8 +3294,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_combo_intr_status_combo1_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (combo_intr_status_combo1_h2l_we),
@@ -3297,7 +3303,7 @@
// from internal hardware
.de (hw2reg.combo_intr_status.combo1_h2l.de),
- .d (hw2reg.combo_intr_status.combo1_h2l.d ),
+ .d (hw2reg.combo_intr_status.combo1_h2l.d),
// to internal hardware
.qe (),
@@ -3314,8 +3320,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_combo_intr_status_combo2_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (combo_intr_status_combo2_h2l_we),
@@ -3323,7 +3329,7 @@
// from internal hardware
.de (hw2reg.combo_intr_status.combo2_h2l.de),
- .d (hw2reg.combo_intr_status.combo2_h2l.d ),
+ .d (hw2reg.combo_intr_status.combo2_h2l.d),
// to internal hardware
.qe (),
@@ -3340,8 +3346,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_combo_intr_status_combo3_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (combo_intr_status_combo3_h2l_we),
@@ -3349,7 +3355,7 @@
// from internal hardware
.de (hw2reg.combo_intr_status.combo3_h2l.de),
- .d (hw2reg.combo_intr_status.combo3_h2l.d ),
+ .d (hw2reg.combo_intr_status.combo3_h2l.d),
// to internal hardware
.qe (),
@@ -3368,8 +3374,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_pwrb_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_pwrb_h2l_we),
@@ -3377,7 +3383,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.pwrb_h2l.de),
- .d (hw2reg.key_intr_status.pwrb_h2l.d ),
+ .d (hw2reg.key_intr_status.pwrb_h2l.d),
// to internal hardware
.qe (),
@@ -3394,8 +3400,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_key0_in_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_key0_in_h2l_we),
@@ -3403,7 +3409,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.key0_in_h2l.de),
- .d (hw2reg.key_intr_status.key0_in_h2l.d ),
+ .d (hw2reg.key_intr_status.key0_in_h2l.d),
// to internal hardware
.qe (),
@@ -3420,8 +3426,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_key1_in_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_key1_in_h2l_we),
@@ -3429,7 +3435,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.key1_in_h2l.de),
- .d (hw2reg.key_intr_status.key1_in_h2l.d ),
+ .d (hw2reg.key_intr_status.key1_in_h2l.d),
// to internal hardware
.qe (),
@@ -3446,8 +3452,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_key2_in_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_key2_in_h2l_we),
@@ -3455,7 +3461,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.key2_in_h2l.de),
- .d (hw2reg.key_intr_status.key2_in_h2l.d ),
+ .d (hw2reg.key_intr_status.key2_in_h2l.d),
// to internal hardware
.qe (),
@@ -3472,8 +3478,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_ac_present_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_ac_present_h2l_we),
@@ -3481,7 +3487,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.ac_present_h2l.de),
- .d (hw2reg.key_intr_status.ac_present_h2l.d ),
+ .d (hw2reg.key_intr_status.ac_present_h2l.d),
// to internal hardware
.qe (),
@@ -3498,8 +3504,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_ec_rst_l_h2l (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_ec_rst_l_h2l_we),
@@ -3507,7 +3513,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.ec_rst_l_h2l.de),
- .d (hw2reg.key_intr_status.ec_rst_l_h2l.d ),
+ .d (hw2reg.key_intr_status.ec_rst_l_h2l.d),
// to internal hardware
.qe (),
@@ -3524,8 +3530,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_pwrb_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_pwrb_l2h_we),
@@ -3533,7 +3539,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.pwrb_l2h.de),
- .d (hw2reg.key_intr_status.pwrb_l2h.d ),
+ .d (hw2reg.key_intr_status.pwrb_l2h.d),
// to internal hardware
.qe (),
@@ -3550,8 +3556,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_key0_in_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_key0_in_l2h_we),
@@ -3559,7 +3565,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.key0_in_l2h.de),
- .d (hw2reg.key_intr_status.key0_in_l2h.d ),
+ .d (hw2reg.key_intr_status.key0_in_l2h.d),
// to internal hardware
.qe (),
@@ -3576,8 +3582,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_key1_in_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_key1_in_l2h_we),
@@ -3585,7 +3591,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.key1_in_l2h.de),
- .d (hw2reg.key_intr_status.key1_in_l2h.d ),
+ .d (hw2reg.key_intr_status.key1_in_l2h.d),
// to internal hardware
.qe (),
@@ -3602,8 +3608,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_key2_in_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_key2_in_l2h_we),
@@ -3611,7 +3617,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.key2_in_l2h.de),
- .d (hw2reg.key_intr_status.key2_in_l2h.d ),
+ .d (hw2reg.key_intr_status.key2_in_l2h.d),
// to internal hardware
.qe (),
@@ -3628,8 +3634,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_ac_present_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_ac_present_l2h_we),
@@ -3637,7 +3643,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.ac_present_l2h.de),
- .d (hw2reg.key_intr_status.ac_present_l2h.d ),
+ .d (hw2reg.key_intr_status.ac_present_l2h.d),
// to internal hardware
.qe (),
@@ -3654,8 +3660,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_key_intr_status_ec_rst_l_l2h (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (key_intr_status_ec_rst_l_l2h_we),
@@ -3663,7 +3669,7 @@
// from internal hardware
.de (hw2reg.key_intr_status.ec_rst_l_l2h.de),
- .d (hw2reg.key_intr_status.ec_rst_l_l2h.d ),
+ .d (hw2reg.key_intr_status.ec_rst_l_l2h.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/trial1/rtl/trial1_reg_top.sv b/hw/ip/trial1/rtl/trial1_reg_top.sv
index f700b42..0df6352 100644
--- a/hw/ip/trial1/rtl/trial1_reg_top.sv
+++ b/hw/ip/trial1/rtl/trial1_reg_top.sv
@@ -203,8 +203,8 @@
.SWACCESS("RW"),
.RESVAL (32'hbc614e)
) u_rwtype0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype0_we),
@@ -212,11 +212,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype0.q ),
+ .q (reg2hw.rwtype0.q),
// to register interface (read)
.qs (rwtype0_qs)
@@ -231,8 +231,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_rwtype1_field0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype1_field0_we),
@@ -240,11 +240,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype1.field0.q ),
+ .q (reg2hw.rwtype1.field0.q),
// to register interface (read)
.qs (rwtype1_field0_qs)
@@ -257,8 +257,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rwtype1_field1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype1_field1_we),
@@ -266,11 +266,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype1.field1.q ),
+ .q (reg2hw.rwtype1.field1.q),
// to register interface (read)
.qs (rwtype1_field1_qs)
@@ -283,8 +283,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_rwtype1_field4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype1_field4_we),
@@ -292,11 +292,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype1.field4.q ),
+ .q (reg2hw.rwtype1.field4.q),
// to register interface (read)
.qs (rwtype1_field4_qs)
@@ -309,8 +309,8 @@
.SWACCESS("RW"),
.RESVAL (8'h64)
) u_rwtype1_field15_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype1_field15_8_we),
@@ -318,11 +318,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype1.field15_8.q ),
+ .q (reg2hw.rwtype1.field15_8.q),
// to register interface (read)
.qs (rwtype1_field15_8_qs)
@@ -336,8 +336,8 @@
.SWACCESS("RW"),
.RESVAL (32'h4000400)
) u_rwtype2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype2_we),
@@ -345,11 +345,11 @@
// from internal hardware
.de (hw2reg.rwtype2.de),
- .d (hw2reg.rwtype2.d ),
+ .d (hw2reg.rwtype2.d),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype2.q ),
+ .q (reg2hw.rwtype2.q),
// to register interface (read)
.qs (rwtype2_qs)
@@ -364,8 +364,8 @@
.SWACCESS("RW"),
.RESVAL (16'hcc55)
) u_rwtype3_field0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype3_field0_we),
@@ -373,11 +373,11 @@
// from internal hardware
.de (hw2reg.rwtype3.field0.de),
- .d (hw2reg.rwtype3.field0.d ),
+ .d (hw2reg.rwtype3.field0.d),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype3.field0.q ),
+ .q (reg2hw.rwtype3.field0.q),
// to register interface (read)
.qs (rwtype3_field0_qs)
@@ -390,8 +390,8 @@
.SWACCESS("RW"),
.RESVAL (16'hee66)
) u_rwtype3_field1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype3_field1_we),
@@ -399,11 +399,11 @@
// from internal hardware
.de (hw2reg.rwtype3.field1.de),
- .d (hw2reg.rwtype3.field1.d ),
+ .d (hw2reg.rwtype3.field1.d),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype3.field1.q ),
+ .q (reg2hw.rwtype3.field1.q),
// to register interface (read)
.qs (rwtype3_field1_qs)
@@ -418,8 +418,8 @@
.SWACCESS("RW"),
.RESVAL (16'h4000)
) u_rwtype4_field0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype4_field0_we),
@@ -427,11 +427,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype4.field0.q ),
+ .q (reg2hw.rwtype4.field0.q),
// to register interface (read)
.qs (rwtype4_field0_qs)
@@ -444,8 +444,8 @@
.SWACCESS("RW"),
.RESVAL (16'h8000)
) u_rwtype4_field1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype4_field1_we),
@@ -453,11 +453,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rwtype4.field1.q ),
+ .q (reg2hw.rwtype4.field1.q),
// to register interface (read)
.qs (rwtype4_field1_qs)
@@ -471,19 +471,20 @@
.SWACCESS("RO"),
.RESVAL (32'h11111111)
) u_rotype0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.rotype0.de),
- .d (hw2reg.rotype0.d ),
+ .d (hw2reg.rotype0.d),
// to internal hardware
.qe (),
- .q (reg2hw.rotype0.q ),
+ .q (reg2hw.rotype0.q),
// to register interface (read)
.qs (rotype0_qs)
@@ -497,8 +498,8 @@
.SWACCESS("W1C"),
.RESVAL (32'hbbccddee)
) u_w1ctype0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (w1ctype0_we),
@@ -506,11 +507,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.w1ctype0.q ),
+ .q (reg2hw.w1ctype0.q),
// to register interface (read)
.qs (w1ctype0_qs)
@@ -525,8 +526,8 @@
.SWACCESS("W1C"),
.RESVAL (16'heeee)
) u_w1ctype1_field0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (w1ctype1_field0_we),
@@ -534,11 +535,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.w1ctype1.field0.q ),
+ .q (reg2hw.w1ctype1.field0.q),
// to register interface (read)
.qs (w1ctype1_field0_qs)
@@ -551,8 +552,8 @@
.SWACCESS("W1C"),
.RESVAL (16'h7777)
) u_w1ctype1_field1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (w1ctype1_field1_we),
@@ -560,11 +561,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.w1ctype1.field1.q ),
+ .q (reg2hw.w1ctype1.field1.q),
// to register interface (read)
.qs (w1ctype1_field1_qs)
@@ -578,8 +579,8 @@
.SWACCESS("W1C"),
.RESVAL (32'haa775566)
) u_w1ctype2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (w1ctype2_we),
@@ -587,11 +588,11 @@
// from internal hardware
.de (hw2reg.w1ctype2.de),
- .d (hw2reg.w1ctype2.d ),
+ .d (hw2reg.w1ctype2.d),
// to internal hardware
.qe (),
- .q (reg2hw.w1ctype2.q ),
+ .q (reg2hw.w1ctype2.q),
// to register interface (read)
.qs (w1ctype2_qs)
@@ -605,8 +606,8 @@
.SWACCESS("W1S"),
.RESVAL (32'h11224488)
) u_w1stype2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (w1stype2_we),
@@ -614,11 +615,11 @@
// from internal hardware
.de (hw2reg.w1stype2.de),
- .d (hw2reg.w1stype2.d ),
+ .d (hw2reg.w1stype2.d),
// to internal hardware
.qe (),
- .q (reg2hw.w1stype2.q ),
+ .q (reg2hw.w1stype2.q),
// to register interface (read)
.qs (w1stype2_qs)
@@ -632,8 +633,8 @@
.SWACCESS("W0C"),
.RESVAL (32'hfec8137f)
) u_w0ctype2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (w0ctype2_we),
@@ -641,11 +642,11 @@
// from internal hardware
.de (hw2reg.w0ctype2.de),
- .d (hw2reg.w0ctype2.d ),
+ .d (hw2reg.w0ctype2.d),
// to internal hardware
.qe (),
- .q (reg2hw.w0ctype2.q ),
+ .q (reg2hw.w0ctype2.q),
// to register interface (read)
.qs (w0ctype2_qs)
@@ -659,8 +660,8 @@
.SWACCESS("W1C"),
.RESVAL (32'haa775566)
) u_r0w1ctype2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (r0w1ctype2_we),
@@ -668,12 +669,13 @@
// from internal hardware
.de (hw2reg.r0w1ctype2.de),
- .d (hw2reg.r0w1ctype2.d ),
+ .d (hw2reg.r0w1ctype2.d),
// to internal hardware
.qe (),
- .q (reg2hw.r0w1ctype2.q ),
+ .q (reg2hw.r0w1ctype2.q),
+ // to register interface (read)
.qs ()
);
@@ -685,8 +687,8 @@
.SWACCESS("RC"),
.RESVAL (32'h77443399)
) u_rctype0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rctype0_we),
@@ -694,11 +696,11 @@
// from internal hardware
.de (hw2reg.rctype0.de),
- .d (hw2reg.rctype0.d ),
+ .d (hw2reg.rctype0.d),
// to internal hardware
.qe (),
- .q (reg2hw.rctype0.q ),
+ .q (reg2hw.rctype0.q),
// to register interface (read)
.qs (rctype0_qs)
@@ -712,8 +714,8 @@
.SWACCESS("WO"),
.RESVAL (32'h11223344)
) u_wotype0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wotype0_we),
@@ -721,12 +723,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wotype0.q ),
+ .q (reg2hw.wotype0.q),
+ // to register interface (read)
.qs ()
);
@@ -739,8 +742,8 @@
.SWACCESS("RW"),
.RESVAL (4'h1)
) u_mixtype0_field0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mixtype0_field0_we),
@@ -748,11 +751,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mixtype0.field0.q ),
+ .q (reg2hw.mixtype0.field0.q),
// to register interface (read)
.qs (mixtype0_field0_qs)
@@ -765,8 +768,8 @@
.SWACCESS("RW"),
.RESVAL (4'h2)
) u_mixtype0_field1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mixtype0_field1_we),
@@ -774,11 +777,11 @@
// from internal hardware
.de (hw2reg.mixtype0.field1.de),
- .d (hw2reg.mixtype0.field1.d ),
+ .d (hw2reg.mixtype0.field1.d),
// to internal hardware
.qe (),
- .q (reg2hw.mixtype0.field1.q ),
+ .q (reg2hw.mixtype0.field1.q),
// to register interface (read)
.qs (mixtype0_field1_qs)
@@ -791,19 +794,20 @@
.SWACCESS("RO"),
.RESVAL (4'h3)
) u_mixtype0_field2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mixtype0.field2.q ),
+ .q (reg2hw.mixtype0.field2.q),
// to register interface (read)
.qs (mixtype0_field2_qs)
@@ -816,19 +820,20 @@
.SWACCESS("RO"),
.RESVAL (4'h4)
) u_mixtype0_field3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.mixtype0.field3.de),
- .d (hw2reg.mixtype0.field3.d ),
+ .d (hw2reg.mixtype0.field3.d),
// to internal hardware
.qe (),
- .q (reg2hw.mixtype0.field3.q ),
+ .q (reg2hw.mixtype0.field3.q),
// to register interface (read)
.qs (mixtype0_field3_qs)
@@ -841,8 +846,8 @@
.SWACCESS("W1C"),
.RESVAL (4'h5)
) u_mixtype0_field4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mixtype0_field4_we),
@@ -850,11 +855,11 @@
// from internal hardware
.de (hw2reg.mixtype0.field4.de),
- .d (hw2reg.mixtype0.field4.d ),
+ .d (hw2reg.mixtype0.field4.d),
// to internal hardware
.qe (),
- .q (reg2hw.mixtype0.field4.q ),
+ .q (reg2hw.mixtype0.field4.q),
// to register interface (read)
.qs (mixtype0_field4_qs)
@@ -867,8 +872,8 @@
.SWACCESS("W1S"),
.RESVAL (4'h6)
) u_mixtype0_field5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mixtype0_field5_we),
@@ -876,11 +881,11 @@
// from internal hardware
.de (hw2reg.mixtype0.field5.de),
- .d (hw2reg.mixtype0.field5.d ),
+ .d (hw2reg.mixtype0.field5.d),
// to internal hardware
.qe (),
- .q (reg2hw.mixtype0.field5.q ),
+ .q (reg2hw.mixtype0.field5.q),
// to register interface (read)
.qs (mixtype0_field5_qs)
@@ -893,8 +898,8 @@
.SWACCESS("RC"),
.RESVAL (4'h7)
) u_mixtype0_field6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mixtype0_field6_we),
@@ -902,11 +907,11 @@
// from internal hardware
.de (hw2reg.mixtype0.field6.de),
- .d (hw2reg.mixtype0.field6.d ),
+ .d (hw2reg.mixtype0.field6.d),
// to internal hardware
.qe (),
- .q (reg2hw.mixtype0.field6.q ),
+ .q (reg2hw.mixtype0.field6.q),
// to register interface (read)
.qs (mixtype0_field6_qs)
@@ -919,8 +924,8 @@
.SWACCESS("WO"),
.RESVAL (4'h8)
) u_mixtype0_field7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mixtype0_field7_we),
@@ -928,12 +933,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mixtype0.field7.q ),
+ .q (reg2hw.mixtype0.field7.q),
+ // to register interface (read)
.qs ()
);
@@ -945,8 +951,8 @@
.SWACCESS("RW"),
.RESVAL (32'hbabababa)
) u_rwtype5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype5_we),
@@ -954,11 +960,11 @@
// from internal hardware
.de (hw2reg.rwtype5.de),
- .d (hw2reg.rwtype5.d ),
+ .d (hw2reg.rwtype5.d),
// to internal hardware
.qe (reg2hw.rwtype5.qe),
- .q (reg2hw.rwtype5.q ),
+ .q (reg2hw.rwtype5.q),
// to register interface (read)
.qs (rwtype5_qs)
@@ -976,7 +982,7 @@
.d (hw2reg.rwtype6.d),
.qre (),
.qe (reg2hw.rwtype6.qe),
- .q (reg2hw.rwtype6.q ),
+ .q (reg2hw.rwtype6.q),
.qs (rwtype6_qs)
);
@@ -992,7 +998,7 @@
.d (hw2reg.rotype1.d),
.qre (),
.qe (),
- .q (reg2hw.rotype1.q ),
+ .q (reg2hw.rotype1.q),
.qs (rotype1_qs)
);
@@ -1021,8 +1027,8 @@
.SWACCESS("RW"),
.RESVAL (32'hf6f6f6f6)
) u_rwtype7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rwtype7_we),
@@ -1030,7 +1036,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
diff --git a/hw/ip/uart/rtl/uart_reg_top.sv b/hw/ip/uart/rtl/uart_reg_top.sv
index 597746b..30b706d 100644
--- a/hw/ip/uart/rtl/uart_reg_top.sv
+++ b/hw/ip/uart/rtl/uart_reg_top.sv
@@ -249,8 +249,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_tx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_tx_watermark_we),
@@ -258,11 +258,11 @@
// from internal hardware
.de (hw2reg.intr_state.tx_watermark.de),
- .d (hw2reg.intr_state.tx_watermark.d ),
+ .d (hw2reg.intr_state.tx_watermark.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.tx_watermark.q ),
+ .q (reg2hw.intr_state.tx_watermark.q),
// to register interface (read)
.qs (intr_state_tx_watermark_qs)
@@ -275,8 +275,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_watermark_we),
@@ -284,11 +284,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_watermark.de),
- .d (hw2reg.intr_state.rx_watermark.d ),
+ .d (hw2reg.intr_state.rx_watermark.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_watermark.q ),
+ .q (reg2hw.intr_state.rx_watermark.q),
// to register interface (read)
.qs (intr_state_rx_watermark_qs)
@@ -301,8 +301,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_tx_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_tx_empty_we),
@@ -310,11 +310,11 @@
// from internal hardware
.de (hw2reg.intr_state.tx_empty.de),
- .d (hw2reg.intr_state.tx_empty.d ),
+ .d (hw2reg.intr_state.tx_empty.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.tx_empty.q ),
+ .q (reg2hw.intr_state.tx_empty.q),
// to register interface (read)
.qs (intr_state_tx_empty_qs)
@@ -327,8 +327,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_overflow_we),
@@ -336,11 +336,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_overflow.de),
- .d (hw2reg.intr_state.rx_overflow.d ),
+ .d (hw2reg.intr_state.rx_overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_overflow.q ),
+ .q (reg2hw.intr_state.rx_overflow.q),
// to register interface (read)
.qs (intr_state_rx_overflow_qs)
@@ -353,8 +353,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_frame_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_frame_err_we),
@@ -362,11 +362,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_frame_err.de),
- .d (hw2reg.intr_state.rx_frame_err.d ),
+ .d (hw2reg.intr_state.rx_frame_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_frame_err.q ),
+ .q (reg2hw.intr_state.rx_frame_err.q),
// to register interface (read)
.qs (intr_state_rx_frame_err_qs)
@@ -379,8 +379,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_break_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_break_err_we),
@@ -388,11 +388,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_break_err.de),
- .d (hw2reg.intr_state.rx_break_err.d ),
+ .d (hw2reg.intr_state.rx_break_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_break_err.q ),
+ .q (reg2hw.intr_state.rx_break_err.q),
// to register interface (read)
.qs (intr_state_rx_break_err_qs)
@@ -405,8 +405,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_timeout (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_timeout_we),
@@ -414,11 +414,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_timeout.de),
- .d (hw2reg.intr_state.rx_timeout.d ),
+ .d (hw2reg.intr_state.rx_timeout.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_timeout.q ),
+ .q (reg2hw.intr_state.rx_timeout.q),
// to register interface (read)
.qs (intr_state_rx_timeout_qs)
@@ -431,8 +431,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_parity_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_parity_err_we),
@@ -440,11 +440,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_parity_err.de),
- .d (hw2reg.intr_state.rx_parity_err.d ),
+ .d (hw2reg.intr_state.rx_parity_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_parity_err.q ),
+ .q (reg2hw.intr_state.rx_parity_err.q),
// to register interface (read)
.qs (intr_state_rx_parity_err_qs)
@@ -459,8 +459,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_tx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_tx_watermark_we),
@@ -468,11 +468,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.tx_watermark.q ),
+ .q (reg2hw.intr_enable.tx_watermark.q),
// to register interface (read)
.qs (intr_enable_tx_watermark_qs)
@@ -485,8 +485,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_watermark_we),
@@ -494,11 +494,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_watermark.q ),
+ .q (reg2hw.intr_enable.rx_watermark.q),
// to register interface (read)
.qs (intr_enable_rx_watermark_qs)
@@ -511,8 +511,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_tx_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_tx_empty_we),
@@ -520,11 +520,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.tx_empty.q ),
+ .q (reg2hw.intr_enable.tx_empty.q),
// to register interface (read)
.qs (intr_enable_tx_empty_qs)
@@ -537,8 +537,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_overflow_we),
@@ -546,11 +546,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_overflow.q ),
+ .q (reg2hw.intr_enable.rx_overflow.q),
// to register interface (read)
.qs (intr_enable_rx_overflow_qs)
@@ -563,8 +563,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_frame_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_frame_err_we),
@@ -572,11 +572,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_frame_err.q ),
+ .q (reg2hw.intr_enable.rx_frame_err.q),
// to register interface (read)
.qs (intr_enable_rx_frame_err_qs)
@@ -589,8 +589,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_break_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_break_err_we),
@@ -598,11 +598,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_break_err.q ),
+ .q (reg2hw.intr_enable.rx_break_err.q),
// to register interface (read)
.qs (intr_enable_rx_break_err_qs)
@@ -615,8 +615,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_timeout (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_timeout_we),
@@ -624,11 +624,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_timeout.q ),
+ .q (reg2hw.intr_enable.rx_timeout.q),
// to register interface (read)
.qs (intr_enable_rx_timeout_qs)
@@ -641,8 +641,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_parity_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_parity_err_we),
@@ -650,11 +650,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_parity_err.q ),
+ .q (reg2hw.intr_enable.rx_parity_err.q),
// to register interface (read)
.qs (intr_enable_rx_parity_err_qs)
@@ -673,7 +673,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.tx_watermark.qe),
- .q (reg2hw.intr_test.tx_watermark.q ),
+ .q (reg2hw.intr_test.tx_watermark.q),
.qs ()
);
@@ -688,7 +688,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_watermark.qe),
- .q (reg2hw.intr_test.rx_watermark.q ),
+ .q (reg2hw.intr_test.rx_watermark.q),
.qs ()
);
@@ -703,7 +703,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.tx_empty.qe),
- .q (reg2hw.intr_test.tx_empty.q ),
+ .q (reg2hw.intr_test.tx_empty.q),
.qs ()
);
@@ -718,7 +718,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_overflow.qe),
- .q (reg2hw.intr_test.rx_overflow.q ),
+ .q (reg2hw.intr_test.rx_overflow.q),
.qs ()
);
@@ -733,7 +733,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_frame_err.qe),
- .q (reg2hw.intr_test.rx_frame_err.q ),
+ .q (reg2hw.intr_test.rx_frame_err.q),
.qs ()
);
@@ -748,7 +748,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_break_err.qe),
- .q (reg2hw.intr_test.rx_break_err.q ),
+ .q (reg2hw.intr_test.rx_break_err.q),
.qs ()
);
@@ -763,7 +763,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_timeout.qe),
- .q (reg2hw.intr_test.rx_timeout.q ),
+ .q (reg2hw.intr_test.rx_timeout.q),
.qs ()
);
@@ -778,7 +778,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_parity_err.qe),
- .q (reg2hw.intr_test.rx_parity_err.q ),
+ .q (reg2hw.intr_test.rx_parity_err.q),
.qs ()
);
@@ -791,8 +791,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_tx (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_tx_we),
@@ -800,11 +800,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.tx.q ),
+ .q (reg2hw.ctrl.tx.q),
// to register interface (read)
.qs (ctrl_tx_qs)
@@ -817,8 +817,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_rx (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_rx_we),
@@ -826,11 +826,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.rx.q ),
+ .q (reg2hw.ctrl.rx.q),
// to register interface (read)
.qs (ctrl_rx_qs)
@@ -843,8 +843,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_nf (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_nf_we),
@@ -852,11 +852,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.nf.q ),
+ .q (reg2hw.ctrl.nf.q),
// to register interface (read)
.qs (ctrl_nf_qs)
@@ -869,8 +869,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_slpbk (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_slpbk_we),
@@ -878,11 +878,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.slpbk.q ),
+ .q (reg2hw.ctrl.slpbk.q),
// to register interface (read)
.qs (ctrl_slpbk_qs)
@@ -895,8 +895,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_llpbk (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_llpbk_we),
@@ -904,11 +904,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.llpbk.q ),
+ .q (reg2hw.ctrl.llpbk.q),
// to register interface (read)
.qs (ctrl_llpbk_qs)
@@ -921,8 +921,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_parity_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_parity_en_we),
@@ -930,11 +930,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.parity_en.q ),
+ .q (reg2hw.ctrl.parity_en.q),
// to register interface (read)
.qs (ctrl_parity_en_qs)
@@ -947,8 +947,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_parity_odd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_parity_odd_we),
@@ -956,11 +956,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.parity_odd.q ),
+ .q (reg2hw.ctrl.parity_odd.q),
// to register interface (read)
.qs (ctrl_parity_odd_qs)
@@ -973,8 +973,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ctrl_rxblvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_rxblvl_we),
@@ -982,11 +982,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.rxblvl.q ),
+ .q (reg2hw.ctrl.rxblvl.q),
// to register interface (read)
.qs (ctrl_rxblvl_qs)
@@ -999,8 +999,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_ctrl_nco (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_nco_we),
@@ -1008,11 +1008,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.nco.q ),
+ .q (reg2hw.ctrl.nco.q),
// to register interface (read)
.qs (ctrl_nco_qs)
@@ -1031,7 +1031,7 @@
.d (hw2reg.status.txfull.d),
.qre (reg2hw.status.txfull.re),
.qe (),
- .q (reg2hw.status.txfull.q ),
+ .q (reg2hw.status.txfull.q),
.qs (status_txfull_qs)
);
@@ -1046,7 +1046,7 @@
.d (hw2reg.status.rxfull.d),
.qre (reg2hw.status.rxfull.re),
.qe (),
- .q (reg2hw.status.rxfull.q ),
+ .q (reg2hw.status.rxfull.q),
.qs (status_rxfull_qs)
);
@@ -1061,7 +1061,7 @@
.d (hw2reg.status.txempty.d),
.qre (reg2hw.status.txempty.re),
.qe (),
- .q (reg2hw.status.txempty.q ),
+ .q (reg2hw.status.txempty.q),
.qs (status_txempty_qs)
);
@@ -1076,7 +1076,7 @@
.d (hw2reg.status.txidle.d),
.qre (reg2hw.status.txidle.re),
.qe (),
- .q (reg2hw.status.txidle.q ),
+ .q (reg2hw.status.txidle.q),
.qs (status_txidle_qs)
);
@@ -1091,7 +1091,7 @@
.d (hw2reg.status.rxidle.d),
.qre (reg2hw.status.rxidle.re),
.qe (),
- .q (reg2hw.status.rxidle.q ),
+ .q (reg2hw.status.rxidle.q),
.qs (status_rxidle_qs)
);
@@ -1106,7 +1106,7 @@
.d (hw2reg.status.rxempty.d),
.qre (reg2hw.status.rxempty.re),
.qe (),
- .q (reg2hw.status.rxempty.q ),
+ .q (reg2hw.status.rxempty.q),
.qs (status_rxempty_qs)
);
@@ -1122,7 +1122,7 @@
.d (hw2reg.rdata.d),
.qre (reg2hw.rdata.re),
.qe (),
- .q (reg2hw.rdata.q ),
+ .q (reg2hw.rdata.q),
.qs (rdata_qs)
);
@@ -1134,8 +1134,8 @@
.SWACCESS("WO"),
.RESVAL (8'h0)
) u_wdata (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wdata_we),
@@ -1143,12 +1143,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.wdata.qe),
- .q (reg2hw.wdata.q ),
+ .q (reg2hw.wdata.q),
+ // to register interface (read)
.qs ()
);
@@ -1161,8 +1162,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fifo_ctrl_rxrst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_rxrst_we),
@@ -1170,12 +1171,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fifo_ctrl.rxrst.qe),
- .q (reg2hw.fifo_ctrl.rxrst.q ),
+ .q (reg2hw.fifo_ctrl.rxrst.q),
+ // to register interface (read)
.qs ()
);
@@ -1186,8 +1188,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_fifo_ctrl_txrst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_txrst_we),
@@ -1195,12 +1197,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.fifo_ctrl.txrst.qe),
- .q (reg2hw.fifo_ctrl.txrst.q ),
+ .q (reg2hw.fifo_ctrl.txrst.q),
+ // to register interface (read)
.qs ()
);
@@ -1211,8 +1214,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_fifo_ctrl_rxilvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_rxilvl_we),
@@ -1220,11 +1223,11 @@
// from internal hardware
.de (hw2reg.fifo_ctrl.rxilvl.de),
- .d (hw2reg.fifo_ctrl.rxilvl.d ),
+ .d (hw2reg.fifo_ctrl.rxilvl.d),
// to internal hardware
.qe (reg2hw.fifo_ctrl.rxilvl.qe),
- .q (reg2hw.fifo_ctrl.rxilvl.q ),
+ .q (reg2hw.fifo_ctrl.rxilvl.q),
// to register interface (read)
.qs (fifo_ctrl_rxilvl_qs)
@@ -1237,8 +1240,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_fifo_ctrl_txilvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_txilvl_we),
@@ -1246,11 +1249,11 @@
// from internal hardware
.de (hw2reg.fifo_ctrl.txilvl.de),
- .d (hw2reg.fifo_ctrl.txilvl.d ),
+ .d (hw2reg.fifo_ctrl.txilvl.d),
// to internal hardware
.qe (reg2hw.fifo_ctrl.txilvl.qe),
- .q (reg2hw.fifo_ctrl.txilvl.q ),
+ .q (reg2hw.fifo_ctrl.txilvl.q),
// to register interface (read)
.qs (fifo_ctrl_txilvl_qs)
@@ -1297,8 +1300,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ovrd_txen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ovrd_txen_we),
@@ -1306,11 +1309,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ovrd.txen.q ),
+ .q (reg2hw.ovrd.txen.q),
// to register interface (read)
.qs (ovrd_txen_qs)
@@ -1323,8 +1326,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ovrd_txval (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ovrd_txval_we),
@@ -1332,11 +1335,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ovrd.txval.q ),
+ .q (reg2hw.ovrd.txval.q),
// to register interface (read)
.qs (ovrd_txval_qs)
@@ -1367,8 +1370,8 @@
.SWACCESS("RW"),
.RESVAL (24'h0)
) u_timeout_ctrl_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timeout_ctrl_val_we),
@@ -1376,11 +1379,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timeout_ctrl.val.q ),
+ .q (reg2hw.timeout_ctrl.val.q),
// to register interface (read)
.qs (timeout_ctrl_val_qs)
@@ -1393,8 +1396,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_timeout_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timeout_ctrl_en_we),
@@ -1402,11 +1405,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timeout_ctrl.en.q ),
+ .q (reg2hw.timeout_ctrl.en.q),
// to register interface (read)
.qs (timeout_ctrl_en_qs)
diff --git a/hw/ip/usbdev/rtl/usbdev_reg_top.sv b/hw/ip/usbdev/rtl/usbdev_reg_top.sv
index e89d077..36adc4c 100644
--- a/hw/ip/usbdev/rtl/usbdev_reg_top.sv
+++ b/hw/ip/usbdev/rtl/usbdev_reg_top.sv
@@ -759,8 +759,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_pkt_received (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_pkt_received_we),
@@ -768,11 +768,11 @@
// from internal hardware
.de (hw2reg.intr_state.pkt_received.de),
- .d (hw2reg.intr_state.pkt_received.d ),
+ .d (hw2reg.intr_state.pkt_received.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.pkt_received.q ),
+ .q (reg2hw.intr_state.pkt_received.q),
// to register interface (read)
.qs (intr_state_pkt_received_qs)
@@ -785,8 +785,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_pkt_sent (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_pkt_sent_we),
@@ -794,11 +794,11 @@
// from internal hardware
.de (hw2reg.intr_state.pkt_sent.de),
- .d (hw2reg.intr_state.pkt_sent.d ),
+ .d (hw2reg.intr_state.pkt_sent.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.pkt_sent.q ),
+ .q (reg2hw.intr_state.pkt_sent.q),
// to register interface (read)
.qs (intr_state_pkt_sent_qs)
@@ -811,8 +811,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_disconnected (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_disconnected_we),
@@ -820,11 +820,11 @@
// from internal hardware
.de (hw2reg.intr_state.disconnected.de),
- .d (hw2reg.intr_state.disconnected.d ),
+ .d (hw2reg.intr_state.disconnected.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.disconnected.q ),
+ .q (reg2hw.intr_state.disconnected.q),
// to register interface (read)
.qs (intr_state_disconnected_qs)
@@ -837,8 +837,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_host_lost (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_host_lost_we),
@@ -846,11 +846,11 @@
// from internal hardware
.de (hw2reg.intr_state.host_lost.de),
- .d (hw2reg.intr_state.host_lost.d ),
+ .d (hw2reg.intr_state.host_lost.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.host_lost.q ),
+ .q (reg2hw.intr_state.host_lost.q),
// to register interface (read)
.qs (intr_state_host_lost_qs)
@@ -863,8 +863,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_link_reset (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_link_reset_we),
@@ -872,11 +872,11 @@
// from internal hardware
.de (hw2reg.intr_state.link_reset.de),
- .d (hw2reg.intr_state.link_reset.d ),
+ .d (hw2reg.intr_state.link_reset.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.link_reset.q ),
+ .q (reg2hw.intr_state.link_reset.q),
// to register interface (read)
.qs (intr_state_link_reset_qs)
@@ -889,8 +889,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_link_suspend (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_link_suspend_we),
@@ -898,11 +898,11 @@
// from internal hardware
.de (hw2reg.intr_state.link_suspend.de),
- .d (hw2reg.intr_state.link_suspend.d ),
+ .d (hw2reg.intr_state.link_suspend.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.link_suspend.q ),
+ .q (reg2hw.intr_state.link_suspend.q),
// to register interface (read)
.qs (intr_state_link_suspend_qs)
@@ -915,8 +915,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_link_resume (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_link_resume_we),
@@ -924,11 +924,11 @@
// from internal hardware
.de (hw2reg.intr_state.link_resume.de),
- .d (hw2reg.intr_state.link_resume.d ),
+ .d (hw2reg.intr_state.link_resume.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.link_resume.q ),
+ .q (reg2hw.intr_state.link_resume.q),
// to register interface (read)
.qs (intr_state_link_resume_qs)
@@ -941,8 +941,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_av_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_av_empty_we),
@@ -950,11 +950,11 @@
// from internal hardware
.de (hw2reg.intr_state.av_empty.de),
- .d (hw2reg.intr_state.av_empty.d ),
+ .d (hw2reg.intr_state.av_empty.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.av_empty.q ),
+ .q (reg2hw.intr_state.av_empty.q),
// to register interface (read)
.qs (intr_state_av_empty_qs)
@@ -967,8 +967,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_full_we),
@@ -976,11 +976,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_full.de),
- .d (hw2reg.intr_state.rx_full.d ),
+ .d (hw2reg.intr_state.rx_full.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_full.q ),
+ .q (reg2hw.intr_state.rx_full.q),
// to register interface (read)
.qs (intr_state_rx_full_qs)
@@ -993,8 +993,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_av_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_av_overflow_we),
@@ -1002,11 +1002,11 @@
// from internal hardware
.de (hw2reg.intr_state.av_overflow.de),
- .d (hw2reg.intr_state.av_overflow.d ),
+ .d (hw2reg.intr_state.av_overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.av_overflow.q ),
+ .q (reg2hw.intr_state.av_overflow.q),
// to register interface (read)
.qs (intr_state_av_overflow_qs)
@@ -1019,8 +1019,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_link_in_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_link_in_err_we),
@@ -1028,11 +1028,11 @@
// from internal hardware
.de (hw2reg.intr_state.link_in_err.de),
- .d (hw2reg.intr_state.link_in_err.d ),
+ .d (hw2reg.intr_state.link_in_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.link_in_err.q ),
+ .q (reg2hw.intr_state.link_in_err.q),
// to register interface (read)
.qs (intr_state_link_in_err_qs)
@@ -1045,8 +1045,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_crc_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_crc_err_we),
@@ -1054,11 +1054,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_crc_err.de),
- .d (hw2reg.intr_state.rx_crc_err.d ),
+ .d (hw2reg.intr_state.rx_crc_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_crc_err.q ),
+ .q (reg2hw.intr_state.rx_crc_err.q),
// to register interface (read)
.qs (intr_state_rx_crc_err_qs)
@@ -1071,8 +1071,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_pid_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_pid_err_we),
@@ -1080,11 +1080,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_pid_err.de),
- .d (hw2reg.intr_state.rx_pid_err.d ),
+ .d (hw2reg.intr_state.rx_pid_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_pid_err.q ),
+ .q (reg2hw.intr_state.rx_pid_err.q),
// to register interface (read)
.qs (intr_state_rx_pid_err_qs)
@@ -1097,8 +1097,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_bitstuff_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_bitstuff_err_we),
@@ -1106,11 +1106,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_bitstuff_err.de),
- .d (hw2reg.intr_state.rx_bitstuff_err.d ),
+ .d (hw2reg.intr_state.rx_bitstuff_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_bitstuff_err.q ),
+ .q (reg2hw.intr_state.rx_bitstuff_err.q),
// to register interface (read)
.qs (intr_state_rx_bitstuff_err_qs)
@@ -1123,8 +1123,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_frame (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_frame_we),
@@ -1132,11 +1132,11 @@
// from internal hardware
.de (hw2reg.intr_state.frame.de),
- .d (hw2reg.intr_state.frame.d ),
+ .d (hw2reg.intr_state.frame.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.frame.q ),
+ .q (reg2hw.intr_state.frame.q),
// to register interface (read)
.qs (intr_state_frame_qs)
@@ -1149,8 +1149,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_connected (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_connected_we),
@@ -1158,11 +1158,11 @@
// from internal hardware
.de (hw2reg.intr_state.connected.de),
- .d (hw2reg.intr_state.connected.d ),
+ .d (hw2reg.intr_state.connected.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.connected.q ),
+ .q (reg2hw.intr_state.connected.q),
// to register interface (read)
.qs (intr_state_connected_qs)
@@ -1175,8 +1175,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_link_out_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_link_out_err_we),
@@ -1184,11 +1184,11 @@
// from internal hardware
.de (hw2reg.intr_state.link_out_err.de),
- .d (hw2reg.intr_state.link_out_err.d ),
+ .d (hw2reg.intr_state.link_out_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.link_out_err.q ),
+ .q (reg2hw.intr_state.link_out_err.q),
// to register interface (read)
.qs (intr_state_link_out_err_qs)
@@ -1203,8 +1203,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_pkt_received (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_pkt_received_we),
@@ -1212,11 +1212,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.pkt_received.q ),
+ .q (reg2hw.intr_enable.pkt_received.q),
// to register interface (read)
.qs (intr_enable_pkt_received_qs)
@@ -1229,8 +1229,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_pkt_sent (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_pkt_sent_we),
@@ -1238,11 +1238,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.pkt_sent.q ),
+ .q (reg2hw.intr_enable.pkt_sent.q),
// to register interface (read)
.qs (intr_enable_pkt_sent_qs)
@@ -1255,8 +1255,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_disconnected (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_disconnected_we),
@@ -1264,11 +1264,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.disconnected.q ),
+ .q (reg2hw.intr_enable.disconnected.q),
// to register interface (read)
.qs (intr_enable_disconnected_qs)
@@ -1281,8 +1281,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_host_lost (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_host_lost_we),
@@ -1290,11 +1290,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.host_lost.q ),
+ .q (reg2hw.intr_enable.host_lost.q),
// to register interface (read)
.qs (intr_enable_host_lost_qs)
@@ -1307,8 +1307,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_link_reset (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_link_reset_we),
@@ -1316,11 +1316,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.link_reset.q ),
+ .q (reg2hw.intr_enable.link_reset.q),
// to register interface (read)
.qs (intr_enable_link_reset_qs)
@@ -1333,8 +1333,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_link_suspend (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_link_suspend_we),
@@ -1342,11 +1342,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.link_suspend.q ),
+ .q (reg2hw.intr_enable.link_suspend.q),
// to register interface (read)
.qs (intr_enable_link_suspend_qs)
@@ -1359,8 +1359,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_link_resume (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_link_resume_we),
@@ -1368,11 +1368,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.link_resume.q ),
+ .q (reg2hw.intr_enable.link_resume.q),
// to register interface (read)
.qs (intr_enable_link_resume_qs)
@@ -1385,8 +1385,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_av_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_av_empty_we),
@@ -1394,11 +1394,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.av_empty.q ),
+ .q (reg2hw.intr_enable.av_empty.q),
// to register interface (read)
.qs (intr_enable_av_empty_qs)
@@ -1411,8 +1411,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_full_we),
@@ -1420,11 +1420,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_full.q ),
+ .q (reg2hw.intr_enable.rx_full.q),
// to register interface (read)
.qs (intr_enable_rx_full_qs)
@@ -1437,8 +1437,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_av_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_av_overflow_we),
@@ -1446,11 +1446,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.av_overflow.q ),
+ .q (reg2hw.intr_enable.av_overflow.q),
// to register interface (read)
.qs (intr_enable_av_overflow_qs)
@@ -1463,8 +1463,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_link_in_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_link_in_err_we),
@@ -1472,11 +1472,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.link_in_err.q ),
+ .q (reg2hw.intr_enable.link_in_err.q),
// to register interface (read)
.qs (intr_enable_link_in_err_qs)
@@ -1489,8 +1489,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_crc_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_crc_err_we),
@@ -1498,11 +1498,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_crc_err.q ),
+ .q (reg2hw.intr_enable.rx_crc_err.q),
// to register interface (read)
.qs (intr_enable_rx_crc_err_qs)
@@ -1515,8 +1515,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_pid_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_pid_err_we),
@@ -1524,11 +1524,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_pid_err.q ),
+ .q (reg2hw.intr_enable.rx_pid_err.q),
// to register interface (read)
.qs (intr_enable_rx_pid_err_qs)
@@ -1541,8 +1541,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_bitstuff_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_bitstuff_err_we),
@@ -1550,11 +1550,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_bitstuff_err.q ),
+ .q (reg2hw.intr_enable.rx_bitstuff_err.q),
// to register interface (read)
.qs (intr_enable_rx_bitstuff_err_qs)
@@ -1567,8 +1567,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_frame (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_frame_we),
@@ -1576,11 +1576,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.frame.q ),
+ .q (reg2hw.intr_enable.frame.q),
// to register interface (read)
.qs (intr_enable_frame_qs)
@@ -1593,8 +1593,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_connected (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_connected_we),
@@ -1602,11 +1602,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.connected.q ),
+ .q (reg2hw.intr_enable.connected.q),
// to register interface (read)
.qs (intr_enable_connected_qs)
@@ -1619,8 +1619,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_link_out_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_link_out_err_we),
@@ -1628,11 +1628,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.link_out_err.q ),
+ .q (reg2hw.intr_enable.link_out_err.q),
// to register interface (read)
.qs (intr_enable_link_out_err_qs)
@@ -1651,7 +1651,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.pkt_received.qe),
- .q (reg2hw.intr_test.pkt_received.q ),
+ .q (reg2hw.intr_test.pkt_received.q),
.qs ()
);
@@ -1666,7 +1666,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.pkt_sent.qe),
- .q (reg2hw.intr_test.pkt_sent.q ),
+ .q (reg2hw.intr_test.pkt_sent.q),
.qs ()
);
@@ -1681,7 +1681,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.disconnected.qe),
- .q (reg2hw.intr_test.disconnected.q ),
+ .q (reg2hw.intr_test.disconnected.q),
.qs ()
);
@@ -1696,7 +1696,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.host_lost.qe),
- .q (reg2hw.intr_test.host_lost.q ),
+ .q (reg2hw.intr_test.host_lost.q),
.qs ()
);
@@ -1711,7 +1711,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.link_reset.qe),
- .q (reg2hw.intr_test.link_reset.q ),
+ .q (reg2hw.intr_test.link_reset.q),
.qs ()
);
@@ -1726,7 +1726,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.link_suspend.qe),
- .q (reg2hw.intr_test.link_suspend.q ),
+ .q (reg2hw.intr_test.link_suspend.q),
.qs ()
);
@@ -1741,7 +1741,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.link_resume.qe),
- .q (reg2hw.intr_test.link_resume.q ),
+ .q (reg2hw.intr_test.link_resume.q),
.qs ()
);
@@ -1756,7 +1756,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.av_empty.qe),
- .q (reg2hw.intr_test.av_empty.q ),
+ .q (reg2hw.intr_test.av_empty.q),
.qs ()
);
@@ -1771,7 +1771,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_full.qe),
- .q (reg2hw.intr_test.rx_full.q ),
+ .q (reg2hw.intr_test.rx_full.q),
.qs ()
);
@@ -1786,7 +1786,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.av_overflow.qe),
- .q (reg2hw.intr_test.av_overflow.q ),
+ .q (reg2hw.intr_test.av_overflow.q),
.qs ()
);
@@ -1801,7 +1801,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.link_in_err.qe),
- .q (reg2hw.intr_test.link_in_err.q ),
+ .q (reg2hw.intr_test.link_in_err.q),
.qs ()
);
@@ -1816,7 +1816,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_crc_err.qe),
- .q (reg2hw.intr_test.rx_crc_err.q ),
+ .q (reg2hw.intr_test.rx_crc_err.q),
.qs ()
);
@@ -1831,7 +1831,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_pid_err.qe),
- .q (reg2hw.intr_test.rx_pid_err.q ),
+ .q (reg2hw.intr_test.rx_pid_err.q),
.qs ()
);
@@ -1846,7 +1846,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_bitstuff_err.qe),
- .q (reg2hw.intr_test.rx_bitstuff_err.q ),
+ .q (reg2hw.intr_test.rx_bitstuff_err.q),
.qs ()
);
@@ -1861,7 +1861,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.frame.qe),
- .q (reg2hw.intr_test.frame.q ),
+ .q (reg2hw.intr_test.frame.q),
.qs ()
);
@@ -1876,7 +1876,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.connected.qe),
- .q (reg2hw.intr_test.connected.q ),
+ .q (reg2hw.intr_test.connected.q),
.qs ()
);
@@ -1891,7 +1891,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.link_out_err.qe),
- .q (reg2hw.intr_test.link_out_err.q ),
+ .q (reg2hw.intr_test.link_out_err.q),
.qs ()
);
@@ -1904,8 +1904,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_usbctrl_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (usbctrl_enable_we),
@@ -1913,11 +1913,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.usbctrl.enable.q ),
+ .q (reg2hw.usbctrl.enable.q),
// to register interface (read)
.qs (usbctrl_enable_qs)
@@ -1930,8 +1930,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_usbctrl_device_address (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (usbctrl_device_address_we),
@@ -1939,11 +1939,11 @@
// from internal hardware
.de (hw2reg.usbctrl.device_address.de),
- .d (hw2reg.usbctrl.device_address.d ),
+ .d (hw2reg.usbctrl.device_address.d),
// to internal hardware
.qe (),
- .q (reg2hw.usbctrl.device_address.q ),
+ .q (reg2hw.usbctrl.device_address.q),
// to register interface (read)
.qs (usbctrl_device_address_qs)
@@ -2079,8 +2079,8 @@
.SWACCESS("WO"),
.RESVAL (5'h0)
) u_avbuffer (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (avbuffer_we),
@@ -2088,12 +2088,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.avbuffer.qe),
- .q (reg2hw.avbuffer.q ),
+ .q (reg2hw.avbuffer.q),
+ // to register interface (read)
.qs ()
);
@@ -2110,7 +2111,7 @@
.d (hw2reg.rxfifo.buffer.d),
.qre (reg2hw.rxfifo.buffer.re),
.qe (),
- .q (reg2hw.rxfifo.buffer.q ),
+ .q (reg2hw.rxfifo.buffer.q),
.qs (rxfifo_buffer_qs)
);
@@ -2125,7 +2126,7 @@
.d (hw2reg.rxfifo.size.d),
.qre (reg2hw.rxfifo.size.re),
.qe (),
- .q (reg2hw.rxfifo.size.q ),
+ .q (reg2hw.rxfifo.size.q),
.qs (rxfifo_size_qs)
);
@@ -2140,7 +2141,7 @@
.d (hw2reg.rxfifo.setup.d),
.qre (reg2hw.rxfifo.setup.re),
.qe (),
- .q (reg2hw.rxfifo.setup.q ),
+ .q (reg2hw.rxfifo.setup.q),
.qs (rxfifo_setup_qs)
);
@@ -2155,7 +2156,7 @@
.d (hw2reg.rxfifo.ep.d),
.qre (reg2hw.rxfifo.ep.re),
.qe (),
- .q (reg2hw.rxfifo.ep.q ),
+ .q (reg2hw.rxfifo.ep.q),
.qs (rxfifo_ep_qs)
);
@@ -2170,8 +2171,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_0_we),
@@ -2179,11 +2180,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[0].q ),
+ .q (reg2hw.rxenable_setup[0].q),
// to register interface (read)
.qs (rxenable_setup_setup_0_qs)
@@ -2196,8 +2197,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_1_we),
@@ -2205,11 +2206,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[1].q ),
+ .q (reg2hw.rxenable_setup[1].q),
// to register interface (read)
.qs (rxenable_setup_setup_1_qs)
@@ -2222,8 +2223,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_2_we),
@@ -2231,11 +2232,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[2].q ),
+ .q (reg2hw.rxenable_setup[2].q),
// to register interface (read)
.qs (rxenable_setup_setup_2_qs)
@@ -2248,8 +2249,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_3_we),
@@ -2257,11 +2258,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[3].q ),
+ .q (reg2hw.rxenable_setup[3].q),
// to register interface (read)
.qs (rxenable_setup_setup_3_qs)
@@ -2274,8 +2275,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_4_we),
@@ -2283,11 +2284,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[4].q ),
+ .q (reg2hw.rxenable_setup[4].q),
// to register interface (read)
.qs (rxenable_setup_setup_4_qs)
@@ -2300,8 +2301,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_5_we),
@@ -2309,11 +2310,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[5].q ),
+ .q (reg2hw.rxenable_setup[5].q),
// to register interface (read)
.qs (rxenable_setup_setup_5_qs)
@@ -2326,8 +2327,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_6_we),
@@ -2335,11 +2336,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[6].q ),
+ .q (reg2hw.rxenable_setup[6].q),
// to register interface (read)
.qs (rxenable_setup_setup_6_qs)
@@ -2352,8 +2353,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_7_we),
@@ -2361,11 +2362,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[7].q ),
+ .q (reg2hw.rxenable_setup[7].q),
// to register interface (read)
.qs (rxenable_setup_setup_7_qs)
@@ -2378,8 +2379,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_8_we),
@@ -2387,11 +2388,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[8].q ),
+ .q (reg2hw.rxenable_setup[8].q),
// to register interface (read)
.qs (rxenable_setup_setup_8_qs)
@@ -2404,8 +2405,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_9_we),
@@ -2413,11 +2414,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[9].q ),
+ .q (reg2hw.rxenable_setup[9].q),
// to register interface (read)
.qs (rxenable_setup_setup_9_qs)
@@ -2430,8 +2431,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_10_we),
@@ -2439,11 +2440,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[10].q ),
+ .q (reg2hw.rxenable_setup[10].q),
// to register interface (read)
.qs (rxenable_setup_setup_10_qs)
@@ -2456,8 +2457,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_setup_setup_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_setup_setup_11_we),
@@ -2465,11 +2466,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_setup[11].q ),
+ .q (reg2hw.rxenable_setup[11].q),
// to register interface (read)
.qs (rxenable_setup_setup_11_qs)
@@ -2487,8 +2488,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_0_we),
@@ -2496,11 +2497,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[0].q ),
+ .q (reg2hw.rxenable_out[0].q),
// to register interface (read)
.qs (rxenable_out_out_0_qs)
@@ -2513,8 +2514,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_1_we),
@@ -2522,11 +2523,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[1].q ),
+ .q (reg2hw.rxenable_out[1].q),
// to register interface (read)
.qs (rxenable_out_out_1_qs)
@@ -2539,8 +2540,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_2_we),
@@ -2548,11 +2549,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[2].q ),
+ .q (reg2hw.rxenable_out[2].q),
// to register interface (read)
.qs (rxenable_out_out_2_qs)
@@ -2565,8 +2566,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_3_we),
@@ -2574,11 +2575,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[3].q ),
+ .q (reg2hw.rxenable_out[3].q),
// to register interface (read)
.qs (rxenable_out_out_3_qs)
@@ -2591,8 +2592,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_4_we),
@@ -2600,11 +2601,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[4].q ),
+ .q (reg2hw.rxenable_out[4].q),
// to register interface (read)
.qs (rxenable_out_out_4_qs)
@@ -2617,8 +2618,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_5_we),
@@ -2626,11 +2627,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[5].q ),
+ .q (reg2hw.rxenable_out[5].q),
// to register interface (read)
.qs (rxenable_out_out_5_qs)
@@ -2643,8 +2644,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_6_we),
@@ -2652,11 +2653,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[6].q ),
+ .q (reg2hw.rxenable_out[6].q),
// to register interface (read)
.qs (rxenable_out_out_6_qs)
@@ -2669,8 +2670,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_7_we),
@@ -2678,11 +2679,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[7].q ),
+ .q (reg2hw.rxenable_out[7].q),
// to register interface (read)
.qs (rxenable_out_out_7_qs)
@@ -2695,8 +2696,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_8_we),
@@ -2704,11 +2705,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[8].q ),
+ .q (reg2hw.rxenable_out[8].q),
// to register interface (read)
.qs (rxenable_out_out_8_qs)
@@ -2721,8 +2722,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_9_we),
@@ -2730,11 +2731,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[9].q ),
+ .q (reg2hw.rxenable_out[9].q),
// to register interface (read)
.qs (rxenable_out_out_9_qs)
@@ -2747,8 +2748,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_10_we),
@@ -2756,11 +2757,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[10].q ),
+ .q (reg2hw.rxenable_out[10].q),
// to register interface (read)
.qs (rxenable_out_out_10_qs)
@@ -2773,8 +2774,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_rxenable_out_out_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rxenable_out_out_11_we),
@@ -2782,11 +2783,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rxenable_out[11].q ),
+ .q (reg2hw.rxenable_out[11].q),
// to register interface (read)
.qs (rxenable_out_out_11_qs)
@@ -2804,8 +2805,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_0_we),
@@ -2813,7 +2814,7 @@
// from internal hardware
.de (hw2reg.in_sent[0].de),
- .d (hw2reg.in_sent[0].d ),
+ .d (hw2reg.in_sent[0].d),
// to internal hardware
.qe (),
@@ -2830,8 +2831,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_1_we),
@@ -2839,7 +2840,7 @@
// from internal hardware
.de (hw2reg.in_sent[1].de),
- .d (hw2reg.in_sent[1].d ),
+ .d (hw2reg.in_sent[1].d),
// to internal hardware
.qe (),
@@ -2856,8 +2857,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_2_we),
@@ -2865,7 +2866,7 @@
// from internal hardware
.de (hw2reg.in_sent[2].de),
- .d (hw2reg.in_sent[2].d ),
+ .d (hw2reg.in_sent[2].d),
// to internal hardware
.qe (),
@@ -2882,8 +2883,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_3_we),
@@ -2891,7 +2892,7 @@
// from internal hardware
.de (hw2reg.in_sent[3].de),
- .d (hw2reg.in_sent[3].d ),
+ .d (hw2reg.in_sent[3].d),
// to internal hardware
.qe (),
@@ -2908,8 +2909,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_4_we),
@@ -2917,7 +2918,7 @@
// from internal hardware
.de (hw2reg.in_sent[4].de),
- .d (hw2reg.in_sent[4].d ),
+ .d (hw2reg.in_sent[4].d),
// to internal hardware
.qe (),
@@ -2934,8 +2935,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_5_we),
@@ -2943,7 +2944,7 @@
// from internal hardware
.de (hw2reg.in_sent[5].de),
- .d (hw2reg.in_sent[5].d ),
+ .d (hw2reg.in_sent[5].d),
// to internal hardware
.qe (),
@@ -2960,8 +2961,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_6_we),
@@ -2969,7 +2970,7 @@
// from internal hardware
.de (hw2reg.in_sent[6].de),
- .d (hw2reg.in_sent[6].d ),
+ .d (hw2reg.in_sent[6].d),
// to internal hardware
.qe (),
@@ -2986,8 +2987,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_7_we),
@@ -2995,7 +2996,7 @@
// from internal hardware
.de (hw2reg.in_sent[7].de),
- .d (hw2reg.in_sent[7].d ),
+ .d (hw2reg.in_sent[7].d),
// to internal hardware
.qe (),
@@ -3012,8 +3013,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_8_we),
@@ -3021,7 +3022,7 @@
// from internal hardware
.de (hw2reg.in_sent[8].de),
- .d (hw2reg.in_sent[8].d ),
+ .d (hw2reg.in_sent[8].d),
// to internal hardware
.qe (),
@@ -3038,8 +3039,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_9_we),
@@ -3047,7 +3048,7 @@
// from internal hardware
.de (hw2reg.in_sent[9].de),
- .d (hw2reg.in_sent[9].d ),
+ .d (hw2reg.in_sent[9].d),
// to internal hardware
.qe (),
@@ -3064,8 +3065,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_10_we),
@@ -3073,7 +3074,7 @@
// from internal hardware
.de (hw2reg.in_sent[10].de),
- .d (hw2reg.in_sent[10].d ),
+ .d (hw2reg.in_sent[10].d),
// to internal hardware
.qe (),
@@ -3090,8 +3091,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_in_sent_sent_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (in_sent_sent_11_we),
@@ -3099,7 +3100,7 @@
// from internal hardware
.de (hw2reg.in_sent[11].de),
- .d (hw2reg.in_sent[11].d ),
+ .d (hw2reg.in_sent[11].d),
// to internal hardware
.qe (),
@@ -3121,8 +3122,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_0_we),
@@ -3130,11 +3131,11 @@
// from internal hardware
.de (hw2reg.stall[0].de),
- .d (hw2reg.stall[0].d ),
+ .d (hw2reg.stall[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[0].q ),
+ .q (reg2hw.stall[0].q),
// to register interface (read)
.qs (stall_stall_0_qs)
@@ -3147,8 +3148,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_1_we),
@@ -3156,11 +3157,11 @@
// from internal hardware
.de (hw2reg.stall[1].de),
- .d (hw2reg.stall[1].d ),
+ .d (hw2reg.stall[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[1].q ),
+ .q (reg2hw.stall[1].q),
// to register interface (read)
.qs (stall_stall_1_qs)
@@ -3173,8 +3174,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_2_we),
@@ -3182,11 +3183,11 @@
// from internal hardware
.de (hw2reg.stall[2].de),
- .d (hw2reg.stall[2].d ),
+ .d (hw2reg.stall[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[2].q ),
+ .q (reg2hw.stall[2].q),
// to register interface (read)
.qs (stall_stall_2_qs)
@@ -3199,8 +3200,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_3_we),
@@ -3208,11 +3209,11 @@
// from internal hardware
.de (hw2reg.stall[3].de),
- .d (hw2reg.stall[3].d ),
+ .d (hw2reg.stall[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[3].q ),
+ .q (reg2hw.stall[3].q),
// to register interface (read)
.qs (stall_stall_3_qs)
@@ -3225,8 +3226,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_4_we),
@@ -3234,11 +3235,11 @@
// from internal hardware
.de (hw2reg.stall[4].de),
- .d (hw2reg.stall[4].d ),
+ .d (hw2reg.stall[4].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[4].q ),
+ .q (reg2hw.stall[4].q),
// to register interface (read)
.qs (stall_stall_4_qs)
@@ -3251,8 +3252,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_5_we),
@@ -3260,11 +3261,11 @@
// from internal hardware
.de (hw2reg.stall[5].de),
- .d (hw2reg.stall[5].d ),
+ .d (hw2reg.stall[5].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[5].q ),
+ .q (reg2hw.stall[5].q),
// to register interface (read)
.qs (stall_stall_5_qs)
@@ -3277,8 +3278,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_6_we),
@@ -3286,11 +3287,11 @@
// from internal hardware
.de (hw2reg.stall[6].de),
- .d (hw2reg.stall[6].d ),
+ .d (hw2reg.stall[6].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[6].q ),
+ .q (reg2hw.stall[6].q),
// to register interface (read)
.qs (stall_stall_6_qs)
@@ -3303,8 +3304,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_7_we),
@@ -3312,11 +3313,11 @@
// from internal hardware
.de (hw2reg.stall[7].de),
- .d (hw2reg.stall[7].d ),
+ .d (hw2reg.stall[7].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[7].q ),
+ .q (reg2hw.stall[7].q),
// to register interface (read)
.qs (stall_stall_7_qs)
@@ -3329,8 +3330,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_8_we),
@@ -3338,11 +3339,11 @@
// from internal hardware
.de (hw2reg.stall[8].de),
- .d (hw2reg.stall[8].d ),
+ .d (hw2reg.stall[8].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[8].q ),
+ .q (reg2hw.stall[8].q),
// to register interface (read)
.qs (stall_stall_8_qs)
@@ -3355,8 +3356,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_9_we),
@@ -3364,11 +3365,11 @@
// from internal hardware
.de (hw2reg.stall[9].de),
- .d (hw2reg.stall[9].d ),
+ .d (hw2reg.stall[9].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[9].q ),
+ .q (reg2hw.stall[9].q),
// to register interface (read)
.qs (stall_stall_9_qs)
@@ -3381,8 +3382,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_10_we),
@@ -3390,11 +3391,11 @@
// from internal hardware
.de (hw2reg.stall[10].de),
- .d (hw2reg.stall[10].d ),
+ .d (hw2reg.stall[10].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[10].q ),
+ .q (reg2hw.stall[10].q),
// to register interface (read)
.qs (stall_stall_10_qs)
@@ -3407,8 +3408,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_stall_stall_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (stall_stall_11_we),
@@ -3416,11 +3417,11 @@
// from internal hardware
.de (hw2reg.stall[11].de),
- .d (hw2reg.stall[11].d ),
+ .d (hw2reg.stall[11].d),
// to internal hardware
.qe (),
- .q (reg2hw.stall[11].q ),
+ .q (reg2hw.stall[11].q),
// to register interface (read)
.qs (stall_stall_11_qs)
@@ -3438,8 +3439,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_0_buffer_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_0_buffer_0_we),
@@ -3447,11 +3448,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[0].buffer.q ),
+ .q (reg2hw.configin[0].buffer.q),
// to register interface (read)
.qs (configin_0_buffer_0_qs)
@@ -3464,8 +3465,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_0_size_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_0_size_0_we),
@@ -3473,11 +3474,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[0].size.q ),
+ .q (reg2hw.configin[0].size.q),
// to register interface (read)
.qs (configin_0_size_0_qs)
@@ -3490,8 +3491,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_0_pend_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_0_pend_0_we),
@@ -3499,11 +3500,11 @@
// from internal hardware
.de (hw2reg.configin[0].pend.de),
- .d (hw2reg.configin[0].pend.d ),
+ .d (hw2reg.configin[0].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[0].pend.q ),
+ .q (reg2hw.configin[0].pend.q),
// to register interface (read)
.qs (configin_0_pend_0_qs)
@@ -3516,8 +3517,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_0_rdy_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_0_rdy_0_we),
@@ -3525,11 +3526,11 @@
// from internal hardware
.de (hw2reg.configin[0].rdy.de),
- .d (hw2reg.configin[0].rdy.d ),
+ .d (hw2reg.configin[0].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[0].rdy.q ),
+ .q (reg2hw.configin[0].rdy.q),
// to register interface (read)
.qs (configin_0_rdy_0_qs)
@@ -3545,8 +3546,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_1_buffer_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_1_buffer_1_we),
@@ -3554,11 +3555,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[1].buffer.q ),
+ .q (reg2hw.configin[1].buffer.q),
// to register interface (read)
.qs (configin_1_buffer_1_qs)
@@ -3571,8 +3572,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_1_size_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_1_size_1_we),
@@ -3580,11 +3581,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[1].size.q ),
+ .q (reg2hw.configin[1].size.q),
// to register interface (read)
.qs (configin_1_size_1_qs)
@@ -3597,8 +3598,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_1_pend_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_1_pend_1_we),
@@ -3606,11 +3607,11 @@
// from internal hardware
.de (hw2reg.configin[1].pend.de),
- .d (hw2reg.configin[1].pend.d ),
+ .d (hw2reg.configin[1].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[1].pend.q ),
+ .q (reg2hw.configin[1].pend.q),
// to register interface (read)
.qs (configin_1_pend_1_qs)
@@ -3623,8 +3624,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_1_rdy_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_1_rdy_1_we),
@@ -3632,11 +3633,11 @@
// from internal hardware
.de (hw2reg.configin[1].rdy.de),
- .d (hw2reg.configin[1].rdy.d ),
+ .d (hw2reg.configin[1].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[1].rdy.q ),
+ .q (reg2hw.configin[1].rdy.q),
// to register interface (read)
.qs (configin_1_rdy_1_qs)
@@ -3652,8 +3653,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_2_buffer_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_2_buffer_2_we),
@@ -3661,11 +3662,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[2].buffer.q ),
+ .q (reg2hw.configin[2].buffer.q),
// to register interface (read)
.qs (configin_2_buffer_2_qs)
@@ -3678,8 +3679,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_2_size_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_2_size_2_we),
@@ -3687,11 +3688,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[2].size.q ),
+ .q (reg2hw.configin[2].size.q),
// to register interface (read)
.qs (configin_2_size_2_qs)
@@ -3704,8 +3705,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_2_pend_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_2_pend_2_we),
@@ -3713,11 +3714,11 @@
// from internal hardware
.de (hw2reg.configin[2].pend.de),
- .d (hw2reg.configin[2].pend.d ),
+ .d (hw2reg.configin[2].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[2].pend.q ),
+ .q (reg2hw.configin[2].pend.q),
// to register interface (read)
.qs (configin_2_pend_2_qs)
@@ -3730,8 +3731,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_2_rdy_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_2_rdy_2_we),
@@ -3739,11 +3740,11 @@
// from internal hardware
.de (hw2reg.configin[2].rdy.de),
- .d (hw2reg.configin[2].rdy.d ),
+ .d (hw2reg.configin[2].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[2].rdy.q ),
+ .q (reg2hw.configin[2].rdy.q),
// to register interface (read)
.qs (configin_2_rdy_2_qs)
@@ -3759,8 +3760,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_3_buffer_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_3_buffer_3_we),
@@ -3768,11 +3769,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[3].buffer.q ),
+ .q (reg2hw.configin[3].buffer.q),
// to register interface (read)
.qs (configin_3_buffer_3_qs)
@@ -3785,8 +3786,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_3_size_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_3_size_3_we),
@@ -3794,11 +3795,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[3].size.q ),
+ .q (reg2hw.configin[3].size.q),
// to register interface (read)
.qs (configin_3_size_3_qs)
@@ -3811,8 +3812,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_3_pend_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_3_pend_3_we),
@@ -3820,11 +3821,11 @@
// from internal hardware
.de (hw2reg.configin[3].pend.de),
- .d (hw2reg.configin[3].pend.d ),
+ .d (hw2reg.configin[3].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[3].pend.q ),
+ .q (reg2hw.configin[3].pend.q),
// to register interface (read)
.qs (configin_3_pend_3_qs)
@@ -3837,8 +3838,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_3_rdy_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_3_rdy_3_we),
@@ -3846,11 +3847,11 @@
// from internal hardware
.de (hw2reg.configin[3].rdy.de),
- .d (hw2reg.configin[3].rdy.d ),
+ .d (hw2reg.configin[3].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[3].rdy.q ),
+ .q (reg2hw.configin[3].rdy.q),
// to register interface (read)
.qs (configin_3_rdy_3_qs)
@@ -3866,8 +3867,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_4_buffer_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_4_buffer_4_we),
@@ -3875,11 +3876,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[4].buffer.q ),
+ .q (reg2hw.configin[4].buffer.q),
// to register interface (read)
.qs (configin_4_buffer_4_qs)
@@ -3892,8 +3893,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_4_size_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_4_size_4_we),
@@ -3901,11 +3902,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[4].size.q ),
+ .q (reg2hw.configin[4].size.q),
// to register interface (read)
.qs (configin_4_size_4_qs)
@@ -3918,8 +3919,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_4_pend_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_4_pend_4_we),
@@ -3927,11 +3928,11 @@
// from internal hardware
.de (hw2reg.configin[4].pend.de),
- .d (hw2reg.configin[4].pend.d ),
+ .d (hw2reg.configin[4].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[4].pend.q ),
+ .q (reg2hw.configin[4].pend.q),
// to register interface (read)
.qs (configin_4_pend_4_qs)
@@ -3944,8 +3945,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_4_rdy_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_4_rdy_4_we),
@@ -3953,11 +3954,11 @@
// from internal hardware
.de (hw2reg.configin[4].rdy.de),
- .d (hw2reg.configin[4].rdy.d ),
+ .d (hw2reg.configin[4].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[4].rdy.q ),
+ .q (reg2hw.configin[4].rdy.q),
// to register interface (read)
.qs (configin_4_rdy_4_qs)
@@ -3973,8 +3974,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_5_buffer_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_5_buffer_5_we),
@@ -3982,11 +3983,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[5].buffer.q ),
+ .q (reg2hw.configin[5].buffer.q),
// to register interface (read)
.qs (configin_5_buffer_5_qs)
@@ -3999,8 +4000,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_5_size_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_5_size_5_we),
@@ -4008,11 +4009,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[5].size.q ),
+ .q (reg2hw.configin[5].size.q),
// to register interface (read)
.qs (configin_5_size_5_qs)
@@ -4025,8 +4026,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_5_pend_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_5_pend_5_we),
@@ -4034,11 +4035,11 @@
// from internal hardware
.de (hw2reg.configin[5].pend.de),
- .d (hw2reg.configin[5].pend.d ),
+ .d (hw2reg.configin[5].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[5].pend.q ),
+ .q (reg2hw.configin[5].pend.q),
// to register interface (read)
.qs (configin_5_pend_5_qs)
@@ -4051,8 +4052,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_5_rdy_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_5_rdy_5_we),
@@ -4060,11 +4061,11 @@
// from internal hardware
.de (hw2reg.configin[5].rdy.de),
- .d (hw2reg.configin[5].rdy.d ),
+ .d (hw2reg.configin[5].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[5].rdy.q ),
+ .q (reg2hw.configin[5].rdy.q),
// to register interface (read)
.qs (configin_5_rdy_5_qs)
@@ -4080,8 +4081,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_6_buffer_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_6_buffer_6_we),
@@ -4089,11 +4090,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[6].buffer.q ),
+ .q (reg2hw.configin[6].buffer.q),
// to register interface (read)
.qs (configin_6_buffer_6_qs)
@@ -4106,8 +4107,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_6_size_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_6_size_6_we),
@@ -4115,11 +4116,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[6].size.q ),
+ .q (reg2hw.configin[6].size.q),
// to register interface (read)
.qs (configin_6_size_6_qs)
@@ -4132,8 +4133,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_6_pend_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_6_pend_6_we),
@@ -4141,11 +4142,11 @@
// from internal hardware
.de (hw2reg.configin[6].pend.de),
- .d (hw2reg.configin[6].pend.d ),
+ .d (hw2reg.configin[6].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[6].pend.q ),
+ .q (reg2hw.configin[6].pend.q),
// to register interface (read)
.qs (configin_6_pend_6_qs)
@@ -4158,8 +4159,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_6_rdy_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_6_rdy_6_we),
@@ -4167,11 +4168,11 @@
// from internal hardware
.de (hw2reg.configin[6].rdy.de),
- .d (hw2reg.configin[6].rdy.d ),
+ .d (hw2reg.configin[6].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[6].rdy.q ),
+ .q (reg2hw.configin[6].rdy.q),
// to register interface (read)
.qs (configin_6_rdy_6_qs)
@@ -4187,8 +4188,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_7_buffer_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_7_buffer_7_we),
@@ -4196,11 +4197,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[7].buffer.q ),
+ .q (reg2hw.configin[7].buffer.q),
// to register interface (read)
.qs (configin_7_buffer_7_qs)
@@ -4213,8 +4214,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_7_size_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_7_size_7_we),
@@ -4222,11 +4223,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[7].size.q ),
+ .q (reg2hw.configin[7].size.q),
// to register interface (read)
.qs (configin_7_size_7_qs)
@@ -4239,8 +4240,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_7_pend_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_7_pend_7_we),
@@ -4248,11 +4249,11 @@
// from internal hardware
.de (hw2reg.configin[7].pend.de),
- .d (hw2reg.configin[7].pend.d ),
+ .d (hw2reg.configin[7].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[7].pend.q ),
+ .q (reg2hw.configin[7].pend.q),
// to register interface (read)
.qs (configin_7_pend_7_qs)
@@ -4265,8 +4266,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_7_rdy_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_7_rdy_7_we),
@@ -4274,11 +4275,11 @@
// from internal hardware
.de (hw2reg.configin[7].rdy.de),
- .d (hw2reg.configin[7].rdy.d ),
+ .d (hw2reg.configin[7].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[7].rdy.q ),
+ .q (reg2hw.configin[7].rdy.q),
// to register interface (read)
.qs (configin_7_rdy_7_qs)
@@ -4294,8 +4295,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_8_buffer_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_8_buffer_8_we),
@@ -4303,11 +4304,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[8].buffer.q ),
+ .q (reg2hw.configin[8].buffer.q),
// to register interface (read)
.qs (configin_8_buffer_8_qs)
@@ -4320,8 +4321,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_8_size_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_8_size_8_we),
@@ -4329,11 +4330,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[8].size.q ),
+ .q (reg2hw.configin[8].size.q),
// to register interface (read)
.qs (configin_8_size_8_qs)
@@ -4346,8 +4347,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_8_pend_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_8_pend_8_we),
@@ -4355,11 +4356,11 @@
// from internal hardware
.de (hw2reg.configin[8].pend.de),
- .d (hw2reg.configin[8].pend.d ),
+ .d (hw2reg.configin[8].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[8].pend.q ),
+ .q (reg2hw.configin[8].pend.q),
// to register interface (read)
.qs (configin_8_pend_8_qs)
@@ -4372,8 +4373,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_8_rdy_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_8_rdy_8_we),
@@ -4381,11 +4382,11 @@
// from internal hardware
.de (hw2reg.configin[8].rdy.de),
- .d (hw2reg.configin[8].rdy.d ),
+ .d (hw2reg.configin[8].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[8].rdy.q ),
+ .q (reg2hw.configin[8].rdy.q),
// to register interface (read)
.qs (configin_8_rdy_8_qs)
@@ -4401,8 +4402,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_9_buffer_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_9_buffer_9_we),
@@ -4410,11 +4411,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[9].buffer.q ),
+ .q (reg2hw.configin[9].buffer.q),
// to register interface (read)
.qs (configin_9_buffer_9_qs)
@@ -4427,8 +4428,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_9_size_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_9_size_9_we),
@@ -4436,11 +4437,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[9].size.q ),
+ .q (reg2hw.configin[9].size.q),
// to register interface (read)
.qs (configin_9_size_9_qs)
@@ -4453,8 +4454,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_9_pend_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_9_pend_9_we),
@@ -4462,11 +4463,11 @@
// from internal hardware
.de (hw2reg.configin[9].pend.de),
- .d (hw2reg.configin[9].pend.d ),
+ .d (hw2reg.configin[9].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[9].pend.q ),
+ .q (reg2hw.configin[9].pend.q),
// to register interface (read)
.qs (configin_9_pend_9_qs)
@@ -4479,8 +4480,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_9_rdy_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_9_rdy_9_we),
@@ -4488,11 +4489,11 @@
// from internal hardware
.de (hw2reg.configin[9].rdy.de),
- .d (hw2reg.configin[9].rdy.d ),
+ .d (hw2reg.configin[9].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[9].rdy.q ),
+ .q (reg2hw.configin[9].rdy.q),
// to register interface (read)
.qs (configin_9_rdy_9_qs)
@@ -4508,8 +4509,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_10_buffer_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_10_buffer_10_we),
@@ -4517,11 +4518,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[10].buffer.q ),
+ .q (reg2hw.configin[10].buffer.q),
// to register interface (read)
.qs (configin_10_buffer_10_qs)
@@ -4534,8 +4535,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_10_size_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_10_size_10_we),
@@ -4543,11 +4544,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[10].size.q ),
+ .q (reg2hw.configin[10].size.q),
// to register interface (read)
.qs (configin_10_size_10_qs)
@@ -4560,8 +4561,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_10_pend_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_10_pend_10_we),
@@ -4569,11 +4570,11 @@
// from internal hardware
.de (hw2reg.configin[10].pend.de),
- .d (hw2reg.configin[10].pend.d ),
+ .d (hw2reg.configin[10].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[10].pend.q ),
+ .q (reg2hw.configin[10].pend.q),
// to register interface (read)
.qs (configin_10_pend_10_qs)
@@ -4586,8 +4587,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_10_rdy_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_10_rdy_10_we),
@@ -4595,11 +4596,11 @@
// from internal hardware
.de (hw2reg.configin[10].rdy.de),
- .d (hw2reg.configin[10].rdy.d ),
+ .d (hw2reg.configin[10].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[10].rdy.q ),
+ .q (reg2hw.configin[10].rdy.q),
// to register interface (read)
.qs (configin_10_rdy_10_qs)
@@ -4615,8 +4616,8 @@
.SWACCESS("RW"),
.RESVAL (5'h0)
) u_configin_11_buffer_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_11_buffer_11_we),
@@ -4624,11 +4625,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[11].buffer.q ),
+ .q (reg2hw.configin[11].buffer.q),
// to register interface (read)
.qs (configin_11_buffer_11_qs)
@@ -4641,8 +4642,8 @@
.SWACCESS("RW"),
.RESVAL (7'h0)
) u_configin_11_size_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_11_size_11_we),
@@ -4650,11 +4651,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.configin[11].size.q ),
+ .q (reg2hw.configin[11].size.q),
// to register interface (read)
.qs (configin_11_size_11_qs)
@@ -4667,8 +4668,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_configin_11_pend_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_11_pend_11_we),
@@ -4676,11 +4677,11 @@
// from internal hardware
.de (hw2reg.configin[11].pend.de),
- .d (hw2reg.configin[11].pend.d ),
+ .d (hw2reg.configin[11].pend.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[11].pend.q ),
+ .q (reg2hw.configin[11].pend.q),
// to register interface (read)
.qs (configin_11_pend_11_qs)
@@ -4693,8 +4694,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_configin_11_rdy_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (configin_11_rdy_11_we),
@@ -4702,11 +4703,11 @@
// from internal hardware
.de (hw2reg.configin[11].rdy.de),
- .d (hw2reg.configin[11].rdy.d ),
+ .d (hw2reg.configin[11].rdy.d),
// to internal hardware
.qe (),
- .q (reg2hw.configin[11].rdy.q ),
+ .q (reg2hw.configin[11].rdy.q),
// to register interface (read)
.qs (configin_11_rdy_11_qs)
@@ -4724,8 +4725,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_0_we),
@@ -4733,11 +4734,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[0].q ),
+ .q (reg2hw.iso[0].q),
// to register interface (read)
.qs (iso_iso_0_qs)
@@ -4750,8 +4751,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_1_we),
@@ -4759,11 +4760,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[1].q ),
+ .q (reg2hw.iso[1].q),
// to register interface (read)
.qs (iso_iso_1_qs)
@@ -4776,8 +4777,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_2_we),
@@ -4785,11 +4786,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[2].q ),
+ .q (reg2hw.iso[2].q),
// to register interface (read)
.qs (iso_iso_2_qs)
@@ -4802,8 +4803,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_3_we),
@@ -4811,11 +4812,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[3].q ),
+ .q (reg2hw.iso[3].q),
// to register interface (read)
.qs (iso_iso_3_qs)
@@ -4828,8 +4829,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_4_we),
@@ -4837,11 +4838,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[4].q ),
+ .q (reg2hw.iso[4].q),
// to register interface (read)
.qs (iso_iso_4_qs)
@@ -4854,8 +4855,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_5_we),
@@ -4863,11 +4864,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[5].q ),
+ .q (reg2hw.iso[5].q),
// to register interface (read)
.qs (iso_iso_5_qs)
@@ -4880,8 +4881,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_6_we),
@@ -4889,11 +4890,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[6].q ),
+ .q (reg2hw.iso[6].q),
// to register interface (read)
.qs (iso_iso_6_qs)
@@ -4906,8 +4907,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_7_we),
@@ -4915,11 +4916,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[7].q ),
+ .q (reg2hw.iso[7].q),
// to register interface (read)
.qs (iso_iso_7_qs)
@@ -4932,8 +4933,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_8_we),
@@ -4941,11 +4942,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[8].q ),
+ .q (reg2hw.iso[8].q),
// to register interface (read)
.qs (iso_iso_8_qs)
@@ -4958,8 +4959,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_9_we),
@@ -4967,11 +4968,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[9].q ),
+ .q (reg2hw.iso[9].q),
// to register interface (read)
.qs (iso_iso_9_qs)
@@ -4984,8 +4985,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_10_we),
@@ -4993,11 +4994,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[10].q ),
+ .q (reg2hw.iso[10].q),
// to register interface (read)
.qs (iso_iso_10_qs)
@@ -5010,8 +5011,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_iso_iso_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (iso_iso_11_we),
@@ -5019,11 +5020,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.iso[11].q ),
+ .q (reg2hw.iso[11].q),
// to register interface (read)
.qs (iso_iso_11_qs)
@@ -5041,8 +5042,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_0_we),
@@ -5050,12 +5051,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[0].qe),
- .q (reg2hw.data_toggle_clear[0].q ),
+ .q (reg2hw.data_toggle_clear[0].q),
+ // to register interface (read)
.qs ()
);
@@ -5066,8 +5068,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_1_we),
@@ -5075,12 +5077,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[1].qe),
- .q (reg2hw.data_toggle_clear[1].q ),
+ .q (reg2hw.data_toggle_clear[1].q),
+ // to register interface (read)
.qs ()
);
@@ -5091,8 +5094,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_2_we),
@@ -5100,12 +5103,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[2].qe),
- .q (reg2hw.data_toggle_clear[2].q ),
+ .q (reg2hw.data_toggle_clear[2].q),
+ // to register interface (read)
.qs ()
);
@@ -5116,8 +5120,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_3_we),
@@ -5125,12 +5129,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[3].qe),
- .q (reg2hw.data_toggle_clear[3].q ),
+ .q (reg2hw.data_toggle_clear[3].q),
+ // to register interface (read)
.qs ()
);
@@ -5141,8 +5146,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_4_we),
@@ -5150,12 +5155,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[4].qe),
- .q (reg2hw.data_toggle_clear[4].q ),
+ .q (reg2hw.data_toggle_clear[4].q),
+ // to register interface (read)
.qs ()
);
@@ -5166,8 +5172,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_5_we),
@@ -5175,12 +5181,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[5].qe),
- .q (reg2hw.data_toggle_clear[5].q ),
+ .q (reg2hw.data_toggle_clear[5].q),
+ // to register interface (read)
.qs ()
);
@@ -5191,8 +5198,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_6_we),
@@ -5200,12 +5207,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[6].qe),
- .q (reg2hw.data_toggle_clear[6].q ),
+ .q (reg2hw.data_toggle_clear[6].q),
+ // to register interface (read)
.qs ()
);
@@ -5216,8 +5224,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_7_we),
@@ -5225,12 +5233,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[7].qe),
- .q (reg2hw.data_toggle_clear[7].q ),
+ .q (reg2hw.data_toggle_clear[7].q),
+ // to register interface (read)
.qs ()
);
@@ -5241,8 +5250,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_8_we),
@@ -5250,12 +5259,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[8].qe),
- .q (reg2hw.data_toggle_clear[8].q ),
+ .q (reg2hw.data_toggle_clear[8].q),
+ // to register interface (read)
.qs ()
);
@@ -5266,8 +5276,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_9_we),
@@ -5275,12 +5285,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[9].qe),
- .q (reg2hw.data_toggle_clear[9].q ),
+ .q (reg2hw.data_toggle_clear[9].q),
+ // to register interface (read)
.qs ()
);
@@ -5291,8 +5302,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_10_we),
@@ -5300,12 +5311,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[10].qe),
- .q (reg2hw.data_toggle_clear[10].q ),
+ .q (reg2hw.data_toggle_clear[10].q),
+ // to register interface (read)
.qs ()
);
@@ -5316,8 +5328,8 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_data_toggle_clear_clear_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (data_toggle_clear_clear_11_we),
@@ -5325,12 +5337,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.data_toggle_clear[11].qe),
- .q (reg2hw.data_toggle_clear[11].q ),
+ .q (reg2hw.data_toggle_clear[11].q),
+ // to register interface (read)
.qs ()
);
@@ -5496,8 +5509,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_dp_o (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_dp_o_we),
@@ -5505,11 +5518,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.dp_o.q ),
+ .q (reg2hw.phy_pins_drive.dp_o.q),
// to register interface (read)
.qs (phy_pins_drive_dp_o_qs)
@@ -5522,8 +5535,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_dn_o (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_dn_o_we),
@@ -5531,11 +5544,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.dn_o.q ),
+ .q (reg2hw.phy_pins_drive.dn_o.q),
// to register interface (read)
.qs (phy_pins_drive_dn_o_qs)
@@ -5548,8 +5561,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_d_o (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_d_o_we),
@@ -5557,11 +5570,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.d_o.q ),
+ .q (reg2hw.phy_pins_drive.d_o.q),
// to register interface (read)
.qs (phy_pins_drive_d_o_qs)
@@ -5574,8 +5587,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_se0_o (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_se0_o_we),
@@ -5583,11 +5596,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.se0_o.q ),
+ .q (reg2hw.phy_pins_drive.se0_o.q),
// to register interface (read)
.qs (phy_pins_drive_se0_o_qs)
@@ -5600,8 +5613,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_oe_o (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_oe_o_we),
@@ -5609,11 +5622,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.oe_o.q ),
+ .q (reg2hw.phy_pins_drive.oe_o.q),
// to register interface (read)
.qs (phy_pins_drive_oe_o_qs)
@@ -5626,8 +5639,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_tx_mode_se_o (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_tx_mode_se_o_we),
@@ -5635,11 +5648,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.tx_mode_se_o.q ),
+ .q (reg2hw.phy_pins_drive.tx_mode_se_o.q),
// to register interface (read)
.qs (phy_pins_drive_tx_mode_se_o_qs)
@@ -5652,8 +5665,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_dp_pullup_en_o (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_dp_pullup_en_o_we),
@@ -5661,11 +5674,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.dp_pullup_en_o.q ),
+ .q (reg2hw.phy_pins_drive.dp_pullup_en_o.q),
// to register interface (read)
.qs (phy_pins_drive_dp_pullup_en_o_qs)
@@ -5678,8 +5691,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_dn_pullup_en_o (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_dn_pullup_en_o_we),
@@ -5687,11 +5700,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.dn_pullup_en_o.q ),
+ .q (reg2hw.phy_pins_drive.dn_pullup_en_o.q),
// to register interface (read)
.qs (phy_pins_drive_dn_pullup_en_o_qs)
@@ -5704,8 +5717,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_suspend_o (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_suspend_o_we),
@@ -5713,11 +5726,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.suspend_o.q ),
+ .q (reg2hw.phy_pins_drive.suspend_o.q),
// to register interface (read)
.qs (phy_pins_drive_suspend_o_qs)
@@ -5730,8 +5743,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_pins_drive_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_pins_drive_en_we),
@@ -5739,11 +5752,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_pins_drive.en.q ),
+ .q (reg2hw.phy_pins_drive.en.q),
// to register interface (read)
.qs (phy_pins_drive_en_qs)
@@ -5758,8 +5771,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_config_rx_differential_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_config_rx_differential_mode_we),
@@ -5767,11 +5780,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_config.rx_differential_mode.q ),
+ .q (reg2hw.phy_config.rx_differential_mode.q),
// to register interface (read)
.qs (phy_config_rx_differential_mode_qs)
@@ -5784,8 +5797,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_config_tx_differential_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_config_tx_differential_mode_we),
@@ -5793,11 +5806,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_config.tx_differential_mode.q ),
+ .q (reg2hw.phy_config.tx_differential_mode.q),
// to register interface (read)
.qs (phy_config_tx_differential_mode_qs)
@@ -5810,8 +5823,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_phy_config_eop_single_bit (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_config_eop_single_bit_we),
@@ -5819,11 +5832,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_config.eop_single_bit.q ),
+ .q (reg2hw.phy_config.eop_single_bit.q),
// to register interface (read)
.qs (phy_config_eop_single_bit_qs)
@@ -5836,8 +5849,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_config_override_pwr_sense_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_config_override_pwr_sense_en_we),
@@ -5845,11 +5858,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_config.override_pwr_sense_en.q ),
+ .q (reg2hw.phy_config.override_pwr_sense_en.q),
// to register interface (read)
.qs (phy_config_override_pwr_sense_en_qs)
@@ -5862,8 +5875,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_config_override_pwr_sense_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_config_override_pwr_sense_val_we),
@@ -5871,11 +5884,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_config.override_pwr_sense_val.q ),
+ .q (reg2hw.phy_config.override_pwr_sense_val.q),
// to register interface (read)
.qs (phy_config_override_pwr_sense_val_qs)
@@ -5888,8 +5901,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_config_pinflip (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_config_pinflip_we),
@@ -5897,11 +5910,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_config.pinflip.q ),
+ .q (reg2hw.phy_config.pinflip.q),
// to register interface (read)
.qs (phy_config_pinflip_qs)
@@ -5914,8 +5927,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_config_usb_ref_disable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_config_usb_ref_disable_we),
@@ -5923,11 +5936,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_config.usb_ref_disable.q ),
+ .q (reg2hw.phy_config.usb_ref_disable.q),
// to register interface (read)
.qs (phy_config_usb_ref_disable_qs)
@@ -5940,8 +5953,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_config_tx_osc_test_mode (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_config_tx_osc_test_mode_we),
@@ -5949,11 +5962,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_config.tx_osc_test_mode.q ),
+ .q (reg2hw.phy_config.tx_osc_test_mode.q),
// to register interface (read)
.qs (phy_config_tx_osc_test_mode_qs)
@@ -5968,8 +5981,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wake_config_wake_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wake_config_wake_en_we),
@@ -5977,11 +5990,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wake_config.wake_en.q ),
+ .q (reg2hw.wake_config.wake_en.q),
// to register interface (read)
.qs (wake_config_wake_en_qs)
@@ -5994,8 +6007,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wake_config_wake_ack (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wake_config_wake_ack_we),
@@ -6003,11 +6016,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wake_config.wake_ack.q ),
+ .q (reg2hw.wake_config.wake_ack.q),
// to register interface (read)
.qs (wake_config_wake_ack_qs)
@@ -6021,15 +6034,16 @@
.SWACCESS("RO"),
.RESVAL (3'h0)
) u_wake_debug (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.wake_debug.de),
- .d (hw2reg.wake_debug.d ),
+ .d (hw2reg.wake_debug.d),
// to internal hardware
.qe (),
diff --git a/hw/ip/usbuart/rtl/usbuart_reg_top.sv b/hw/ip/usbuart/rtl/usbuart_reg_top.sv
index f23e59e..f344569 100644
--- a/hw/ip/usbuart/rtl/usbuart_reg_top.sv
+++ b/hw/ip/usbuart/rtl/usbuart_reg_top.sv
@@ -263,8 +263,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_tx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_tx_watermark_we),
@@ -272,11 +272,11 @@
// from internal hardware
.de (hw2reg.intr_state.tx_watermark.de),
- .d (hw2reg.intr_state.tx_watermark.d ),
+ .d (hw2reg.intr_state.tx_watermark.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.tx_watermark.q ),
+ .q (reg2hw.intr_state.tx_watermark.q),
// to register interface (read)
.qs (intr_state_tx_watermark_qs)
@@ -289,8 +289,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_watermark_we),
@@ -298,11 +298,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_watermark.de),
- .d (hw2reg.intr_state.rx_watermark.d ),
+ .d (hw2reg.intr_state.rx_watermark.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_watermark.q ),
+ .q (reg2hw.intr_state.rx_watermark.q),
// to register interface (read)
.qs (intr_state_rx_watermark_qs)
@@ -315,8 +315,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_tx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_tx_overflow_we),
@@ -324,11 +324,11 @@
// from internal hardware
.de (hw2reg.intr_state.tx_overflow.de),
- .d (hw2reg.intr_state.tx_overflow.d ),
+ .d (hw2reg.intr_state.tx_overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.tx_overflow.q ),
+ .q (reg2hw.intr_state.tx_overflow.q),
// to register interface (read)
.qs (intr_state_tx_overflow_qs)
@@ -341,8 +341,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_overflow_we),
@@ -350,11 +350,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_overflow.de),
- .d (hw2reg.intr_state.rx_overflow.d ),
+ .d (hw2reg.intr_state.rx_overflow.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_overflow.q ),
+ .q (reg2hw.intr_state.rx_overflow.q),
// to register interface (read)
.qs (intr_state_rx_overflow_qs)
@@ -367,8 +367,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_frame_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_frame_err_we),
@@ -376,11 +376,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_frame_err.de),
- .d (hw2reg.intr_state.rx_frame_err.d ),
+ .d (hw2reg.intr_state.rx_frame_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_frame_err.q ),
+ .q (reg2hw.intr_state.rx_frame_err.q),
// to register interface (read)
.qs (intr_state_rx_frame_err_qs)
@@ -393,8 +393,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_break_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_break_err_we),
@@ -402,11 +402,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_break_err.de),
- .d (hw2reg.intr_state.rx_break_err.d ),
+ .d (hw2reg.intr_state.rx_break_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_break_err.q ),
+ .q (reg2hw.intr_state.rx_break_err.q),
// to register interface (read)
.qs (intr_state_rx_break_err_qs)
@@ -419,8 +419,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_timeout (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_timeout_we),
@@ -428,11 +428,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_timeout.de),
- .d (hw2reg.intr_state.rx_timeout.d ),
+ .d (hw2reg.intr_state.rx_timeout.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_timeout.q ),
+ .q (reg2hw.intr_state.rx_timeout.q),
// to register interface (read)
.qs (intr_state_rx_timeout_qs)
@@ -445,8 +445,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rx_parity_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rx_parity_err_we),
@@ -454,11 +454,11 @@
// from internal hardware
.de (hw2reg.intr_state.rx_parity_err.de),
- .d (hw2reg.intr_state.rx_parity_err.d ),
+ .d (hw2reg.intr_state.rx_parity_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rx_parity_err.q ),
+ .q (reg2hw.intr_state.rx_parity_err.q),
// to register interface (read)
.qs (intr_state_rx_parity_err_qs)
@@ -473,8 +473,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_tx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_tx_watermark_we),
@@ -482,11 +482,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.tx_watermark.q ),
+ .q (reg2hw.intr_enable.tx_watermark.q),
// to register interface (read)
.qs (intr_enable_tx_watermark_qs)
@@ -499,8 +499,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_watermark (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_watermark_we),
@@ -508,11 +508,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_watermark.q ),
+ .q (reg2hw.intr_enable.rx_watermark.q),
// to register interface (read)
.qs (intr_enable_rx_watermark_qs)
@@ -525,8 +525,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_tx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_tx_overflow_we),
@@ -534,11 +534,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.tx_overflow.q ),
+ .q (reg2hw.intr_enable.tx_overflow.q),
// to register interface (read)
.qs (intr_enable_tx_overflow_qs)
@@ -551,8 +551,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_overflow (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_overflow_we),
@@ -560,11 +560,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_overflow.q ),
+ .q (reg2hw.intr_enable.rx_overflow.q),
// to register interface (read)
.qs (intr_enable_rx_overflow_qs)
@@ -577,8 +577,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_frame_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_frame_err_we),
@@ -586,11 +586,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_frame_err.q ),
+ .q (reg2hw.intr_enable.rx_frame_err.q),
// to register interface (read)
.qs (intr_enable_rx_frame_err_qs)
@@ -603,8 +603,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_break_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_break_err_we),
@@ -612,11 +612,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_break_err.q ),
+ .q (reg2hw.intr_enable.rx_break_err.q),
// to register interface (read)
.qs (intr_enable_rx_break_err_qs)
@@ -629,8 +629,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_timeout (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_timeout_we),
@@ -638,11 +638,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_timeout.q ),
+ .q (reg2hw.intr_enable.rx_timeout.q),
// to register interface (read)
.qs (intr_enable_rx_timeout_qs)
@@ -655,8 +655,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rx_parity_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rx_parity_err_we),
@@ -664,11 +664,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rx_parity_err.q ),
+ .q (reg2hw.intr_enable.rx_parity_err.q),
// to register interface (read)
.qs (intr_enable_rx_parity_err_qs)
@@ -687,7 +687,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.tx_watermark.qe),
- .q (reg2hw.intr_test.tx_watermark.q ),
+ .q (reg2hw.intr_test.tx_watermark.q),
.qs ()
);
@@ -702,7 +702,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_watermark.qe),
- .q (reg2hw.intr_test.rx_watermark.q ),
+ .q (reg2hw.intr_test.rx_watermark.q),
.qs ()
);
@@ -717,7 +717,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.tx_overflow.qe),
- .q (reg2hw.intr_test.tx_overflow.q ),
+ .q (reg2hw.intr_test.tx_overflow.q),
.qs ()
);
@@ -732,7 +732,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_overflow.qe),
- .q (reg2hw.intr_test.rx_overflow.q ),
+ .q (reg2hw.intr_test.rx_overflow.q),
.qs ()
);
@@ -747,7 +747,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_frame_err.qe),
- .q (reg2hw.intr_test.rx_frame_err.q ),
+ .q (reg2hw.intr_test.rx_frame_err.q),
.qs ()
);
@@ -762,7 +762,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_break_err.qe),
- .q (reg2hw.intr_test.rx_break_err.q ),
+ .q (reg2hw.intr_test.rx_break_err.q),
.qs ()
);
@@ -777,7 +777,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_timeout.qe),
- .q (reg2hw.intr_test.rx_timeout.q ),
+ .q (reg2hw.intr_test.rx_timeout.q),
.qs ()
);
@@ -792,7 +792,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rx_parity_err.qe),
- .q (reg2hw.intr_test.rx_parity_err.q ),
+ .q (reg2hw.intr_test.rx_parity_err.q),
.qs ()
);
@@ -805,8 +805,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_tx (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_tx_we),
@@ -814,11 +814,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.tx.q ),
+ .q (reg2hw.ctrl.tx.q),
// to register interface (read)
.qs (ctrl_tx_qs)
@@ -831,8 +831,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_rx (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_rx_we),
@@ -840,11 +840,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.rx.q ),
+ .q (reg2hw.ctrl.rx.q),
// to register interface (read)
.qs (ctrl_rx_qs)
@@ -857,8 +857,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_nf (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_nf_we),
@@ -866,11 +866,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.nf.q ),
+ .q (reg2hw.ctrl.nf.q),
// to register interface (read)
.qs (ctrl_nf_qs)
@@ -883,8 +883,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_slpbk (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_slpbk_we),
@@ -892,11 +892,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.slpbk.q ),
+ .q (reg2hw.ctrl.slpbk.q),
// to register interface (read)
.qs (ctrl_slpbk_qs)
@@ -909,8 +909,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_llpbk (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_llpbk_we),
@@ -918,11 +918,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.llpbk.q ),
+ .q (reg2hw.ctrl.llpbk.q),
// to register interface (read)
.qs (ctrl_llpbk_qs)
@@ -935,8 +935,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_parity_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_parity_en_we),
@@ -944,11 +944,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.parity_en.q ),
+ .q (reg2hw.ctrl.parity_en.q),
// to register interface (read)
.qs (ctrl_parity_en_qs)
@@ -961,8 +961,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ctrl_parity_odd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_parity_odd_we),
@@ -970,11 +970,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.parity_odd.q ),
+ .q (reg2hw.ctrl.parity_odd.q),
// to register interface (read)
.qs (ctrl_parity_odd_qs)
@@ -987,8 +987,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ctrl_rxblvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_rxblvl_we),
@@ -996,11 +996,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.rxblvl.q ),
+ .q (reg2hw.ctrl.rxblvl.q),
// to register interface (read)
.qs (ctrl_rxblvl_qs)
@@ -1013,8 +1013,8 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_ctrl_nco (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ctrl_nco_we),
@@ -1022,11 +1022,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.nco.q ),
+ .q (reg2hw.ctrl.nco.q),
// to register interface (read)
.qs (ctrl_nco_qs)
@@ -1136,7 +1136,7 @@
.d (hw2reg.rdata.d),
.qre (reg2hw.rdata.re),
.qe (),
- .q (reg2hw.rdata.q ),
+ .q (reg2hw.rdata.q),
.qs (rdata_qs)
);
@@ -1148,8 +1148,8 @@
.SWACCESS("WO"),
.RESVAL (8'h0)
) u_wdata (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wdata_we),
@@ -1157,12 +1157,13 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.wdata.qe),
- .q (reg2hw.wdata.q ),
+ .q (reg2hw.wdata.q),
+ // to register interface (read)
.qs ()
);
@@ -1175,8 +1176,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_fifo_ctrl_rxrst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_rxrst_we),
@@ -1184,11 +1185,11 @@
// from internal hardware
.de (hw2reg.fifo_ctrl.rxrst.de),
- .d (hw2reg.fifo_ctrl.rxrst.d ),
+ .d (hw2reg.fifo_ctrl.rxrst.d),
// to internal hardware
.qe (reg2hw.fifo_ctrl.rxrst.qe),
- .q (reg2hw.fifo_ctrl.rxrst.q ),
+ .q (reg2hw.fifo_ctrl.rxrst.q),
// to register interface (read)
.qs (fifo_ctrl_rxrst_qs)
@@ -1201,8 +1202,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_fifo_ctrl_txrst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_txrst_we),
@@ -1210,11 +1211,11 @@
// from internal hardware
.de (hw2reg.fifo_ctrl.txrst.de),
- .d (hw2reg.fifo_ctrl.txrst.d ),
+ .d (hw2reg.fifo_ctrl.txrst.d),
// to internal hardware
.qe (reg2hw.fifo_ctrl.txrst.qe),
- .q (reg2hw.fifo_ctrl.txrst.q ),
+ .q (reg2hw.fifo_ctrl.txrst.q),
// to register interface (read)
.qs (fifo_ctrl_txrst_qs)
@@ -1227,8 +1228,8 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_fifo_ctrl_rxilvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_rxilvl_we),
@@ -1236,11 +1237,11 @@
// from internal hardware
.de (hw2reg.fifo_ctrl.rxilvl.de),
- .d (hw2reg.fifo_ctrl.rxilvl.d ),
+ .d (hw2reg.fifo_ctrl.rxilvl.d),
// to internal hardware
.qe (reg2hw.fifo_ctrl.rxilvl.qe),
- .q (reg2hw.fifo_ctrl.rxilvl.q ),
+ .q (reg2hw.fifo_ctrl.rxilvl.q),
// to register interface (read)
.qs (fifo_ctrl_rxilvl_qs)
@@ -1253,8 +1254,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_fifo_ctrl_txilvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_ctrl_txilvl_we),
@@ -1262,11 +1263,11 @@
// from internal hardware
.de (hw2reg.fifo_ctrl.txilvl.de),
- .d (hw2reg.fifo_ctrl.txilvl.d ),
+ .d (hw2reg.fifo_ctrl.txilvl.d),
// to internal hardware
.qe (reg2hw.fifo_ctrl.txilvl.qe),
- .q (reg2hw.fifo_ctrl.txilvl.q ),
+ .q (reg2hw.fifo_ctrl.txilvl.q),
// to register interface (read)
.qs (fifo_ctrl_txilvl_qs)
@@ -1313,8 +1314,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ovrd_txen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ovrd_txen_we),
@@ -1322,11 +1323,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ovrd.txen.q ),
+ .q (reg2hw.ovrd.txen.q),
// to register interface (read)
.qs (ovrd_txen_qs)
@@ -1339,8 +1340,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ovrd_txval (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ovrd_txval_we),
@@ -1348,11 +1349,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ovrd.txval.q ),
+ .q (reg2hw.ovrd.txval.q),
// to register interface (read)
.qs (ovrd_txval_qs)
@@ -1383,8 +1384,8 @@
.SWACCESS("RW"),
.RESVAL (24'h0)
) u_timeout_ctrl_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timeout_ctrl_val_we),
@@ -1392,11 +1393,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timeout_ctrl.val.q ),
+ .q (reg2hw.timeout_ctrl.val.q),
// to register interface (read)
.qs (timeout_ctrl_val_qs)
@@ -1409,8 +1410,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_timeout_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (timeout_ctrl_en_we),
@@ -1418,11 +1419,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.timeout_ctrl.en.q ),
+ .q (reg2hw.timeout_ctrl.en.q),
// to register interface (read)
.qs (timeout_ctrl_en_qs)
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index 74af3f5..9ed9a9c 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -1024,8 +1024,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_classa (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_classa_we),
@@ -1033,11 +1033,11 @@
// from internal hardware
.de (hw2reg.intr_state.classa.de),
- .d (hw2reg.intr_state.classa.d ),
+ .d (hw2reg.intr_state.classa.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.classa.q ),
+ .q (reg2hw.intr_state.classa.q),
// to register interface (read)
.qs (intr_state_classa_qs)
@@ -1050,8 +1050,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_classb (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_classb_we),
@@ -1059,11 +1059,11 @@
// from internal hardware
.de (hw2reg.intr_state.classb.de),
- .d (hw2reg.intr_state.classb.d ),
+ .d (hw2reg.intr_state.classb.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.classb.q ),
+ .q (reg2hw.intr_state.classb.q),
// to register interface (read)
.qs (intr_state_classb_qs)
@@ -1076,8 +1076,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_classc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_classc_we),
@@ -1085,11 +1085,11 @@
// from internal hardware
.de (hw2reg.intr_state.classc.de),
- .d (hw2reg.intr_state.classc.d ),
+ .d (hw2reg.intr_state.classc.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.classc.q ),
+ .q (reg2hw.intr_state.classc.q),
// to register interface (read)
.qs (intr_state_classc_qs)
@@ -1102,8 +1102,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_classd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_classd_we),
@@ -1111,11 +1111,11 @@
// from internal hardware
.de (hw2reg.intr_state.classd.de),
- .d (hw2reg.intr_state.classd.d ),
+ .d (hw2reg.intr_state.classd.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.classd.q ),
+ .q (reg2hw.intr_state.classd.q),
// to register interface (read)
.qs (intr_state_classd_qs)
@@ -1130,8 +1130,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_classa (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_classa_we),
@@ -1139,11 +1139,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.classa.q ),
+ .q (reg2hw.intr_enable.classa.q),
// to register interface (read)
.qs (intr_enable_classa_qs)
@@ -1156,8 +1156,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_classb (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_classb_we),
@@ -1165,11 +1165,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.classb.q ),
+ .q (reg2hw.intr_enable.classb.q),
// to register interface (read)
.qs (intr_enable_classb_qs)
@@ -1182,8 +1182,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_classc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_classc_we),
@@ -1191,11 +1191,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.classc.q ),
+ .q (reg2hw.intr_enable.classc.q),
// to register interface (read)
.qs (intr_enable_classc_qs)
@@ -1208,8 +1208,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_classd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_classd_we),
@@ -1217,11 +1217,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.classd.q ),
+ .q (reg2hw.intr_enable.classd.q),
// to register interface (read)
.qs (intr_enable_classd_qs)
@@ -1240,7 +1240,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.classa.qe),
- .q (reg2hw.intr_test.classa.q ),
+ .q (reg2hw.intr_test.classa.q),
.qs ()
);
@@ -1255,7 +1255,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.classb.qe),
- .q (reg2hw.intr_test.classb.q ),
+ .q (reg2hw.intr_test.classb.q),
.qs ()
);
@@ -1270,7 +1270,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.classc.qe),
- .q (reg2hw.intr_test.classc.q ),
+ .q (reg2hw.intr_test.classc.q),
.qs ()
);
@@ -1285,7 +1285,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.classd.qe),
- .q (reg2hw.intr_test.classd.q ),
+ .q (reg2hw.intr_test.classd.q),
.qs ()
);
@@ -1297,8 +1297,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_ping_timer_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ping_timer_regwen_we),
@@ -1306,7 +1306,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -1324,20 +1324,20 @@
.SWACCESS("RW"),
.RESVAL (24'h20)
) u_ping_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ping_timeout_cyc_we & ping_timer_regwen_qs),
.wd (ping_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ping_timeout_cyc.q ),
+ .q (reg2hw.ping_timeout_cyc.q),
// to register interface (read)
.qs (ping_timeout_cyc_qs)
@@ -1351,20 +1351,20 @@
.SWACCESS("W1S"),
.RESVAL (1'h0)
) u_ping_timer_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ping_timer_en_we & ping_timer_regwen_qs),
.wd (ping_timer_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ping_timer_en.q ),
+ .q (reg2hw.ping_timer_en.q),
// to register interface (read)
.qs (ping_timer_en_qs)
@@ -1380,8 +1380,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_0_we),
@@ -1389,11 +1389,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[0].q ),
+ .q (reg2hw.alert_regwen[0].q),
// to register interface (read)
.qs (alert_regwen_0_qs)
@@ -1407,8 +1407,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_1_we),
@@ -1416,11 +1416,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[1].q ),
+ .q (reg2hw.alert_regwen[1].q),
// to register interface (read)
.qs (alert_regwen_1_qs)
@@ -1434,8 +1434,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_2_we),
@@ -1443,11 +1443,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[2].q ),
+ .q (reg2hw.alert_regwen[2].q),
// to register interface (read)
.qs (alert_regwen_2_qs)
@@ -1461,8 +1461,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_3_we),
@@ -1470,11 +1470,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[3].q ),
+ .q (reg2hw.alert_regwen[3].q),
// to register interface (read)
.qs (alert_regwen_3_qs)
@@ -1488,8 +1488,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_4_we),
@@ -1497,11 +1497,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[4].q ),
+ .q (reg2hw.alert_regwen[4].q),
// to register interface (read)
.qs (alert_regwen_4_qs)
@@ -1515,8 +1515,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_5_we),
@@ -1524,11 +1524,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[5].q ),
+ .q (reg2hw.alert_regwen[5].q),
// to register interface (read)
.qs (alert_regwen_5_qs)
@@ -1542,8 +1542,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_6_we),
@@ -1551,11 +1551,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[6].q ),
+ .q (reg2hw.alert_regwen[6].q),
// to register interface (read)
.qs (alert_regwen_6_qs)
@@ -1569,8 +1569,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_7_we),
@@ -1578,11 +1578,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[7].q ),
+ .q (reg2hw.alert_regwen[7].q),
// to register interface (read)
.qs (alert_regwen_7_qs)
@@ -1596,8 +1596,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_8_we),
@@ -1605,11 +1605,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[8].q ),
+ .q (reg2hw.alert_regwen[8].q),
// to register interface (read)
.qs (alert_regwen_8_qs)
@@ -1623,8 +1623,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_9_we),
@@ -1632,11 +1632,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[9].q ),
+ .q (reg2hw.alert_regwen[9].q),
// to register interface (read)
.qs (alert_regwen_9_qs)
@@ -1650,8 +1650,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_10_we),
@@ -1659,11 +1659,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[10].q ),
+ .q (reg2hw.alert_regwen[10].q),
// to register interface (read)
.qs (alert_regwen_10_qs)
@@ -1677,8 +1677,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_11_we),
@@ -1686,11 +1686,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[11].q ),
+ .q (reg2hw.alert_regwen[11].q),
// to register interface (read)
.qs (alert_regwen_11_qs)
@@ -1704,8 +1704,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_12_we),
@@ -1713,11 +1713,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[12].q ),
+ .q (reg2hw.alert_regwen[12].q),
// to register interface (read)
.qs (alert_regwen_12_qs)
@@ -1731,8 +1731,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_13_we),
@@ -1740,11 +1740,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[13].q ),
+ .q (reg2hw.alert_regwen[13].q),
// to register interface (read)
.qs (alert_regwen_13_qs)
@@ -1758,8 +1758,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_14_we),
@@ -1767,11 +1767,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[14].q ),
+ .q (reg2hw.alert_regwen[14].q),
// to register interface (read)
.qs (alert_regwen_14_qs)
@@ -1785,8 +1785,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_15_we),
@@ -1794,11 +1794,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[15].q ),
+ .q (reg2hw.alert_regwen[15].q),
// to register interface (read)
.qs (alert_regwen_15_qs)
@@ -1812,8 +1812,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_16_we),
@@ -1821,11 +1821,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[16].q ),
+ .q (reg2hw.alert_regwen[16].q),
// to register interface (read)
.qs (alert_regwen_16_qs)
@@ -1839,8 +1839,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_17_we),
@@ -1848,11 +1848,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[17].q ),
+ .q (reg2hw.alert_regwen[17].q),
// to register interface (read)
.qs (alert_regwen_17_qs)
@@ -1866,8 +1866,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_18_we),
@@ -1875,11 +1875,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[18].q ),
+ .q (reg2hw.alert_regwen[18].q),
// to register interface (read)
.qs (alert_regwen_18_qs)
@@ -1893,8 +1893,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_19_we),
@@ -1902,11 +1902,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[19].q ),
+ .q (reg2hw.alert_regwen[19].q),
// to register interface (read)
.qs (alert_regwen_19_qs)
@@ -1920,8 +1920,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_20_we),
@@ -1929,11 +1929,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[20].q ),
+ .q (reg2hw.alert_regwen[20].q),
// to register interface (read)
.qs (alert_regwen_20_qs)
@@ -1947,8 +1947,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_21_we),
@@ -1956,11 +1956,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[21].q ),
+ .q (reg2hw.alert_regwen[21].q),
// to register interface (read)
.qs (alert_regwen_21_qs)
@@ -1974,8 +1974,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_22_we),
@@ -1983,11 +1983,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[22].q ),
+ .q (reg2hw.alert_regwen[22].q),
// to register interface (read)
.qs (alert_regwen_22_qs)
@@ -2001,8 +2001,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_23_we),
@@ -2010,11 +2010,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[23].q ),
+ .q (reg2hw.alert_regwen[23].q),
// to register interface (read)
.qs (alert_regwen_23_qs)
@@ -2028,8 +2028,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_24_we),
@@ -2037,11 +2037,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[24].q ),
+ .q (reg2hw.alert_regwen[24].q),
// to register interface (read)
.qs (alert_regwen_24_qs)
@@ -2055,8 +2055,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_25_we),
@@ -2064,11 +2064,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[25].q ),
+ .q (reg2hw.alert_regwen[25].q),
// to register interface (read)
.qs (alert_regwen_25_qs)
@@ -2082,8 +2082,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_26_we),
@@ -2091,11 +2091,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[26].q ),
+ .q (reg2hw.alert_regwen[26].q),
// to register interface (read)
.qs (alert_regwen_26_qs)
@@ -2109,8 +2109,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_27_we),
@@ -2118,11 +2118,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[27].q ),
+ .q (reg2hw.alert_regwen[27].q),
// to register interface (read)
.qs (alert_regwen_27_qs)
@@ -2136,8 +2136,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_28_we),
@@ -2145,11 +2145,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[28].q ),
+ .q (reg2hw.alert_regwen[28].q),
// to register interface (read)
.qs (alert_regwen_28_qs)
@@ -2163,8 +2163,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_29_we),
@@ -2172,11 +2172,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[29].q ),
+ .q (reg2hw.alert_regwen[29].q),
// to register interface (read)
.qs (alert_regwen_29_qs)
@@ -2190,8 +2190,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_30_we),
@@ -2199,11 +2199,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[30].q ),
+ .q (reg2hw.alert_regwen[30].q),
// to register interface (read)
.qs (alert_regwen_30_qs)
@@ -2217,8 +2217,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_31_we),
@@ -2226,11 +2226,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[31].q ),
+ .q (reg2hw.alert_regwen[31].q),
// to register interface (read)
.qs (alert_regwen_31_qs)
@@ -2244,8 +2244,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_32_we),
@@ -2253,11 +2253,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[32].q ),
+ .q (reg2hw.alert_regwen[32].q),
// to register interface (read)
.qs (alert_regwen_32_qs)
@@ -2271,8 +2271,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_33_we),
@@ -2280,11 +2280,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[33].q ),
+ .q (reg2hw.alert_regwen[33].q),
// to register interface (read)
.qs (alert_regwen_33_qs)
@@ -2298,8 +2298,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_34_we),
@@ -2307,11 +2307,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[34].q ),
+ .q (reg2hw.alert_regwen[34].q),
// to register interface (read)
.qs (alert_regwen_34_qs)
@@ -2325,8 +2325,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_35_we),
@@ -2334,11 +2334,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[35].q ),
+ .q (reg2hw.alert_regwen[35].q),
// to register interface (read)
.qs (alert_regwen_35_qs)
@@ -2352,8 +2352,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_36_we),
@@ -2361,11 +2361,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[36].q ),
+ .q (reg2hw.alert_regwen[36].q),
// to register interface (read)
.qs (alert_regwen_36_qs)
@@ -2379,8 +2379,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_37_we),
@@ -2388,11 +2388,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[37].q ),
+ .q (reg2hw.alert_regwen[37].q),
// to register interface (read)
.qs (alert_regwen_37_qs)
@@ -2406,8 +2406,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_38_we),
@@ -2415,11 +2415,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_regwen[38].q ),
+ .q (reg2hw.alert_regwen[38].q),
// to register interface (read)
.qs (alert_regwen_38_qs)
@@ -2435,20 +2435,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_0_we & alert_regwen_0_qs),
.wd (alert_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[0].q ),
+ .q (reg2hw.alert_en[0].q),
// to register interface (read)
.qs (alert_en_0_qs)
@@ -2462,20 +2462,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_1_we & alert_regwen_1_qs),
.wd (alert_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[1].q ),
+ .q (reg2hw.alert_en[1].q),
// to register interface (read)
.qs (alert_en_1_qs)
@@ -2489,20 +2489,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_2_we & alert_regwen_2_qs),
.wd (alert_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[2].q ),
+ .q (reg2hw.alert_en[2].q),
// to register interface (read)
.qs (alert_en_2_qs)
@@ -2516,20 +2516,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_3_we & alert_regwen_3_qs),
.wd (alert_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[3].q ),
+ .q (reg2hw.alert_en[3].q),
// to register interface (read)
.qs (alert_en_3_qs)
@@ -2543,20 +2543,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_4_we & alert_regwen_4_qs),
.wd (alert_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[4].q ),
+ .q (reg2hw.alert_en[4].q),
// to register interface (read)
.qs (alert_en_4_qs)
@@ -2570,20 +2570,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_5_we & alert_regwen_5_qs),
.wd (alert_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[5].q ),
+ .q (reg2hw.alert_en[5].q),
// to register interface (read)
.qs (alert_en_5_qs)
@@ -2597,20 +2597,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_6_we & alert_regwen_6_qs),
.wd (alert_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[6].q ),
+ .q (reg2hw.alert_en[6].q),
// to register interface (read)
.qs (alert_en_6_qs)
@@ -2624,20 +2624,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_7_we & alert_regwen_7_qs),
.wd (alert_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[7].q ),
+ .q (reg2hw.alert_en[7].q),
// to register interface (read)
.qs (alert_en_7_qs)
@@ -2651,20 +2651,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_8_we & alert_regwen_8_qs),
.wd (alert_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[8].q ),
+ .q (reg2hw.alert_en[8].q),
// to register interface (read)
.qs (alert_en_8_qs)
@@ -2678,20 +2678,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_9_we & alert_regwen_9_qs),
.wd (alert_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[9].q ),
+ .q (reg2hw.alert_en[9].q),
// to register interface (read)
.qs (alert_en_9_qs)
@@ -2705,20 +2705,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_10_we & alert_regwen_10_qs),
.wd (alert_en_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[10].q ),
+ .q (reg2hw.alert_en[10].q),
// to register interface (read)
.qs (alert_en_10_qs)
@@ -2732,20 +2732,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_11_we & alert_regwen_11_qs),
.wd (alert_en_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[11].q ),
+ .q (reg2hw.alert_en[11].q),
// to register interface (read)
.qs (alert_en_11_qs)
@@ -2759,20 +2759,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_12_we & alert_regwen_12_qs),
.wd (alert_en_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[12].q ),
+ .q (reg2hw.alert_en[12].q),
// to register interface (read)
.qs (alert_en_12_qs)
@@ -2786,20 +2786,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_13_we & alert_regwen_13_qs),
.wd (alert_en_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[13].q ),
+ .q (reg2hw.alert_en[13].q),
// to register interface (read)
.qs (alert_en_13_qs)
@@ -2813,20 +2813,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_14_we & alert_regwen_14_qs),
.wd (alert_en_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[14].q ),
+ .q (reg2hw.alert_en[14].q),
// to register interface (read)
.qs (alert_en_14_qs)
@@ -2840,20 +2840,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_15_we & alert_regwen_15_qs),
.wd (alert_en_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[15].q ),
+ .q (reg2hw.alert_en[15].q),
// to register interface (read)
.qs (alert_en_15_qs)
@@ -2867,20 +2867,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_16_we & alert_regwen_16_qs),
.wd (alert_en_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[16].q ),
+ .q (reg2hw.alert_en[16].q),
// to register interface (read)
.qs (alert_en_16_qs)
@@ -2894,20 +2894,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_17_we & alert_regwen_17_qs),
.wd (alert_en_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[17].q ),
+ .q (reg2hw.alert_en[17].q),
// to register interface (read)
.qs (alert_en_17_qs)
@@ -2921,20 +2921,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_18_we & alert_regwen_18_qs),
.wd (alert_en_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[18].q ),
+ .q (reg2hw.alert_en[18].q),
// to register interface (read)
.qs (alert_en_18_qs)
@@ -2948,20 +2948,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_19_we & alert_regwen_19_qs),
.wd (alert_en_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[19].q ),
+ .q (reg2hw.alert_en[19].q),
// to register interface (read)
.qs (alert_en_19_qs)
@@ -2975,20 +2975,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_20_we & alert_regwen_20_qs),
.wd (alert_en_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[20].q ),
+ .q (reg2hw.alert_en[20].q),
// to register interface (read)
.qs (alert_en_20_qs)
@@ -3002,20 +3002,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_21_we & alert_regwen_21_qs),
.wd (alert_en_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[21].q ),
+ .q (reg2hw.alert_en[21].q),
// to register interface (read)
.qs (alert_en_21_qs)
@@ -3029,20 +3029,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_22_we & alert_regwen_22_qs),
.wd (alert_en_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[22].q ),
+ .q (reg2hw.alert_en[22].q),
// to register interface (read)
.qs (alert_en_22_qs)
@@ -3056,20 +3056,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_23_we & alert_regwen_23_qs),
.wd (alert_en_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[23].q ),
+ .q (reg2hw.alert_en[23].q),
// to register interface (read)
.qs (alert_en_23_qs)
@@ -3083,20 +3083,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_24_we & alert_regwen_24_qs),
.wd (alert_en_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[24].q ),
+ .q (reg2hw.alert_en[24].q),
// to register interface (read)
.qs (alert_en_24_qs)
@@ -3110,20 +3110,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_25_we & alert_regwen_25_qs),
.wd (alert_en_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[25].q ),
+ .q (reg2hw.alert_en[25].q),
// to register interface (read)
.qs (alert_en_25_qs)
@@ -3137,20 +3137,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_26_we & alert_regwen_26_qs),
.wd (alert_en_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[26].q ),
+ .q (reg2hw.alert_en[26].q),
// to register interface (read)
.qs (alert_en_26_qs)
@@ -3164,20 +3164,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_27_we & alert_regwen_27_qs),
.wd (alert_en_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[27].q ),
+ .q (reg2hw.alert_en[27].q),
// to register interface (read)
.qs (alert_en_27_qs)
@@ -3191,20 +3191,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_28_we & alert_regwen_28_qs),
.wd (alert_en_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[28].q ),
+ .q (reg2hw.alert_en[28].q),
// to register interface (read)
.qs (alert_en_28_qs)
@@ -3218,20 +3218,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_29_we & alert_regwen_29_qs),
.wd (alert_en_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[29].q ),
+ .q (reg2hw.alert_en[29].q),
// to register interface (read)
.qs (alert_en_29_qs)
@@ -3245,20 +3245,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_30_we & alert_regwen_30_qs),
.wd (alert_en_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[30].q ),
+ .q (reg2hw.alert_en[30].q),
// to register interface (read)
.qs (alert_en_30_qs)
@@ -3272,20 +3272,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_31_we & alert_regwen_31_qs),
.wd (alert_en_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[31].q ),
+ .q (reg2hw.alert_en[31].q),
// to register interface (read)
.qs (alert_en_31_qs)
@@ -3299,20 +3299,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_32_we & alert_regwen_32_qs),
.wd (alert_en_32_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[32].q ),
+ .q (reg2hw.alert_en[32].q),
// to register interface (read)
.qs (alert_en_32_qs)
@@ -3326,20 +3326,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_33_we & alert_regwen_33_qs),
.wd (alert_en_33_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[33].q ),
+ .q (reg2hw.alert_en[33].q),
// to register interface (read)
.qs (alert_en_33_qs)
@@ -3353,20 +3353,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_34_we & alert_regwen_34_qs),
.wd (alert_en_34_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[34].q ),
+ .q (reg2hw.alert_en[34].q),
// to register interface (read)
.qs (alert_en_34_qs)
@@ -3380,20 +3380,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_35_we & alert_regwen_35_qs),
.wd (alert_en_35_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[35].q ),
+ .q (reg2hw.alert_en[35].q),
// to register interface (read)
.qs (alert_en_35_qs)
@@ -3407,20 +3407,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_36_we & alert_regwen_36_qs),
.wd (alert_en_36_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[36].q ),
+ .q (reg2hw.alert_en[36].q),
// to register interface (read)
.qs (alert_en_36_qs)
@@ -3434,20 +3434,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_37_we & alert_regwen_37_qs),
.wd (alert_en_37_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[37].q ),
+ .q (reg2hw.alert_en[37].q),
// to register interface (read)
.qs (alert_en_37_qs)
@@ -3461,20 +3461,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_en_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_en_38_we & alert_regwen_38_qs),
.wd (alert_en_38_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_en[38].q ),
+ .q (reg2hw.alert_en[38].q),
// to register interface (read)
.qs (alert_en_38_qs)
@@ -3490,20 +3490,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_0_we & alert_regwen_0_qs),
.wd (alert_class_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[0].q ),
+ .q (reg2hw.alert_class[0].q),
// to register interface (read)
.qs (alert_class_0_qs)
@@ -3517,20 +3517,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_1_we & alert_regwen_1_qs),
.wd (alert_class_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[1].q ),
+ .q (reg2hw.alert_class[1].q),
// to register interface (read)
.qs (alert_class_1_qs)
@@ -3544,20 +3544,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_2_we & alert_regwen_2_qs),
.wd (alert_class_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[2].q ),
+ .q (reg2hw.alert_class[2].q),
// to register interface (read)
.qs (alert_class_2_qs)
@@ -3571,20 +3571,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_3_we & alert_regwen_3_qs),
.wd (alert_class_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[3].q ),
+ .q (reg2hw.alert_class[3].q),
// to register interface (read)
.qs (alert_class_3_qs)
@@ -3598,20 +3598,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_4_we & alert_regwen_4_qs),
.wd (alert_class_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[4].q ),
+ .q (reg2hw.alert_class[4].q),
// to register interface (read)
.qs (alert_class_4_qs)
@@ -3625,20 +3625,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_5_we & alert_regwen_5_qs),
.wd (alert_class_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[5].q ),
+ .q (reg2hw.alert_class[5].q),
// to register interface (read)
.qs (alert_class_5_qs)
@@ -3652,20 +3652,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_6_we & alert_regwen_6_qs),
.wd (alert_class_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[6].q ),
+ .q (reg2hw.alert_class[6].q),
// to register interface (read)
.qs (alert_class_6_qs)
@@ -3679,20 +3679,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_7_we & alert_regwen_7_qs),
.wd (alert_class_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[7].q ),
+ .q (reg2hw.alert_class[7].q),
// to register interface (read)
.qs (alert_class_7_qs)
@@ -3706,20 +3706,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_8_we & alert_regwen_8_qs),
.wd (alert_class_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[8].q ),
+ .q (reg2hw.alert_class[8].q),
// to register interface (read)
.qs (alert_class_8_qs)
@@ -3733,20 +3733,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_9_we & alert_regwen_9_qs),
.wd (alert_class_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[9].q ),
+ .q (reg2hw.alert_class[9].q),
// to register interface (read)
.qs (alert_class_9_qs)
@@ -3760,20 +3760,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_10_we & alert_regwen_10_qs),
.wd (alert_class_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[10].q ),
+ .q (reg2hw.alert_class[10].q),
// to register interface (read)
.qs (alert_class_10_qs)
@@ -3787,20 +3787,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_11_we & alert_regwen_11_qs),
.wd (alert_class_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[11].q ),
+ .q (reg2hw.alert_class[11].q),
// to register interface (read)
.qs (alert_class_11_qs)
@@ -3814,20 +3814,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_12_we & alert_regwen_12_qs),
.wd (alert_class_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[12].q ),
+ .q (reg2hw.alert_class[12].q),
// to register interface (read)
.qs (alert_class_12_qs)
@@ -3841,20 +3841,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_13_we & alert_regwen_13_qs),
.wd (alert_class_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[13].q ),
+ .q (reg2hw.alert_class[13].q),
// to register interface (read)
.qs (alert_class_13_qs)
@@ -3868,20 +3868,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_14_we & alert_regwen_14_qs),
.wd (alert_class_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[14].q ),
+ .q (reg2hw.alert_class[14].q),
// to register interface (read)
.qs (alert_class_14_qs)
@@ -3895,20 +3895,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_15_we & alert_regwen_15_qs),
.wd (alert_class_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[15].q ),
+ .q (reg2hw.alert_class[15].q),
// to register interface (read)
.qs (alert_class_15_qs)
@@ -3922,20 +3922,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_16_we & alert_regwen_16_qs),
.wd (alert_class_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[16].q ),
+ .q (reg2hw.alert_class[16].q),
// to register interface (read)
.qs (alert_class_16_qs)
@@ -3949,20 +3949,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_17_we & alert_regwen_17_qs),
.wd (alert_class_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[17].q ),
+ .q (reg2hw.alert_class[17].q),
// to register interface (read)
.qs (alert_class_17_qs)
@@ -3976,20 +3976,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_18_we & alert_regwen_18_qs),
.wd (alert_class_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[18].q ),
+ .q (reg2hw.alert_class[18].q),
// to register interface (read)
.qs (alert_class_18_qs)
@@ -4003,20 +4003,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_19_we & alert_regwen_19_qs),
.wd (alert_class_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[19].q ),
+ .q (reg2hw.alert_class[19].q),
// to register interface (read)
.qs (alert_class_19_qs)
@@ -4030,20 +4030,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_20_we & alert_regwen_20_qs),
.wd (alert_class_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[20].q ),
+ .q (reg2hw.alert_class[20].q),
// to register interface (read)
.qs (alert_class_20_qs)
@@ -4057,20 +4057,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_21_we & alert_regwen_21_qs),
.wd (alert_class_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[21].q ),
+ .q (reg2hw.alert_class[21].q),
// to register interface (read)
.qs (alert_class_21_qs)
@@ -4084,20 +4084,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_22_we & alert_regwen_22_qs),
.wd (alert_class_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[22].q ),
+ .q (reg2hw.alert_class[22].q),
// to register interface (read)
.qs (alert_class_22_qs)
@@ -4111,20 +4111,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_23_we & alert_regwen_23_qs),
.wd (alert_class_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[23].q ),
+ .q (reg2hw.alert_class[23].q),
// to register interface (read)
.qs (alert_class_23_qs)
@@ -4138,20 +4138,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_24_we & alert_regwen_24_qs),
.wd (alert_class_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[24].q ),
+ .q (reg2hw.alert_class[24].q),
// to register interface (read)
.qs (alert_class_24_qs)
@@ -4165,20 +4165,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_25_we & alert_regwen_25_qs),
.wd (alert_class_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[25].q ),
+ .q (reg2hw.alert_class[25].q),
// to register interface (read)
.qs (alert_class_25_qs)
@@ -4192,20 +4192,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_26_we & alert_regwen_26_qs),
.wd (alert_class_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[26].q ),
+ .q (reg2hw.alert_class[26].q),
// to register interface (read)
.qs (alert_class_26_qs)
@@ -4219,20 +4219,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_27_we & alert_regwen_27_qs),
.wd (alert_class_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[27].q ),
+ .q (reg2hw.alert_class[27].q),
// to register interface (read)
.qs (alert_class_27_qs)
@@ -4246,20 +4246,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_28_we & alert_regwen_28_qs),
.wd (alert_class_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[28].q ),
+ .q (reg2hw.alert_class[28].q),
// to register interface (read)
.qs (alert_class_28_qs)
@@ -4273,20 +4273,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_29_we & alert_regwen_29_qs),
.wd (alert_class_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[29].q ),
+ .q (reg2hw.alert_class[29].q),
// to register interface (read)
.qs (alert_class_29_qs)
@@ -4300,20 +4300,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_30_we & alert_regwen_30_qs),
.wd (alert_class_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[30].q ),
+ .q (reg2hw.alert_class[30].q),
// to register interface (read)
.qs (alert_class_30_qs)
@@ -4327,20 +4327,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_31_we & alert_regwen_31_qs),
.wd (alert_class_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[31].q ),
+ .q (reg2hw.alert_class[31].q),
// to register interface (read)
.qs (alert_class_31_qs)
@@ -4354,20 +4354,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_32_we & alert_regwen_32_qs),
.wd (alert_class_32_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[32].q ),
+ .q (reg2hw.alert_class[32].q),
// to register interface (read)
.qs (alert_class_32_qs)
@@ -4381,20 +4381,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_33_we & alert_regwen_33_qs),
.wd (alert_class_33_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[33].q ),
+ .q (reg2hw.alert_class[33].q),
// to register interface (read)
.qs (alert_class_33_qs)
@@ -4408,20 +4408,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_34_we & alert_regwen_34_qs),
.wd (alert_class_34_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[34].q ),
+ .q (reg2hw.alert_class[34].q),
// to register interface (read)
.qs (alert_class_34_qs)
@@ -4435,20 +4435,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_35_we & alert_regwen_35_qs),
.wd (alert_class_35_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[35].q ),
+ .q (reg2hw.alert_class[35].q),
// to register interface (read)
.qs (alert_class_35_qs)
@@ -4462,20 +4462,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_36_we & alert_regwen_36_qs),
.wd (alert_class_36_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[36].q ),
+ .q (reg2hw.alert_class[36].q),
// to register interface (read)
.qs (alert_class_36_qs)
@@ -4489,20 +4489,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_37_we & alert_regwen_37_qs),
.wd (alert_class_37_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[37].q ),
+ .q (reg2hw.alert_class[37].q),
// to register interface (read)
.qs (alert_class_37_qs)
@@ -4516,20 +4516,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_alert_class_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_class_38_we & alert_regwen_38_qs),
.wd (alert_class_38_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_class[38].q ),
+ .q (reg2hw.alert_class[38].q),
// to register interface (read)
.qs (alert_class_38_qs)
@@ -4545,8 +4545,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_0_we),
@@ -4554,11 +4554,11 @@
// from internal hardware
.de (hw2reg.alert_cause[0].de),
- .d (hw2reg.alert_cause[0].d ),
+ .d (hw2reg.alert_cause[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[0].q ),
+ .q (reg2hw.alert_cause[0].q),
// to register interface (read)
.qs (alert_cause_0_qs)
@@ -4572,8 +4572,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_1_we),
@@ -4581,11 +4581,11 @@
// from internal hardware
.de (hw2reg.alert_cause[1].de),
- .d (hw2reg.alert_cause[1].d ),
+ .d (hw2reg.alert_cause[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[1].q ),
+ .q (reg2hw.alert_cause[1].q),
// to register interface (read)
.qs (alert_cause_1_qs)
@@ -4599,8 +4599,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_2_we),
@@ -4608,11 +4608,11 @@
// from internal hardware
.de (hw2reg.alert_cause[2].de),
- .d (hw2reg.alert_cause[2].d ),
+ .d (hw2reg.alert_cause[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[2].q ),
+ .q (reg2hw.alert_cause[2].q),
// to register interface (read)
.qs (alert_cause_2_qs)
@@ -4626,8 +4626,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_3_we),
@@ -4635,11 +4635,11 @@
// from internal hardware
.de (hw2reg.alert_cause[3].de),
- .d (hw2reg.alert_cause[3].d ),
+ .d (hw2reg.alert_cause[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[3].q ),
+ .q (reg2hw.alert_cause[3].q),
// to register interface (read)
.qs (alert_cause_3_qs)
@@ -4653,8 +4653,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_4_we),
@@ -4662,11 +4662,11 @@
// from internal hardware
.de (hw2reg.alert_cause[4].de),
- .d (hw2reg.alert_cause[4].d ),
+ .d (hw2reg.alert_cause[4].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[4].q ),
+ .q (reg2hw.alert_cause[4].q),
// to register interface (read)
.qs (alert_cause_4_qs)
@@ -4680,8 +4680,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_5_we),
@@ -4689,11 +4689,11 @@
// from internal hardware
.de (hw2reg.alert_cause[5].de),
- .d (hw2reg.alert_cause[5].d ),
+ .d (hw2reg.alert_cause[5].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[5].q ),
+ .q (reg2hw.alert_cause[5].q),
// to register interface (read)
.qs (alert_cause_5_qs)
@@ -4707,8 +4707,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_6_we),
@@ -4716,11 +4716,11 @@
// from internal hardware
.de (hw2reg.alert_cause[6].de),
- .d (hw2reg.alert_cause[6].d ),
+ .d (hw2reg.alert_cause[6].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[6].q ),
+ .q (reg2hw.alert_cause[6].q),
// to register interface (read)
.qs (alert_cause_6_qs)
@@ -4734,8 +4734,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_7_we),
@@ -4743,11 +4743,11 @@
// from internal hardware
.de (hw2reg.alert_cause[7].de),
- .d (hw2reg.alert_cause[7].d ),
+ .d (hw2reg.alert_cause[7].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[7].q ),
+ .q (reg2hw.alert_cause[7].q),
// to register interface (read)
.qs (alert_cause_7_qs)
@@ -4761,8 +4761,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_8_we),
@@ -4770,11 +4770,11 @@
// from internal hardware
.de (hw2reg.alert_cause[8].de),
- .d (hw2reg.alert_cause[8].d ),
+ .d (hw2reg.alert_cause[8].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[8].q ),
+ .q (reg2hw.alert_cause[8].q),
// to register interface (read)
.qs (alert_cause_8_qs)
@@ -4788,8 +4788,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_9_we),
@@ -4797,11 +4797,11 @@
// from internal hardware
.de (hw2reg.alert_cause[9].de),
- .d (hw2reg.alert_cause[9].d ),
+ .d (hw2reg.alert_cause[9].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[9].q ),
+ .q (reg2hw.alert_cause[9].q),
// to register interface (read)
.qs (alert_cause_9_qs)
@@ -4815,8 +4815,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_10_we),
@@ -4824,11 +4824,11 @@
// from internal hardware
.de (hw2reg.alert_cause[10].de),
- .d (hw2reg.alert_cause[10].d ),
+ .d (hw2reg.alert_cause[10].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[10].q ),
+ .q (reg2hw.alert_cause[10].q),
// to register interface (read)
.qs (alert_cause_10_qs)
@@ -4842,8 +4842,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_11_we),
@@ -4851,11 +4851,11 @@
// from internal hardware
.de (hw2reg.alert_cause[11].de),
- .d (hw2reg.alert_cause[11].d ),
+ .d (hw2reg.alert_cause[11].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[11].q ),
+ .q (reg2hw.alert_cause[11].q),
// to register interface (read)
.qs (alert_cause_11_qs)
@@ -4869,8 +4869,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_12_we),
@@ -4878,11 +4878,11 @@
// from internal hardware
.de (hw2reg.alert_cause[12].de),
- .d (hw2reg.alert_cause[12].d ),
+ .d (hw2reg.alert_cause[12].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[12].q ),
+ .q (reg2hw.alert_cause[12].q),
// to register interface (read)
.qs (alert_cause_12_qs)
@@ -4896,8 +4896,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_13_we),
@@ -4905,11 +4905,11 @@
// from internal hardware
.de (hw2reg.alert_cause[13].de),
- .d (hw2reg.alert_cause[13].d ),
+ .d (hw2reg.alert_cause[13].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[13].q ),
+ .q (reg2hw.alert_cause[13].q),
// to register interface (read)
.qs (alert_cause_13_qs)
@@ -4923,8 +4923,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_14_we),
@@ -4932,11 +4932,11 @@
// from internal hardware
.de (hw2reg.alert_cause[14].de),
- .d (hw2reg.alert_cause[14].d ),
+ .d (hw2reg.alert_cause[14].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[14].q ),
+ .q (reg2hw.alert_cause[14].q),
// to register interface (read)
.qs (alert_cause_14_qs)
@@ -4950,8 +4950,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_15_we),
@@ -4959,11 +4959,11 @@
// from internal hardware
.de (hw2reg.alert_cause[15].de),
- .d (hw2reg.alert_cause[15].d ),
+ .d (hw2reg.alert_cause[15].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[15].q ),
+ .q (reg2hw.alert_cause[15].q),
// to register interface (read)
.qs (alert_cause_15_qs)
@@ -4977,8 +4977,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_16_we),
@@ -4986,11 +4986,11 @@
// from internal hardware
.de (hw2reg.alert_cause[16].de),
- .d (hw2reg.alert_cause[16].d ),
+ .d (hw2reg.alert_cause[16].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[16].q ),
+ .q (reg2hw.alert_cause[16].q),
// to register interface (read)
.qs (alert_cause_16_qs)
@@ -5004,8 +5004,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_17_we),
@@ -5013,11 +5013,11 @@
// from internal hardware
.de (hw2reg.alert_cause[17].de),
- .d (hw2reg.alert_cause[17].d ),
+ .d (hw2reg.alert_cause[17].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[17].q ),
+ .q (reg2hw.alert_cause[17].q),
// to register interface (read)
.qs (alert_cause_17_qs)
@@ -5031,8 +5031,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_18_we),
@@ -5040,11 +5040,11 @@
// from internal hardware
.de (hw2reg.alert_cause[18].de),
- .d (hw2reg.alert_cause[18].d ),
+ .d (hw2reg.alert_cause[18].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[18].q ),
+ .q (reg2hw.alert_cause[18].q),
// to register interface (read)
.qs (alert_cause_18_qs)
@@ -5058,8 +5058,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_19_we),
@@ -5067,11 +5067,11 @@
// from internal hardware
.de (hw2reg.alert_cause[19].de),
- .d (hw2reg.alert_cause[19].d ),
+ .d (hw2reg.alert_cause[19].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[19].q ),
+ .q (reg2hw.alert_cause[19].q),
// to register interface (read)
.qs (alert_cause_19_qs)
@@ -5085,8 +5085,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_20_we),
@@ -5094,11 +5094,11 @@
// from internal hardware
.de (hw2reg.alert_cause[20].de),
- .d (hw2reg.alert_cause[20].d ),
+ .d (hw2reg.alert_cause[20].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[20].q ),
+ .q (reg2hw.alert_cause[20].q),
// to register interface (read)
.qs (alert_cause_20_qs)
@@ -5112,8 +5112,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_21_we),
@@ -5121,11 +5121,11 @@
// from internal hardware
.de (hw2reg.alert_cause[21].de),
- .d (hw2reg.alert_cause[21].d ),
+ .d (hw2reg.alert_cause[21].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[21].q ),
+ .q (reg2hw.alert_cause[21].q),
// to register interface (read)
.qs (alert_cause_21_qs)
@@ -5139,8 +5139,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_22_we),
@@ -5148,11 +5148,11 @@
// from internal hardware
.de (hw2reg.alert_cause[22].de),
- .d (hw2reg.alert_cause[22].d ),
+ .d (hw2reg.alert_cause[22].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[22].q ),
+ .q (reg2hw.alert_cause[22].q),
// to register interface (read)
.qs (alert_cause_22_qs)
@@ -5166,8 +5166,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_23_we),
@@ -5175,11 +5175,11 @@
// from internal hardware
.de (hw2reg.alert_cause[23].de),
- .d (hw2reg.alert_cause[23].d ),
+ .d (hw2reg.alert_cause[23].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[23].q ),
+ .q (reg2hw.alert_cause[23].q),
// to register interface (read)
.qs (alert_cause_23_qs)
@@ -5193,8 +5193,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_24_we),
@@ -5202,11 +5202,11 @@
// from internal hardware
.de (hw2reg.alert_cause[24].de),
- .d (hw2reg.alert_cause[24].d ),
+ .d (hw2reg.alert_cause[24].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[24].q ),
+ .q (reg2hw.alert_cause[24].q),
// to register interface (read)
.qs (alert_cause_24_qs)
@@ -5220,8 +5220,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_25_we),
@@ -5229,11 +5229,11 @@
// from internal hardware
.de (hw2reg.alert_cause[25].de),
- .d (hw2reg.alert_cause[25].d ),
+ .d (hw2reg.alert_cause[25].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[25].q ),
+ .q (reg2hw.alert_cause[25].q),
// to register interface (read)
.qs (alert_cause_25_qs)
@@ -5247,8 +5247,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_26_we),
@@ -5256,11 +5256,11 @@
// from internal hardware
.de (hw2reg.alert_cause[26].de),
- .d (hw2reg.alert_cause[26].d ),
+ .d (hw2reg.alert_cause[26].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[26].q ),
+ .q (reg2hw.alert_cause[26].q),
// to register interface (read)
.qs (alert_cause_26_qs)
@@ -5274,8 +5274,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_27_we),
@@ -5283,11 +5283,11 @@
// from internal hardware
.de (hw2reg.alert_cause[27].de),
- .d (hw2reg.alert_cause[27].d ),
+ .d (hw2reg.alert_cause[27].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[27].q ),
+ .q (reg2hw.alert_cause[27].q),
// to register interface (read)
.qs (alert_cause_27_qs)
@@ -5301,8 +5301,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_28_we),
@@ -5310,11 +5310,11 @@
// from internal hardware
.de (hw2reg.alert_cause[28].de),
- .d (hw2reg.alert_cause[28].d ),
+ .d (hw2reg.alert_cause[28].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[28].q ),
+ .q (reg2hw.alert_cause[28].q),
// to register interface (read)
.qs (alert_cause_28_qs)
@@ -5328,8 +5328,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_29_we),
@@ -5337,11 +5337,11 @@
// from internal hardware
.de (hw2reg.alert_cause[29].de),
- .d (hw2reg.alert_cause[29].d ),
+ .d (hw2reg.alert_cause[29].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[29].q ),
+ .q (reg2hw.alert_cause[29].q),
// to register interface (read)
.qs (alert_cause_29_qs)
@@ -5355,8 +5355,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_30_we),
@@ -5364,11 +5364,11 @@
// from internal hardware
.de (hw2reg.alert_cause[30].de),
- .d (hw2reg.alert_cause[30].d ),
+ .d (hw2reg.alert_cause[30].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[30].q ),
+ .q (reg2hw.alert_cause[30].q),
// to register interface (read)
.qs (alert_cause_30_qs)
@@ -5382,8 +5382,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_31_we),
@@ -5391,11 +5391,11 @@
// from internal hardware
.de (hw2reg.alert_cause[31].de),
- .d (hw2reg.alert_cause[31].d ),
+ .d (hw2reg.alert_cause[31].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[31].q ),
+ .q (reg2hw.alert_cause[31].q),
// to register interface (read)
.qs (alert_cause_31_qs)
@@ -5409,8 +5409,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_32_we),
@@ -5418,11 +5418,11 @@
// from internal hardware
.de (hw2reg.alert_cause[32].de),
- .d (hw2reg.alert_cause[32].d ),
+ .d (hw2reg.alert_cause[32].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[32].q ),
+ .q (reg2hw.alert_cause[32].q),
// to register interface (read)
.qs (alert_cause_32_qs)
@@ -5436,8 +5436,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_33_we),
@@ -5445,11 +5445,11 @@
// from internal hardware
.de (hw2reg.alert_cause[33].de),
- .d (hw2reg.alert_cause[33].d ),
+ .d (hw2reg.alert_cause[33].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[33].q ),
+ .q (reg2hw.alert_cause[33].q),
// to register interface (read)
.qs (alert_cause_33_qs)
@@ -5463,8 +5463,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_34_we),
@@ -5472,11 +5472,11 @@
// from internal hardware
.de (hw2reg.alert_cause[34].de),
- .d (hw2reg.alert_cause[34].d ),
+ .d (hw2reg.alert_cause[34].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[34].q ),
+ .q (reg2hw.alert_cause[34].q),
// to register interface (read)
.qs (alert_cause_34_qs)
@@ -5490,8 +5490,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_35_we),
@@ -5499,11 +5499,11 @@
// from internal hardware
.de (hw2reg.alert_cause[35].de),
- .d (hw2reg.alert_cause[35].d ),
+ .d (hw2reg.alert_cause[35].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[35].q ),
+ .q (reg2hw.alert_cause[35].q),
// to register interface (read)
.qs (alert_cause_35_qs)
@@ -5517,8 +5517,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_36_we),
@@ -5526,11 +5526,11 @@
// from internal hardware
.de (hw2reg.alert_cause[36].de),
- .d (hw2reg.alert_cause[36].d ),
+ .d (hw2reg.alert_cause[36].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[36].q ),
+ .q (reg2hw.alert_cause[36].q),
// to register interface (read)
.qs (alert_cause_36_qs)
@@ -5544,8 +5544,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_37_we),
@@ -5553,11 +5553,11 @@
// from internal hardware
.de (hw2reg.alert_cause[37].de),
- .d (hw2reg.alert_cause[37].d ),
+ .d (hw2reg.alert_cause[37].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[37].q ),
+ .q (reg2hw.alert_cause[37].q),
// to register interface (read)
.qs (alert_cause_37_qs)
@@ -5571,8 +5571,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_cause_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_cause_38_we),
@@ -5580,11 +5580,11 @@
// from internal hardware
.de (hw2reg.alert_cause[38].de),
- .d (hw2reg.alert_cause[38].d ),
+ .d (hw2reg.alert_cause[38].d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_cause[38].q ),
+ .q (reg2hw.alert_cause[38].q),
// to register interface (read)
.qs (alert_cause_38_qs)
@@ -5600,8 +5600,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_0_we),
@@ -5609,7 +5609,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5627,8 +5627,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_1_we),
@@ -5636,7 +5636,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5654,8 +5654,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_2_we),
@@ -5663,7 +5663,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5681,8 +5681,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_3_we),
@@ -5690,7 +5690,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5708,8 +5708,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_4_we),
@@ -5717,7 +5717,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5735,8 +5735,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_5_we),
@@ -5744,7 +5744,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5762,8 +5762,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_6_we),
@@ -5771,7 +5771,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5789,8 +5789,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_7_we),
@@ -5798,7 +5798,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5816,8 +5816,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_8_we),
@@ -5825,7 +5825,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5843,8 +5843,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_9_we),
@@ -5852,7 +5852,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5870,8 +5870,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_10_we),
@@ -5879,7 +5879,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5897,8 +5897,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_11_we),
@@ -5906,7 +5906,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5924,8 +5924,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_12_we),
@@ -5933,7 +5933,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5951,8 +5951,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_13_we),
@@ -5960,7 +5960,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5978,8 +5978,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_14_we),
@@ -5987,7 +5987,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6005,8 +6005,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_15_we),
@@ -6014,7 +6014,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6032,8 +6032,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_16_we),
@@ -6041,7 +6041,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6059,8 +6059,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_17_we),
@@ -6068,7 +6068,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6086,8 +6086,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_18_we),
@@ -6095,7 +6095,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6113,8 +6113,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_19_we),
@@ -6122,7 +6122,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6140,8 +6140,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_20_we),
@@ -6149,7 +6149,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6167,8 +6167,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_21_we),
@@ -6176,7 +6176,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6194,8 +6194,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_22_we),
@@ -6203,7 +6203,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6221,8 +6221,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_23_we),
@@ -6230,7 +6230,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6248,8 +6248,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_24_we),
@@ -6257,7 +6257,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6275,8 +6275,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_25_we),
@@ -6284,7 +6284,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6302,8 +6302,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_26_we),
@@ -6311,7 +6311,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6329,8 +6329,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_27_we),
@@ -6338,7 +6338,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6356,8 +6356,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_28_we),
@@ -6365,7 +6365,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6383,8 +6383,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_29_we),
@@ -6392,7 +6392,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6410,8 +6410,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_30_we),
@@ -6419,7 +6419,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6437,8 +6437,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_31_we),
@@ -6446,7 +6446,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6464,8 +6464,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_32_we),
@@ -6473,7 +6473,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6491,8 +6491,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_33_we),
@@ -6500,7 +6500,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6518,8 +6518,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_34_we),
@@ -6527,7 +6527,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6545,8 +6545,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_35_we),
@@ -6554,7 +6554,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6572,8 +6572,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_36_we),
@@ -6581,7 +6581,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6599,8 +6599,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_37_we),
@@ -6608,7 +6608,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6626,8 +6626,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_loc_alert_regwen_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_regwen_38_we),
@@ -6635,7 +6635,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6655,20 +6655,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_loc_alert_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_en_0_we & loc_alert_regwen_0_qs),
.wd (loc_alert_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_en[0].q ),
+ .q (reg2hw.loc_alert_en[0].q),
// to register interface (read)
.qs (loc_alert_en_0_qs)
@@ -6682,20 +6682,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_loc_alert_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_en_1_we & loc_alert_regwen_1_qs),
.wd (loc_alert_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_en[1].q ),
+ .q (reg2hw.loc_alert_en[1].q),
// to register interface (read)
.qs (loc_alert_en_1_qs)
@@ -6709,20 +6709,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_loc_alert_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_en_2_we & loc_alert_regwen_2_qs),
.wd (loc_alert_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_en[2].q ),
+ .q (reg2hw.loc_alert_en[2].q),
// to register interface (read)
.qs (loc_alert_en_2_qs)
@@ -6736,20 +6736,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_loc_alert_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_en_3_we & loc_alert_regwen_3_qs),
.wd (loc_alert_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_en[3].q ),
+ .q (reg2hw.loc_alert_en[3].q),
// to register interface (read)
.qs (loc_alert_en_3_qs)
@@ -6765,20 +6765,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_loc_alert_class_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_class_0_we & loc_alert_regwen_0_qs),
.wd (loc_alert_class_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_class[0].q ),
+ .q (reg2hw.loc_alert_class[0].q),
// to register interface (read)
.qs (loc_alert_class_0_qs)
@@ -6792,20 +6792,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_loc_alert_class_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_class_1_we & loc_alert_regwen_1_qs),
.wd (loc_alert_class_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_class[1].q ),
+ .q (reg2hw.loc_alert_class[1].q),
// to register interface (read)
.qs (loc_alert_class_1_qs)
@@ -6819,20 +6819,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_loc_alert_class_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_class_2_we & loc_alert_regwen_2_qs),
.wd (loc_alert_class_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_class[2].q ),
+ .q (reg2hw.loc_alert_class[2].q),
// to register interface (read)
.qs (loc_alert_class_2_qs)
@@ -6846,20 +6846,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_loc_alert_class_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (loc_alert_class_3_we & loc_alert_regwen_3_qs),
.wd (loc_alert_class_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_class[3].q ),
+ .q (reg2hw.loc_alert_class[3].q),
// to register interface (read)
.qs (loc_alert_class_3_qs)
@@ -6875,8 +6875,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_loc_alert_cause_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_cause_0_we),
@@ -6884,11 +6884,11 @@
// from internal hardware
.de (hw2reg.loc_alert_cause[0].de),
- .d (hw2reg.loc_alert_cause[0].d ),
+ .d (hw2reg.loc_alert_cause[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_cause[0].q ),
+ .q (reg2hw.loc_alert_cause[0].q),
// to register interface (read)
.qs (loc_alert_cause_0_qs)
@@ -6902,8 +6902,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_loc_alert_cause_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_cause_1_we),
@@ -6911,11 +6911,11 @@
// from internal hardware
.de (hw2reg.loc_alert_cause[1].de),
- .d (hw2reg.loc_alert_cause[1].d ),
+ .d (hw2reg.loc_alert_cause[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_cause[1].q ),
+ .q (reg2hw.loc_alert_cause[1].q),
// to register interface (read)
.qs (loc_alert_cause_1_qs)
@@ -6929,8 +6929,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_loc_alert_cause_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_cause_2_we),
@@ -6938,11 +6938,11 @@
// from internal hardware
.de (hw2reg.loc_alert_cause[2].de),
- .d (hw2reg.loc_alert_cause[2].d ),
+ .d (hw2reg.loc_alert_cause[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_cause[2].q ),
+ .q (reg2hw.loc_alert_cause[2].q),
// to register interface (read)
.qs (loc_alert_cause_2_qs)
@@ -6956,8 +6956,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_loc_alert_cause_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (loc_alert_cause_3_we),
@@ -6965,11 +6965,11 @@
// from internal hardware
.de (hw2reg.loc_alert_cause[3].de),
- .d (hw2reg.loc_alert_cause[3].d ),
+ .d (hw2reg.loc_alert_cause[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.loc_alert_cause[3].q ),
+ .q (reg2hw.loc_alert_cause[3].q),
// to register interface (read)
.qs (loc_alert_cause_3_qs)
@@ -6983,8 +6983,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classa_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classa_regwen_we),
@@ -6992,7 +6992,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7011,20 +7011,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classa_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_we & classa_regwen_qs),
.wd (classa_ctrl_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en.q ),
+ .q (reg2hw.classa_ctrl.en.q),
// to register interface (read)
.qs (classa_ctrl_en_qs)
@@ -7037,20 +7037,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classa_ctrl_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_lock_we & classa_regwen_qs),
.wd (classa_ctrl_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.lock.q ),
+ .q (reg2hw.classa_ctrl.lock.q),
// to register interface (read)
.qs (classa_ctrl_lock_qs)
@@ -7063,20 +7063,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classa_ctrl_en_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_e0_we & classa_regwen_qs),
.wd (classa_ctrl_en_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en_e0.q ),
+ .q (reg2hw.classa_ctrl.en_e0.q),
// to register interface (read)
.qs (classa_ctrl_en_e0_qs)
@@ -7089,20 +7089,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classa_ctrl_en_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_e1_we & classa_regwen_qs),
.wd (classa_ctrl_en_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en_e1.q ),
+ .q (reg2hw.classa_ctrl.en_e1.q),
// to register interface (read)
.qs (classa_ctrl_en_e1_qs)
@@ -7115,20 +7115,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classa_ctrl_en_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_e2_we & classa_regwen_qs),
.wd (classa_ctrl_en_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en_e2.q ),
+ .q (reg2hw.classa_ctrl.en_e2.q),
// to register interface (read)
.qs (classa_ctrl_en_e2_qs)
@@ -7141,20 +7141,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classa_ctrl_en_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_en_e3_we & classa_regwen_qs),
.wd (classa_ctrl_en_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.en_e3.q ),
+ .q (reg2hw.classa_ctrl.en_e3.q),
// to register interface (read)
.qs (classa_ctrl_en_e3_qs)
@@ -7167,20 +7167,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_classa_ctrl_map_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_map_e0_we & classa_regwen_qs),
.wd (classa_ctrl_map_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.map_e0.q ),
+ .q (reg2hw.classa_ctrl.map_e0.q),
// to register interface (read)
.qs (classa_ctrl_map_e0_qs)
@@ -7193,20 +7193,20 @@
.SWACCESS("RW"),
.RESVAL (2'h1)
) u_classa_ctrl_map_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_map_e1_we & classa_regwen_qs),
.wd (classa_ctrl_map_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.map_e1.q ),
+ .q (reg2hw.classa_ctrl.map_e1.q),
// to register interface (read)
.qs (classa_ctrl_map_e1_qs)
@@ -7219,20 +7219,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_classa_ctrl_map_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_map_e2_we & classa_regwen_qs),
.wd (classa_ctrl_map_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.map_e2.q ),
+ .q (reg2hw.classa_ctrl.map_e2.q),
// to register interface (read)
.qs (classa_ctrl_map_e2_qs)
@@ -7245,20 +7245,20 @@
.SWACCESS("RW"),
.RESVAL (2'h3)
) u_classa_ctrl_map_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_ctrl_map_e3_we & classa_regwen_qs),
.wd (classa_ctrl_map_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_ctrl.map_e3.q ),
+ .q (reg2hw.classa_ctrl.map_e3.q),
// to register interface (read)
.qs (classa_ctrl_map_e3_qs)
@@ -7272,8 +7272,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classa_clr_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classa_clr_regwen_we),
@@ -7281,7 +7281,7 @@
// from internal hardware
.de (hw2reg.classa_clr_regwen.de),
- .d (hw2reg.classa_clr_regwen.d ),
+ .d (hw2reg.classa_clr_regwen.d),
// to internal hardware
.qe (),
@@ -7299,21 +7299,22 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_classa_clr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_clr_we & classa_clr_regwen_qs),
.wd (classa_clr_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.classa_clr.qe),
- .q (reg2hw.classa_clr.q ),
+ .q (reg2hw.classa_clr.q),
+ // to register interface (read)
.qs ()
);
@@ -7341,20 +7342,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_classa_accum_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_accum_thresh_we & classa_regwen_qs),
.wd (classa_accum_thresh_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_accum_thresh.q ),
+ .q (reg2hw.classa_accum_thresh.q),
// to register interface (read)
.qs (classa_accum_thresh_qs)
@@ -7368,20 +7369,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_timeout_cyc_we & classa_regwen_qs),
.wd (classa_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_timeout_cyc.q ),
+ .q (reg2hw.classa_timeout_cyc.q),
// to register interface (read)
.qs (classa_timeout_cyc_qs)
@@ -7395,20 +7396,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_phase0_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_phase0_cyc_we & classa_regwen_qs),
.wd (classa_phase0_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_phase0_cyc.q ),
+ .q (reg2hw.classa_phase0_cyc.q),
// to register interface (read)
.qs (classa_phase0_cyc_qs)
@@ -7422,20 +7423,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_phase1_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_phase1_cyc_we & classa_regwen_qs),
.wd (classa_phase1_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_phase1_cyc.q ),
+ .q (reg2hw.classa_phase1_cyc.q),
// to register interface (read)
.qs (classa_phase1_cyc_qs)
@@ -7449,20 +7450,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_phase2_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_phase2_cyc_we & classa_regwen_qs),
.wd (classa_phase2_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_phase2_cyc.q ),
+ .q (reg2hw.classa_phase2_cyc.q),
// to register interface (read)
.qs (classa_phase2_cyc_qs)
@@ -7476,20 +7477,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classa_phase3_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classa_phase3_cyc_we & classa_regwen_qs),
.wd (classa_phase3_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classa_phase3_cyc.q ),
+ .q (reg2hw.classa_phase3_cyc.q),
// to register interface (read)
.qs (classa_phase3_cyc_qs)
@@ -7535,8 +7536,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classb_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classb_regwen_we),
@@ -7544,7 +7545,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7563,20 +7564,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classb_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_we & classb_regwen_qs),
.wd (classb_ctrl_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en.q ),
+ .q (reg2hw.classb_ctrl.en.q),
// to register interface (read)
.qs (classb_ctrl_en_qs)
@@ -7589,20 +7590,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classb_ctrl_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_lock_we & classb_regwen_qs),
.wd (classb_ctrl_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.lock.q ),
+ .q (reg2hw.classb_ctrl.lock.q),
// to register interface (read)
.qs (classb_ctrl_lock_qs)
@@ -7615,20 +7616,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classb_ctrl_en_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_e0_we & classb_regwen_qs),
.wd (classb_ctrl_en_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en_e0.q ),
+ .q (reg2hw.classb_ctrl.en_e0.q),
// to register interface (read)
.qs (classb_ctrl_en_e0_qs)
@@ -7641,20 +7642,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classb_ctrl_en_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_e1_we & classb_regwen_qs),
.wd (classb_ctrl_en_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en_e1.q ),
+ .q (reg2hw.classb_ctrl.en_e1.q),
// to register interface (read)
.qs (classb_ctrl_en_e1_qs)
@@ -7667,20 +7668,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classb_ctrl_en_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_e2_we & classb_regwen_qs),
.wd (classb_ctrl_en_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en_e2.q ),
+ .q (reg2hw.classb_ctrl.en_e2.q),
// to register interface (read)
.qs (classb_ctrl_en_e2_qs)
@@ -7693,20 +7694,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classb_ctrl_en_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_en_e3_we & classb_regwen_qs),
.wd (classb_ctrl_en_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.en_e3.q ),
+ .q (reg2hw.classb_ctrl.en_e3.q),
// to register interface (read)
.qs (classb_ctrl_en_e3_qs)
@@ -7719,20 +7720,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_classb_ctrl_map_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_map_e0_we & classb_regwen_qs),
.wd (classb_ctrl_map_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.map_e0.q ),
+ .q (reg2hw.classb_ctrl.map_e0.q),
// to register interface (read)
.qs (classb_ctrl_map_e0_qs)
@@ -7745,20 +7746,20 @@
.SWACCESS("RW"),
.RESVAL (2'h1)
) u_classb_ctrl_map_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_map_e1_we & classb_regwen_qs),
.wd (classb_ctrl_map_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.map_e1.q ),
+ .q (reg2hw.classb_ctrl.map_e1.q),
// to register interface (read)
.qs (classb_ctrl_map_e1_qs)
@@ -7771,20 +7772,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_classb_ctrl_map_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_map_e2_we & classb_regwen_qs),
.wd (classb_ctrl_map_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.map_e2.q ),
+ .q (reg2hw.classb_ctrl.map_e2.q),
// to register interface (read)
.qs (classb_ctrl_map_e2_qs)
@@ -7797,20 +7798,20 @@
.SWACCESS("RW"),
.RESVAL (2'h3)
) u_classb_ctrl_map_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_ctrl_map_e3_we & classb_regwen_qs),
.wd (classb_ctrl_map_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_ctrl.map_e3.q ),
+ .q (reg2hw.classb_ctrl.map_e3.q),
// to register interface (read)
.qs (classb_ctrl_map_e3_qs)
@@ -7824,8 +7825,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classb_clr_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classb_clr_regwen_we),
@@ -7833,7 +7834,7 @@
// from internal hardware
.de (hw2reg.classb_clr_regwen.de),
- .d (hw2reg.classb_clr_regwen.d ),
+ .d (hw2reg.classb_clr_regwen.d),
// to internal hardware
.qe (),
@@ -7851,21 +7852,22 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_classb_clr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_clr_we & classb_clr_regwen_qs),
.wd (classb_clr_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.classb_clr.qe),
- .q (reg2hw.classb_clr.q ),
+ .q (reg2hw.classb_clr.q),
+ // to register interface (read)
.qs ()
);
@@ -7893,20 +7895,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_classb_accum_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_accum_thresh_we & classb_regwen_qs),
.wd (classb_accum_thresh_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_accum_thresh.q ),
+ .q (reg2hw.classb_accum_thresh.q),
// to register interface (read)
.qs (classb_accum_thresh_qs)
@@ -7920,20 +7922,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_timeout_cyc_we & classb_regwen_qs),
.wd (classb_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_timeout_cyc.q ),
+ .q (reg2hw.classb_timeout_cyc.q),
// to register interface (read)
.qs (classb_timeout_cyc_qs)
@@ -7947,20 +7949,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_phase0_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_phase0_cyc_we & classb_regwen_qs),
.wd (classb_phase0_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_phase0_cyc.q ),
+ .q (reg2hw.classb_phase0_cyc.q),
// to register interface (read)
.qs (classb_phase0_cyc_qs)
@@ -7974,20 +7976,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_phase1_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_phase1_cyc_we & classb_regwen_qs),
.wd (classb_phase1_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_phase1_cyc.q ),
+ .q (reg2hw.classb_phase1_cyc.q),
// to register interface (read)
.qs (classb_phase1_cyc_qs)
@@ -8001,20 +8003,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_phase2_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_phase2_cyc_we & classb_regwen_qs),
.wd (classb_phase2_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_phase2_cyc.q ),
+ .q (reg2hw.classb_phase2_cyc.q),
// to register interface (read)
.qs (classb_phase2_cyc_qs)
@@ -8028,20 +8030,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classb_phase3_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classb_phase3_cyc_we & classb_regwen_qs),
.wd (classb_phase3_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classb_phase3_cyc.q ),
+ .q (reg2hw.classb_phase3_cyc.q),
// to register interface (read)
.qs (classb_phase3_cyc_qs)
@@ -8087,8 +8089,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classc_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classc_regwen_we),
@@ -8096,7 +8098,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8115,20 +8117,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classc_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_we & classc_regwen_qs),
.wd (classc_ctrl_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en.q ),
+ .q (reg2hw.classc_ctrl.en.q),
// to register interface (read)
.qs (classc_ctrl_en_qs)
@@ -8141,20 +8143,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classc_ctrl_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_lock_we & classc_regwen_qs),
.wd (classc_ctrl_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.lock.q ),
+ .q (reg2hw.classc_ctrl.lock.q),
// to register interface (read)
.qs (classc_ctrl_lock_qs)
@@ -8167,20 +8169,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classc_ctrl_en_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_e0_we & classc_regwen_qs),
.wd (classc_ctrl_en_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en_e0.q ),
+ .q (reg2hw.classc_ctrl.en_e0.q),
// to register interface (read)
.qs (classc_ctrl_en_e0_qs)
@@ -8193,20 +8195,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classc_ctrl_en_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_e1_we & classc_regwen_qs),
.wd (classc_ctrl_en_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en_e1.q ),
+ .q (reg2hw.classc_ctrl.en_e1.q),
// to register interface (read)
.qs (classc_ctrl_en_e1_qs)
@@ -8219,20 +8221,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classc_ctrl_en_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_e2_we & classc_regwen_qs),
.wd (classc_ctrl_en_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en_e2.q ),
+ .q (reg2hw.classc_ctrl.en_e2.q),
// to register interface (read)
.qs (classc_ctrl_en_e2_qs)
@@ -8245,20 +8247,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classc_ctrl_en_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_en_e3_we & classc_regwen_qs),
.wd (classc_ctrl_en_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.en_e3.q ),
+ .q (reg2hw.classc_ctrl.en_e3.q),
// to register interface (read)
.qs (classc_ctrl_en_e3_qs)
@@ -8271,20 +8273,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_classc_ctrl_map_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_map_e0_we & classc_regwen_qs),
.wd (classc_ctrl_map_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.map_e0.q ),
+ .q (reg2hw.classc_ctrl.map_e0.q),
// to register interface (read)
.qs (classc_ctrl_map_e0_qs)
@@ -8297,20 +8299,20 @@
.SWACCESS("RW"),
.RESVAL (2'h1)
) u_classc_ctrl_map_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_map_e1_we & classc_regwen_qs),
.wd (classc_ctrl_map_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.map_e1.q ),
+ .q (reg2hw.classc_ctrl.map_e1.q),
// to register interface (read)
.qs (classc_ctrl_map_e1_qs)
@@ -8323,20 +8325,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_classc_ctrl_map_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_map_e2_we & classc_regwen_qs),
.wd (classc_ctrl_map_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.map_e2.q ),
+ .q (reg2hw.classc_ctrl.map_e2.q),
// to register interface (read)
.qs (classc_ctrl_map_e2_qs)
@@ -8349,20 +8351,20 @@
.SWACCESS("RW"),
.RESVAL (2'h3)
) u_classc_ctrl_map_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_ctrl_map_e3_we & classc_regwen_qs),
.wd (classc_ctrl_map_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_ctrl.map_e3.q ),
+ .q (reg2hw.classc_ctrl.map_e3.q),
// to register interface (read)
.qs (classc_ctrl_map_e3_qs)
@@ -8376,8 +8378,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classc_clr_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classc_clr_regwen_we),
@@ -8385,7 +8387,7 @@
// from internal hardware
.de (hw2reg.classc_clr_regwen.de),
- .d (hw2reg.classc_clr_regwen.d ),
+ .d (hw2reg.classc_clr_regwen.d),
// to internal hardware
.qe (),
@@ -8403,21 +8405,22 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_classc_clr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_clr_we & classc_clr_regwen_qs),
.wd (classc_clr_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.classc_clr.qe),
- .q (reg2hw.classc_clr.q ),
+ .q (reg2hw.classc_clr.q),
+ // to register interface (read)
.qs ()
);
@@ -8445,20 +8448,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_classc_accum_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_accum_thresh_we & classc_regwen_qs),
.wd (classc_accum_thresh_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_accum_thresh.q ),
+ .q (reg2hw.classc_accum_thresh.q),
// to register interface (read)
.qs (classc_accum_thresh_qs)
@@ -8472,20 +8475,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_timeout_cyc_we & classc_regwen_qs),
.wd (classc_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_timeout_cyc.q ),
+ .q (reg2hw.classc_timeout_cyc.q),
// to register interface (read)
.qs (classc_timeout_cyc_qs)
@@ -8499,20 +8502,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_phase0_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_phase0_cyc_we & classc_regwen_qs),
.wd (classc_phase0_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_phase0_cyc.q ),
+ .q (reg2hw.classc_phase0_cyc.q),
// to register interface (read)
.qs (classc_phase0_cyc_qs)
@@ -8526,20 +8529,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_phase1_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_phase1_cyc_we & classc_regwen_qs),
.wd (classc_phase1_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_phase1_cyc.q ),
+ .q (reg2hw.classc_phase1_cyc.q),
// to register interface (read)
.qs (classc_phase1_cyc_qs)
@@ -8553,20 +8556,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_phase2_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_phase2_cyc_we & classc_regwen_qs),
.wd (classc_phase2_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_phase2_cyc.q ),
+ .q (reg2hw.classc_phase2_cyc.q),
// to register interface (read)
.qs (classc_phase2_cyc_qs)
@@ -8580,20 +8583,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classc_phase3_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classc_phase3_cyc_we & classc_regwen_qs),
.wd (classc_phase3_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classc_phase3_cyc.q ),
+ .q (reg2hw.classc_phase3_cyc.q),
// to register interface (read)
.qs (classc_phase3_cyc_qs)
@@ -8639,8 +8642,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classd_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classd_regwen_we),
@@ -8648,7 +8651,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8667,20 +8670,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classd_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_we & classd_regwen_qs),
.wd (classd_ctrl_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en.q ),
+ .q (reg2hw.classd_ctrl.en.q),
// to register interface (read)
.qs (classd_ctrl_en_qs)
@@ -8693,20 +8696,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_classd_ctrl_lock (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_lock_we & classd_regwen_qs),
.wd (classd_ctrl_lock_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.lock.q ),
+ .q (reg2hw.classd_ctrl.lock.q),
// to register interface (read)
.qs (classd_ctrl_lock_qs)
@@ -8719,20 +8722,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classd_ctrl_en_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_e0_we & classd_regwen_qs),
.wd (classd_ctrl_en_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en_e0.q ),
+ .q (reg2hw.classd_ctrl.en_e0.q),
// to register interface (read)
.qs (classd_ctrl_en_e0_qs)
@@ -8745,20 +8748,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classd_ctrl_en_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_e1_we & classd_regwen_qs),
.wd (classd_ctrl_en_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en_e1.q ),
+ .q (reg2hw.classd_ctrl.en_e1.q),
// to register interface (read)
.qs (classd_ctrl_en_e1_qs)
@@ -8771,20 +8774,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classd_ctrl_en_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_e2_we & classd_regwen_qs),
.wd (classd_ctrl_en_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en_e2.q ),
+ .q (reg2hw.classd_ctrl.en_e2.q),
// to register interface (read)
.qs (classd_ctrl_en_e2_qs)
@@ -8797,20 +8800,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_classd_ctrl_en_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_en_e3_we & classd_regwen_qs),
.wd (classd_ctrl_en_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.en_e3.q ),
+ .q (reg2hw.classd_ctrl.en_e3.q),
// to register interface (read)
.qs (classd_ctrl_en_e3_qs)
@@ -8823,20 +8826,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_classd_ctrl_map_e0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_map_e0_we & classd_regwen_qs),
.wd (classd_ctrl_map_e0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.map_e0.q ),
+ .q (reg2hw.classd_ctrl.map_e0.q),
// to register interface (read)
.qs (classd_ctrl_map_e0_qs)
@@ -8849,20 +8852,20 @@
.SWACCESS("RW"),
.RESVAL (2'h1)
) u_classd_ctrl_map_e1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_map_e1_we & classd_regwen_qs),
.wd (classd_ctrl_map_e1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.map_e1.q ),
+ .q (reg2hw.classd_ctrl.map_e1.q),
// to register interface (read)
.qs (classd_ctrl_map_e1_qs)
@@ -8875,20 +8878,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_classd_ctrl_map_e2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_map_e2_we & classd_regwen_qs),
.wd (classd_ctrl_map_e2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.map_e2.q ),
+ .q (reg2hw.classd_ctrl.map_e2.q),
// to register interface (read)
.qs (classd_ctrl_map_e2_qs)
@@ -8901,20 +8904,20 @@
.SWACCESS("RW"),
.RESVAL (2'h3)
) u_classd_ctrl_map_e3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_ctrl_map_e3_we & classd_regwen_qs),
.wd (classd_ctrl_map_e3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_ctrl.map_e3.q ),
+ .q (reg2hw.classd_ctrl.map_e3.q),
// to register interface (read)
.qs (classd_ctrl_map_e3_qs)
@@ -8928,8 +8931,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_classd_clr_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (classd_clr_regwen_we),
@@ -8937,7 +8940,7 @@
// from internal hardware
.de (hw2reg.classd_clr_regwen.de),
- .d (hw2reg.classd_clr_regwen.d ),
+ .d (hw2reg.classd_clr_regwen.d),
// to internal hardware
.qe (),
@@ -8955,21 +8958,22 @@
.SWACCESS("WO"),
.RESVAL (1'h0)
) u_classd_clr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_clr_we & classd_clr_regwen_qs),
.wd (classd_clr_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (reg2hw.classd_clr.qe),
- .q (reg2hw.classd_clr.q ),
+ .q (reg2hw.classd_clr.q),
+ // to register interface (read)
.qs ()
);
@@ -8997,20 +9001,20 @@
.SWACCESS("RW"),
.RESVAL (16'h0)
) u_classd_accum_thresh (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_accum_thresh_we & classd_regwen_qs),
.wd (classd_accum_thresh_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_accum_thresh.q ),
+ .q (reg2hw.classd_accum_thresh.q),
// to register interface (read)
.qs (classd_accum_thresh_qs)
@@ -9024,20 +9028,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_timeout_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_timeout_cyc_we & classd_regwen_qs),
.wd (classd_timeout_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_timeout_cyc.q ),
+ .q (reg2hw.classd_timeout_cyc.q),
// to register interface (read)
.qs (classd_timeout_cyc_qs)
@@ -9051,20 +9055,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_phase0_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_phase0_cyc_we & classd_regwen_qs),
.wd (classd_phase0_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_phase0_cyc.q ),
+ .q (reg2hw.classd_phase0_cyc.q),
// to register interface (read)
.qs (classd_phase0_cyc_qs)
@@ -9078,20 +9082,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_phase1_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_phase1_cyc_we & classd_regwen_qs),
.wd (classd_phase1_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_phase1_cyc.q ),
+ .q (reg2hw.classd_phase1_cyc.q),
// to register interface (read)
.qs (classd_phase1_cyc_qs)
@@ -9105,20 +9109,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_phase2_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_phase2_cyc_we & classd_regwen_qs),
.wd (classd_phase2_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_phase2_cyc.q ),
+ .q (reg2hw.classd_phase2_cyc.q),
// to register interface (read)
.qs (classd_phase2_cyc_qs)
@@ -9132,20 +9136,20 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_classd_phase3_cyc (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (classd_phase3_cyc_we & classd_regwen_qs),
.wd (classd_phase3_cyc_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.classd_phase3_cyc.q ),
+ .q (reg2hw.classd_phase3_cyc.q),
// to register interface (read)
.qs (classd_phase3_cyc_qs)
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv b/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
index a291b15..3402780 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
@@ -294,19 +294,20 @@
.SWACCESS("RO"),
.RESVAL (8'h1)
) u_revid (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.revid.q ),
+ .q (reg2hw.revid.q),
// to register interface (read)
.qs (revid_qs)
@@ -322,8 +323,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_0_we),
@@ -331,11 +332,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[0].q ),
+ .q (reg2hw.rega[0].q),
// to register interface (read)
.qs (rega_0_qs)
@@ -349,8 +350,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_1_we),
@@ -358,11 +359,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[1].q ),
+ .q (reg2hw.rega[1].q),
// to register interface (read)
.qs (rega_1_qs)
@@ -376,8 +377,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_2_we),
@@ -385,11 +386,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[2].q ),
+ .q (reg2hw.rega[2].q),
// to register interface (read)
.qs (rega_2_qs)
@@ -403,8 +404,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_3_we),
@@ -412,11 +413,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[3].q ),
+ .q (reg2hw.rega[3].q),
// to register interface (read)
.qs (rega_3_qs)
@@ -430,8 +431,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_4_we),
@@ -439,11 +440,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[4].q ),
+ .q (reg2hw.rega[4].q),
// to register interface (read)
.qs (rega_4_qs)
@@ -457,8 +458,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_5_we),
@@ -466,11 +467,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[5].q ),
+ .q (reg2hw.rega[5].q),
// to register interface (read)
.qs (rega_5_qs)
@@ -484,8 +485,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_6_we),
@@ -493,11 +494,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[6].q ),
+ .q (reg2hw.rega[6].q),
// to register interface (read)
.qs (rega_6_qs)
@@ -511,8 +512,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_7_we),
@@ -520,11 +521,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[7].q ),
+ .q (reg2hw.rega[7].q),
// to register interface (read)
.qs (rega_7_qs)
@@ -538,8 +539,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_8_we),
@@ -547,11 +548,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[8].q ),
+ .q (reg2hw.rega[8].q),
// to register interface (read)
.qs (rega_8_qs)
@@ -565,8 +566,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_9_we),
@@ -574,11 +575,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[9].q ),
+ .q (reg2hw.rega[9].q),
// to register interface (read)
.qs (rega_9_qs)
@@ -592,8 +593,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_10_we),
@@ -601,11 +602,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[10].q ),
+ .q (reg2hw.rega[10].q),
// to register interface (read)
.qs (rega_10_qs)
@@ -619,8 +620,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_11_we),
@@ -628,11 +629,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[11].q ),
+ .q (reg2hw.rega[11].q),
// to register interface (read)
.qs (rega_11_qs)
@@ -646,8 +647,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_12_we),
@@ -655,11 +656,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[12].q ),
+ .q (reg2hw.rega[12].q),
// to register interface (read)
.qs (rega_12_qs)
@@ -673,8 +674,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_13_we),
@@ -682,11 +683,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[13].q ),
+ .q (reg2hw.rega[13].q),
// to register interface (read)
.qs (rega_13_qs)
@@ -700,8 +701,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_14_we),
@@ -709,11 +710,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[14].q ),
+ .q (reg2hw.rega[14].q),
// to register interface (read)
.qs (rega_14_qs)
@@ -727,8 +728,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_15_we),
@@ -736,11 +737,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[15].q ),
+ .q (reg2hw.rega[15].q),
// to register interface (read)
.qs (rega_15_qs)
@@ -754,8 +755,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_16_we),
@@ -763,11 +764,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[16].q ),
+ .q (reg2hw.rega[16].q),
// to register interface (read)
.qs (rega_16_qs)
@@ -781,8 +782,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_17_we),
@@ -790,11 +791,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[17].q ),
+ .q (reg2hw.rega[17].q),
// to register interface (read)
.qs (rega_17_qs)
@@ -808,8 +809,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_18_we),
@@ -817,11 +818,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[18].q ),
+ .q (reg2hw.rega[18].q),
// to register interface (read)
.qs (rega_18_qs)
@@ -835,8 +836,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_19_we),
@@ -844,11 +845,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[19].q ),
+ .q (reg2hw.rega[19].q),
// to register interface (read)
.qs (rega_19_qs)
@@ -862,8 +863,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_20_we),
@@ -871,11 +872,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[20].q ),
+ .q (reg2hw.rega[20].q),
// to register interface (read)
.qs (rega_20_qs)
@@ -889,8 +890,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_21_we),
@@ -898,11 +899,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[21].q ),
+ .q (reg2hw.rega[21].q),
// to register interface (read)
.qs (rega_21_qs)
@@ -916,8 +917,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_22_we),
@@ -925,11 +926,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[22].q ),
+ .q (reg2hw.rega[22].q),
// to register interface (read)
.qs (rega_22_qs)
@@ -943,8 +944,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_23_we),
@@ -952,11 +953,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[23].q ),
+ .q (reg2hw.rega[23].q),
// to register interface (read)
.qs (rega_23_qs)
@@ -970,8 +971,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_24_we),
@@ -979,11 +980,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[24].q ),
+ .q (reg2hw.rega[24].q),
// to register interface (read)
.qs (rega_24_qs)
@@ -997,8 +998,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_25_we),
@@ -1006,11 +1007,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[25].q ),
+ .q (reg2hw.rega[25].q),
// to register interface (read)
.qs (rega_25_qs)
@@ -1024,8 +1025,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_26_we),
@@ -1033,11 +1034,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[26].q ),
+ .q (reg2hw.rega[26].q),
// to register interface (read)
.qs (rega_26_qs)
@@ -1051,8 +1052,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_27_we),
@@ -1060,11 +1061,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[27].q ),
+ .q (reg2hw.rega[27].q),
// to register interface (read)
.qs (rega_27_qs)
@@ -1078,8 +1079,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_28_we),
@@ -1087,11 +1088,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[28].q ),
+ .q (reg2hw.rega[28].q),
// to register interface (read)
.qs (rega_28_qs)
@@ -1105,8 +1106,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_29_we),
@@ -1114,11 +1115,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[29].q ),
+ .q (reg2hw.rega[29].q),
// to register interface (read)
.qs (rega_29_qs)
@@ -1132,8 +1133,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_30_we),
@@ -1141,11 +1142,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[30].q ),
+ .q (reg2hw.rega[30].q),
// to register interface (read)
.qs (rega_30_qs)
@@ -1159,8 +1160,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_31_we),
@@ -1168,11 +1169,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[31].q ),
+ .q (reg2hw.rega[31].q),
// to register interface (read)
.qs (rega_31_qs)
@@ -1186,8 +1187,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_32_we),
@@ -1195,11 +1196,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[32].q ),
+ .q (reg2hw.rega[32].q),
// to register interface (read)
.qs (rega_32_qs)
@@ -1213,8 +1214,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_33_we),
@@ -1222,11 +1223,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[33].q ),
+ .q (reg2hw.rega[33].q),
// to register interface (read)
.qs (rega_33_qs)
@@ -1240,8 +1241,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_34_we),
@@ -1249,11 +1250,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[34].q ),
+ .q (reg2hw.rega[34].q),
// to register interface (read)
.qs (rega_34_qs)
@@ -1267,8 +1268,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_35_we),
@@ -1276,11 +1277,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[35].q ),
+ .q (reg2hw.rega[35].q),
// to register interface (read)
.qs (rega_35_qs)
@@ -1294,8 +1295,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_36_we),
@@ -1303,11 +1304,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[36].q ),
+ .q (reg2hw.rega[36].q),
// to register interface (read)
.qs (rega_36_qs)
@@ -1321,8 +1322,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_37_we),
@@ -1330,11 +1331,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[37].q ),
+ .q (reg2hw.rega[37].q),
// to register interface (read)
.qs (rega_37_qs)
@@ -1348,8 +1349,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_38_we),
@@ -1357,11 +1358,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[38].q ),
+ .q (reg2hw.rega[38].q),
// to register interface (read)
.qs (rega_38_qs)
@@ -1375,8 +1376,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_39_we),
@@ -1384,11 +1385,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[39].q ),
+ .q (reg2hw.rega[39].q),
// to register interface (read)
.qs (rega_39_qs)
@@ -1402,8 +1403,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_40_we),
@@ -1411,11 +1412,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[40].q ),
+ .q (reg2hw.rega[40].q),
// to register interface (read)
.qs (rega_40_qs)
@@ -1429,8 +1430,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_41_we),
@@ -1438,11 +1439,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[41].q ),
+ .q (reg2hw.rega[41].q),
// to register interface (read)
.qs (rega_41_qs)
@@ -1456,8 +1457,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_42_we),
@@ -1465,11 +1466,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[42].q ),
+ .q (reg2hw.rega[42].q),
// to register interface (read)
.qs (rega_42_qs)
@@ -1483,8 +1484,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_43_we),
@@ -1492,11 +1493,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[43].q ),
+ .q (reg2hw.rega[43].q),
// to register interface (read)
.qs (rega_43_qs)
@@ -1510,8 +1511,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_44_we),
@@ -1519,11 +1520,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[44].q ),
+ .q (reg2hw.rega[44].q),
// to register interface (read)
.qs (rega_44_qs)
@@ -1537,8 +1538,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_45_we),
@@ -1546,11 +1547,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[45].q ),
+ .q (reg2hw.rega[45].q),
// to register interface (read)
.qs (rega_45_qs)
@@ -1564,8 +1565,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_46_we),
@@ -1573,11 +1574,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[46].q ),
+ .q (reg2hw.rega[46].q),
// to register interface (read)
.qs (rega_46_qs)
@@ -1591,8 +1592,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_47 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_47_we),
@@ -1600,11 +1601,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[47].q ),
+ .q (reg2hw.rega[47].q),
// to register interface (read)
.qs (rega_47_qs)
@@ -1618,8 +1619,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_48 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_48_we),
@@ -1627,11 +1628,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[48].q ),
+ .q (reg2hw.rega[48].q),
// to register interface (read)
.qs (rega_48_qs)
@@ -1645,8 +1646,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_rega_49 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (rega_49_we),
@@ -1654,11 +1655,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.rega[49].q ),
+ .q (reg2hw.rega[49].q),
// to register interface (read)
.qs (rega_49_qs)
@@ -1674,8 +1675,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_0_we),
@@ -1683,11 +1684,11 @@
// from internal hardware
.de (hw2reg.regb[0].de),
- .d (hw2reg.regb[0].d ),
+ .d (hw2reg.regb[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[0].q ),
+ .q (reg2hw.regb[0].q),
// to register interface (read)
.qs (regb_0_qs)
@@ -1701,8 +1702,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_1_we),
@@ -1710,11 +1711,11 @@
// from internal hardware
.de (hw2reg.regb[1].de),
- .d (hw2reg.regb[1].d ),
+ .d (hw2reg.regb[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[1].q ),
+ .q (reg2hw.regb[1].q),
// to register interface (read)
.qs (regb_1_qs)
@@ -1728,8 +1729,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_2_we),
@@ -1737,11 +1738,11 @@
// from internal hardware
.de (hw2reg.regb[2].de),
- .d (hw2reg.regb[2].d ),
+ .d (hw2reg.regb[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[2].q ),
+ .q (reg2hw.regb[2].q),
// to register interface (read)
.qs (regb_2_qs)
@@ -1755,8 +1756,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_3_we),
@@ -1764,11 +1765,11 @@
// from internal hardware
.de (hw2reg.regb[3].de),
- .d (hw2reg.regb[3].d ),
+ .d (hw2reg.regb[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[3].q ),
+ .q (reg2hw.regb[3].q),
// to register interface (read)
.qs (regb_3_qs)
@@ -1782,8 +1783,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_4_we),
@@ -1791,11 +1792,11 @@
// from internal hardware
.de (hw2reg.regb[4].de),
- .d (hw2reg.regb[4].d ),
+ .d (hw2reg.regb[4].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[4].q ),
+ .q (reg2hw.regb[4].q),
// to register interface (read)
.qs (regb_4_qs)
@@ -1809,8 +1810,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_5_we),
@@ -1818,11 +1819,11 @@
// from internal hardware
.de (hw2reg.regb[5].de),
- .d (hw2reg.regb[5].d ),
+ .d (hw2reg.regb[5].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[5].q ),
+ .q (reg2hw.regb[5].q),
// to register interface (read)
.qs (regb_5_qs)
@@ -1836,8 +1837,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_6_we),
@@ -1845,11 +1846,11 @@
// from internal hardware
.de (hw2reg.regb[6].de),
- .d (hw2reg.regb[6].d ),
+ .d (hw2reg.regb[6].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[6].q ),
+ .q (reg2hw.regb[6].q),
// to register interface (read)
.qs (regb_6_qs)
@@ -1863,8 +1864,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_7_we),
@@ -1872,11 +1873,11 @@
// from internal hardware
.de (hw2reg.regb[7].de),
- .d (hw2reg.regb[7].d ),
+ .d (hw2reg.regb[7].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[7].q ),
+ .q (reg2hw.regb[7].q),
// to register interface (read)
.qs (regb_7_qs)
@@ -1890,8 +1891,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_8_we),
@@ -1899,11 +1900,11 @@
// from internal hardware
.de (hw2reg.regb[8].de),
- .d (hw2reg.regb[8].d ),
+ .d (hw2reg.regb[8].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[8].q ),
+ .q (reg2hw.regb[8].q),
// to register interface (read)
.qs (regb_8_qs)
@@ -1917,8 +1918,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_regb_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (regb_9_we),
@@ -1926,11 +1927,11 @@
// from internal hardware
.de (hw2reg.regb[9].de),
- .d (hw2reg.regb[9].d ),
+ .d (hw2reg.regb[9].d),
// to internal hardware
.qe (),
- .q (reg2hw.regb[9].q ),
+ .q (reg2hw.regb[9].q),
// to register interface (read)
.qs (regb_9_qs)
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
index f1cbd1b..42e2175 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
@@ -150,8 +150,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_extclk_sel_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (extclk_sel_regwen_we),
@@ -159,7 +159,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -177,20 +177,20 @@
.SWACCESS("RW"),
.RESVAL (4'h5)
) u_extclk_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (extclk_sel_we & extclk_sel_regwen_qs),
.wd (extclk_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.extclk_sel.q ),
+ .q (reg2hw.extclk_sel.q),
// to register interface (read)
.qs (extclk_sel_qs)
@@ -204,8 +204,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_jitter_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (jitter_enable_we),
@@ -213,11 +213,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.jitter_enable.q ),
+ .q (reg2hw.jitter_enable.q),
// to register interface (read)
.qs (jitter_enable_qs)
@@ -232,8 +232,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_enables_clk_io_div4_peri_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_enables_clk_io_div4_peri_en_we),
@@ -241,11 +241,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_enables.clk_io_div4_peri_en.q ),
+ .q (reg2hw.clk_enables.clk_io_div4_peri_en.q),
// to register interface (read)
.qs (clk_enables_clk_io_div4_peri_en_qs)
@@ -258,8 +258,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_enables_clk_io_div2_peri_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_enables_clk_io_div2_peri_en_we),
@@ -267,11 +267,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_enables.clk_io_div2_peri_en.q ),
+ .q (reg2hw.clk_enables.clk_io_div2_peri_en.q),
// to register interface (read)
.qs (clk_enables_clk_io_div2_peri_en_qs)
@@ -284,8 +284,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_enables_clk_io_peri_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_enables_clk_io_peri_en_we),
@@ -293,11 +293,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_enables.clk_io_peri_en.q ),
+ .q (reg2hw.clk_enables.clk_io_peri_en.q),
// to register interface (read)
.qs (clk_enables_clk_io_peri_en_qs)
@@ -310,8 +310,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_enables_clk_usb_peri_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_enables_clk_usb_peri_en_we),
@@ -319,11 +319,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_enables.clk_usb_peri_en.q ),
+ .q (reg2hw.clk_enables.clk_usb_peri_en.q),
// to register interface (read)
.qs (clk_enables_clk_usb_peri_en_qs)
@@ -338,8 +338,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_hints_clk_main_aes_hint (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_hints_clk_main_aes_hint_we),
@@ -347,11 +347,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_hints.clk_main_aes_hint.q ),
+ .q (reg2hw.clk_hints.clk_main_aes_hint.q),
// to register interface (read)
.qs (clk_hints_clk_main_aes_hint_qs)
@@ -364,8 +364,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_hints_clk_main_hmac_hint (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_hints_clk_main_hmac_hint_we),
@@ -373,11 +373,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_hints.clk_main_hmac_hint.q ),
+ .q (reg2hw.clk_hints.clk_main_hmac_hint.q),
// to register interface (read)
.qs (clk_hints_clk_main_hmac_hint_qs)
@@ -390,8 +390,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_hints_clk_main_kmac_hint (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_hints_clk_main_kmac_hint_we),
@@ -399,11 +399,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_hints.clk_main_kmac_hint.q ),
+ .q (reg2hw.clk_hints.clk_main_kmac_hint.q),
// to register interface (read)
.qs (clk_hints_clk_main_kmac_hint_qs)
@@ -416,8 +416,8 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_clk_hints_clk_main_otbn_hint (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (clk_hints_clk_main_otbn_hint_we),
@@ -425,11 +425,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.clk_hints.clk_main_otbn_hint.q ),
+ .q (reg2hw.clk_hints.clk_main_otbn_hint.q),
// to register interface (read)
.qs (clk_hints_clk_main_otbn_hint_qs)
@@ -444,15 +444,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_clk_hints_status_clk_main_aes_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.clk_hints_status.clk_main_aes_val.de),
- .d (hw2reg.clk_hints_status.clk_main_aes_val.d ),
+ .d (hw2reg.clk_hints_status.clk_main_aes_val.d),
// to internal hardware
.qe (),
@@ -469,15 +470,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_clk_hints_status_clk_main_hmac_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.clk_hints_status.clk_main_hmac_val.de),
- .d (hw2reg.clk_hints_status.clk_main_hmac_val.d ),
+ .d (hw2reg.clk_hints_status.clk_main_hmac_val.d),
// to internal hardware
.qe (),
@@ -494,15 +496,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_clk_hints_status_clk_main_kmac_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.clk_hints_status.clk_main_kmac_val.de),
- .d (hw2reg.clk_hints_status.clk_main_kmac_val.d ),
+ .d (hw2reg.clk_hints_status.clk_main_kmac_val.d),
// to internal hardware
.qe (),
@@ -519,15 +522,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_clk_hints_status_clk_main_otbn_val (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.clk_hints_status.clk_main_otbn_val.de),
- .d (hw2reg.clk_hints_status.clk_main_otbn_val.d ),
+ .d (hw2reg.clk_hints_status.clk_main_otbn_val.d),
// to internal hardware
.qe (),
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
index 333f380..ec67358 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_core_reg_top.sv
@@ -1231,8 +1231,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_prog_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_prog_empty_we),
@@ -1240,11 +1240,11 @@
// from internal hardware
.de (hw2reg.intr_state.prog_empty.de),
- .d (hw2reg.intr_state.prog_empty.d ),
+ .d (hw2reg.intr_state.prog_empty.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.prog_empty.q ),
+ .q (reg2hw.intr_state.prog_empty.q),
// to register interface (read)
.qs (intr_state_prog_empty_qs)
@@ -1257,8 +1257,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_prog_lvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_prog_lvl_we),
@@ -1266,11 +1266,11 @@
// from internal hardware
.de (hw2reg.intr_state.prog_lvl.de),
- .d (hw2reg.intr_state.prog_lvl.d ),
+ .d (hw2reg.intr_state.prog_lvl.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.prog_lvl.q ),
+ .q (reg2hw.intr_state.prog_lvl.q),
// to register interface (read)
.qs (intr_state_prog_lvl_qs)
@@ -1283,8 +1283,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rd_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rd_full_we),
@@ -1292,11 +1292,11 @@
// from internal hardware
.de (hw2reg.intr_state.rd_full.de),
- .d (hw2reg.intr_state.rd_full.d ),
+ .d (hw2reg.intr_state.rd_full.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rd_full.q ),
+ .q (reg2hw.intr_state.rd_full.q),
// to register interface (read)
.qs (intr_state_rd_full_qs)
@@ -1309,8 +1309,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_rd_lvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_rd_lvl_we),
@@ -1318,11 +1318,11 @@
// from internal hardware
.de (hw2reg.intr_state.rd_lvl.de),
- .d (hw2reg.intr_state.rd_lvl.d ),
+ .d (hw2reg.intr_state.rd_lvl.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rd_lvl.q ),
+ .q (reg2hw.intr_state.rd_lvl.q),
// to register interface (read)
.qs (intr_state_rd_lvl_qs)
@@ -1335,8 +1335,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_op_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_op_done_we),
@@ -1344,11 +1344,11 @@
// from internal hardware
.de (hw2reg.intr_state.op_done.de),
- .d (hw2reg.intr_state.op_done.d ),
+ .d (hw2reg.intr_state.op_done.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.op_done.q ),
+ .q (reg2hw.intr_state.op_done.q),
// to register interface (read)
.qs (intr_state_op_done_qs)
@@ -1361,8 +1361,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_err_we),
@@ -1370,11 +1370,11 @@
// from internal hardware
.de (hw2reg.intr_state.err.de),
- .d (hw2reg.intr_state.err.d ),
+ .d (hw2reg.intr_state.err.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.err.q ),
+ .q (reg2hw.intr_state.err.q),
// to register interface (read)
.qs (intr_state_err_qs)
@@ -1389,8 +1389,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_prog_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_prog_empty_we),
@@ -1398,11 +1398,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.prog_empty.q ),
+ .q (reg2hw.intr_enable.prog_empty.q),
// to register interface (read)
.qs (intr_enable_prog_empty_qs)
@@ -1415,8 +1415,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_prog_lvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_prog_lvl_we),
@@ -1424,11 +1424,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.prog_lvl.q ),
+ .q (reg2hw.intr_enable.prog_lvl.q),
// to register interface (read)
.qs (intr_enable_prog_lvl_qs)
@@ -1441,8 +1441,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rd_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rd_full_we),
@@ -1450,11 +1450,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rd_full.q ),
+ .q (reg2hw.intr_enable.rd_full.q),
// to register interface (read)
.qs (intr_enable_rd_full_qs)
@@ -1467,8 +1467,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_rd_lvl (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_rd_lvl_we),
@@ -1476,11 +1476,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rd_lvl.q ),
+ .q (reg2hw.intr_enable.rd_lvl.q),
// to register interface (read)
.qs (intr_enable_rd_lvl_qs)
@@ -1493,8 +1493,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_op_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_op_done_we),
@@ -1502,11 +1502,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.op_done.q ),
+ .q (reg2hw.intr_enable.op_done.q),
// to register interface (read)
.qs (intr_enable_op_done_qs)
@@ -1519,8 +1519,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_err_we),
@@ -1528,11 +1528,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.err.q ),
+ .q (reg2hw.intr_enable.err.q),
// to register interface (read)
.qs (intr_enable_err_qs)
@@ -1551,7 +1551,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.prog_empty.qe),
- .q (reg2hw.intr_test.prog_empty.q ),
+ .q (reg2hw.intr_test.prog_empty.q),
.qs ()
);
@@ -1566,7 +1566,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.prog_lvl.qe),
- .q (reg2hw.intr_test.prog_lvl.q ),
+ .q (reg2hw.intr_test.prog_lvl.q),
.qs ()
);
@@ -1581,7 +1581,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rd_full.qe),
- .q (reg2hw.intr_test.rd_full.q ),
+ .q (reg2hw.intr_test.rd_full.q),
.qs ()
);
@@ -1596,7 +1596,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.rd_lvl.qe),
- .q (reg2hw.intr_test.rd_lvl.q ),
+ .q (reg2hw.intr_test.rd_lvl.q),
.qs ()
);
@@ -1611,7 +1611,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.op_done.qe),
- .q (reg2hw.intr_test.op_done.q ),
+ .q (reg2hw.intr_test.op_done.q),
.qs ()
);
@@ -1626,7 +1626,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.err.qe),
- .q (reg2hw.intr_test.err.q ),
+ .q (reg2hw.intr_test.err.q),
.qs ()
);
@@ -1643,7 +1643,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_err.qe),
- .q (reg2hw.alert_test.recov_err.q ),
+ .q (reg2hw.alert_test.recov_err.q),
.qs ()
);
@@ -1658,7 +1658,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_mp_err.qe),
- .q (reg2hw.alert_test.recov_mp_err.q ),
+ .q (reg2hw.alert_test.recov_mp_err.q),
.qs ()
);
@@ -1673,7 +1673,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_ecc_err.qe),
- .q (reg2hw.alert_test.recov_ecc_err.q ),
+ .q (reg2hw.alert_test.recov_ecc_err.q),
.qs ()
);
@@ -1688,7 +1688,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.fatal_intg_err.qe),
- .q (reg2hw.alert_test.fatal_intg_err.q ),
+ .q (reg2hw.alert_test.fatal_intg_err.q),
.qs ()
);
@@ -1700,8 +1700,8 @@
.SWACCESS("W1S"),
.RESVAL (1'h0)
) u_init (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (init_we),
@@ -1709,11 +1709,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.init.q ),
+ .q (reg2hw.init.q),
// to register interface (read)
.qs (init_qs)
@@ -1744,20 +1744,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_start (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_start_we & ctrl_regwen_qs),
.wd (control_start_wd),
// from internal hardware
.de (hw2reg.control.start.de),
- .d (hw2reg.control.start.d ),
+ .d (hw2reg.control.start.d),
// to internal hardware
.qe (),
- .q (reg2hw.control.start.q ),
+ .q (reg2hw.control.start.q),
// to register interface (read)
.qs (control_start_qs)
@@ -1770,20 +1770,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_control_op (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_op_we & ctrl_regwen_qs),
.wd (control_op_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.op.q ),
+ .q (reg2hw.control.op.q),
// to register interface (read)
.qs (control_op_qs)
@@ -1796,20 +1796,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_prog_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_prog_sel_we & ctrl_regwen_qs),
.wd (control_prog_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.prog_sel.q ),
+ .q (reg2hw.control.prog_sel.q),
// to register interface (read)
.qs (control_prog_sel_qs)
@@ -1822,20 +1822,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_erase_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_erase_sel_we & ctrl_regwen_qs),
.wd (control_erase_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.erase_sel.q ),
+ .q (reg2hw.control.erase_sel.q),
// to register interface (read)
.qs (control_erase_sel_qs)
@@ -1848,20 +1848,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_partition_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_partition_sel_we & ctrl_regwen_qs),
.wd (control_partition_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.partition_sel.q ),
+ .q (reg2hw.control.partition_sel.q),
// to register interface (read)
.qs (control_partition_sel_qs)
@@ -1874,20 +1874,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_control_info_sel (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_info_sel_we & ctrl_regwen_qs),
.wd (control_info_sel_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.info_sel.q ),
+ .q (reg2hw.control.info_sel.q),
// to register interface (read)
.qs (control_info_sel_qs)
@@ -1900,20 +1900,20 @@
.SWACCESS("RW"),
.RESVAL (12'h0)
) u_control_num (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_num_we & ctrl_regwen_qs),
.wd (control_num_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.num.q ),
+ .q (reg2hw.control.num.q),
// to register interface (read)
.qs (control_num_qs)
@@ -1927,8 +1927,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_addr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (addr_we),
@@ -1936,11 +1936,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.addr.q ),
+ .q (reg2hw.addr.q),
// to register interface (read)
.qs (addr_qs)
@@ -1955,8 +1955,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_prog_type_en_normal (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prog_type_en_normal_we),
@@ -1964,11 +1964,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prog_type_en.normal.q ),
+ .q (reg2hw.prog_type_en.normal.q),
// to register interface (read)
.qs (prog_type_en_normal_qs)
@@ -1981,8 +1981,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_prog_type_en_repair (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prog_type_en_repair_we),
@@ -1990,11 +1990,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prog_type_en.repair.q ),
+ .q (reg2hw.prog_type_en.repair.q),
// to register interface (read)
.qs (prog_type_en_repair_qs)
@@ -2008,8 +2008,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_erase_suspend (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (erase_suspend_we),
@@ -2017,11 +2017,11 @@
// from internal hardware
.de (hw2reg.erase_suspend.de),
- .d (hw2reg.erase_suspend.d ),
+ .d (hw2reg.erase_suspend.d),
// to internal hardware
.qe (),
- .q (reg2hw.erase_suspend.q ),
+ .q (reg2hw.erase_suspend.q),
// to register interface (read)
.qs (erase_suspend_qs)
@@ -2037,8 +2037,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_0_we),
@@ -2046,7 +2046,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2064,8 +2064,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_1_we),
@@ -2073,7 +2073,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2091,8 +2091,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_2_we),
@@ -2100,7 +2100,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2118,8 +2118,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_3_we),
@@ -2127,7 +2127,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2145,8 +2145,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_4_we),
@@ -2154,7 +2154,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2172,8 +2172,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_5_we),
@@ -2181,7 +2181,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2199,8 +2199,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_6_we),
@@ -2208,7 +2208,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2226,8 +2226,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_region_cfg_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (region_cfg_regwen_7_we),
@@ -2235,7 +2235,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2256,20 +2256,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].en.q ),
+ .q (reg2hw.mp_region_cfg[0].en.q),
// to register interface (read)
.qs (mp_region_cfg_0_en_0_qs)
@@ -2282,20 +2282,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_rd_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[0].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_rd_en_0_qs)
@@ -2308,20 +2308,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_prog_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[0].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_prog_en_0_qs)
@@ -2334,20 +2334,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_erase_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[0].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_erase_en_0_qs)
@@ -2360,20 +2360,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_scramble_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[0].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_scramble_en_0_qs)
@@ -2386,20 +2386,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_ecc_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[0].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_ecc_en_0_qs)
@@ -2412,20 +2412,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_he_en_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].he_en.q ),
+ .q (reg2hw.mp_region_cfg[0].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_0_he_en_0_qs)
@@ -2438,20 +2438,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_0_base_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_base_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_base_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].base.q ),
+ .q (reg2hw.mp_region_cfg[0].base.q),
// to register interface (read)
.qs (mp_region_cfg_0_base_0_qs)
@@ -2464,20 +2464,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_0_size_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_0_size_0_we & region_cfg_regwen_0_qs),
.wd (mp_region_cfg_0_size_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[0].size.q ),
+ .q (reg2hw.mp_region_cfg[0].size.q),
// to register interface (read)
.qs (mp_region_cfg_0_size_0_qs)
@@ -2493,20 +2493,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].en.q ),
+ .q (reg2hw.mp_region_cfg[1].en.q),
// to register interface (read)
.qs (mp_region_cfg_1_en_1_qs)
@@ -2519,20 +2519,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_rd_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[1].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_rd_en_1_qs)
@@ -2545,20 +2545,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_prog_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[1].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_prog_en_1_qs)
@@ -2571,20 +2571,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_erase_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[1].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_erase_en_1_qs)
@@ -2597,20 +2597,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_scramble_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[1].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_scramble_en_1_qs)
@@ -2623,20 +2623,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_ecc_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[1].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_ecc_en_1_qs)
@@ -2649,20 +2649,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_he_en_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].he_en.q ),
+ .q (reg2hw.mp_region_cfg[1].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_1_he_en_1_qs)
@@ -2675,20 +2675,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_1_base_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_base_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_base_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].base.q ),
+ .q (reg2hw.mp_region_cfg[1].base.q),
// to register interface (read)
.qs (mp_region_cfg_1_base_1_qs)
@@ -2701,20 +2701,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_1_size_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_1_size_1_we & region_cfg_regwen_1_qs),
.wd (mp_region_cfg_1_size_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[1].size.q ),
+ .q (reg2hw.mp_region_cfg[1].size.q),
// to register interface (read)
.qs (mp_region_cfg_1_size_1_qs)
@@ -2730,20 +2730,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].en.q ),
+ .q (reg2hw.mp_region_cfg[2].en.q),
// to register interface (read)
.qs (mp_region_cfg_2_en_2_qs)
@@ -2756,20 +2756,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_rd_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_rd_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_rd_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[2].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_rd_en_2_qs)
@@ -2782,20 +2782,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_prog_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_prog_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_prog_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[2].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_prog_en_2_qs)
@@ -2808,20 +2808,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_erase_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_erase_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_erase_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[2].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_erase_en_2_qs)
@@ -2834,20 +2834,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_scramble_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_scramble_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_scramble_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[2].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_scramble_en_2_qs)
@@ -2860,20 +2860,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_ecc_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_ecc_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_ecc_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[2].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_ecc_en_2_qs)
@@ -2886,20 +2886,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_2_he_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_he_en_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_he_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].he_en.q ),
+ .q (reg2hw.mp_region_cfg[2].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_2_he_en_2_qs)
@@ -2912,20 +2912,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_2_base_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_base_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_base_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].base.q ),
+ .q (reg2hw.mp_region_cfg[2].base.q),
// to register interface (read)
.qs (mp_region_cfg_2_base_2_qs)
@@ -2938,20 +2938,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_2_size_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_2_size_2_we & region_cfg_regwen_2_qs),
.wd (mp_region_cfg_2_size_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[2].size.q ),
+ .q (reg2hw.mp_region_cfg[2].size.q),
// to register interface (read)
.qs (mp_region_cfg_2_size_2_qs)
@@ -2967,20 +2967,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].en.q ),
+ .q (reg2hw.mp_region_cfg[3].en.q),
// to register interface (read)
.qs (mp_region_cfg_3_en_3_qs)
@@ -2993,20 +2993,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_rd_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_rd_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_rd_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[3].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_rd_en_3_qs)
@@ -3019,20 +3019,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_prog_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_prog_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_prog_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[3].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_prog_en_3_qs)
@@ -3045,20 +3045,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_erase_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_erase_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_erase_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[3].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_erase_en_3_qs)
@@ -3071,20 +3071,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_scramble_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_scramble_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_scramble_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[3].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_scramble_en_3_qs)
@@ -3097,20 +3097,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_ecc_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_ecc_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_ecc_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[3].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_ecc_en_3_qs)
@@ -3123,20 +3123,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_3_he_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_he_en_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_he_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].he_en.q ),
+ .q (reg2hw.mp_region_cfg[3].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_3_he_en_3_qs)
@@ -3149,20 +3149,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_3_base_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_base_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_base_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].base.q ),
+ .q (reg2hw.mp_region_cfg[3].base.q),
// to register interface (read)
.qs (mp_region_cfg_3_base_3_qs)
@@ -3175,20 +3175,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_3_size_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_3_size_3_we & region_cfg_regwen_3_qs),
.wd (mp_region_cfg_3_size_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[3].size.q ),
+ .q (reg2hw.mp_region_cfg[3].size.q),
// to register interface (read)
.qs (mp_region_cfg_3_size_3_qs)
@@ -3204,20 +3204,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].en.q ),
+ .q (reg2hw.mp_region_cfg[4].en.q),
// to register interface (read)
.qs (mp_region_cfg_4_en_4_qs)
@@ -3230,20 +3230,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_rd_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_rd_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_rd_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[4].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_rd_en_4_qs)
@@ -3256,20 +3256,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_prog_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_prog_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_prog_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[4].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_prog_en_4_qs)
@@ -3282,20 +3282,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_erase_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_erase_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_erase_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[4].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_erase_en_4_qs)
@@ -3308,20 +3308,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_scramble_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_scramble_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_scramble_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[4].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_scramble_en_4_qs)
@@ -3334,20 +3334,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_ecc_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_ecc_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_ecc_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[4].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_ecc_en_4_qs)
@@ -3360,20 +3360,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_4_he_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_he_en_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_he_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].he_en.q ),
+ .q (reg2hw.mp_region_cfg[4].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_4_he_en_4_qs)
@@ -3386,20 +3386,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_4_base_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_base_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_base_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].base.q ),
+ .q (reg2hw.mp_region_cfg[4].base.q),
// to register interface (read)
.qs (mp_region_cfg_4_base_4_qs)
@@ -3412,20 +3412,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_4_size_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_4_size_4_we & region_cfg_regwen_4_qs),
.wd (mp_region_cfg_4_size_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[4].size.q ),
+ .q (reg2hw.mp_region_cfg[4].size.q),
// to register interface (read)
.qs (mp_region_cfg_4_size_4_qs)
@@ -3441,20 +3441,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].en.q ),
+ .q (reg2hw.mp_region_cfg[5].en.q),
// to register interface (read)
.qs (mp_region_cfg_5_en_5_qs)
@@ -3467,20 +3467,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_rd_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_rd_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_rd_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[5].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_rd_en_5_qs)
@@ -3493,20 +3493,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_prog_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_prog_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_prog_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[5].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_prog_en_5_qs)
@@ -3519,20 +3519,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_erase_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_erase_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_erase_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[5].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_erase_en_5_qs)
@@ -3545,20 +3545,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_scramble_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_scramble_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_scramble_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[5].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_scramble_en_5_qs)
@@ -3571,20 +3571,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_ecc_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_ecc_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_ecc_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[5].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_ecc_en_5_qs)
@@ -3597,20 +3597,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_5_he_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_he_en_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_he_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].he_en.q ),
+ .q (reg2hw.mp_region_cfg[5].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_5_he_en_5_qs)
@@ -3623,20 +3623,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_5_base_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_base_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_base_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].base.q ),
+ .q (reg2hw.mp_region_cfg[5].base.q),
// to register interface (read)
.qs (mp_region_cfg_5_base_5_qs)
@@ -3649,20 +3649,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_5_size_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_5_size_5_we & region_cfg_regwen_5_qs),
.wd (mp_region_cfg_5_size_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[5].size.q ),
+ .q (reg2hw.mp_region_cfg[5].size.q),
// to register interface (read)
.qs (mp_region_cfg_5_size_5_qs)
@@ -3678,20 +3678,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].en.q ),
+ .q (reg2hw.mp_region_cfg[6].en.q),
// to register interface (read)
.qs (mp_region_cfg_6_en_6_qs)
@@ -3704,20 +3704,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_rd_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_rd_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_rd_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[6].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_rd_en_6_qs)
@@ -3730,20 +3730,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_prog_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_prog_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_prog_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[6].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_prog_en_6_qs)
@@ -3756,20 +3756,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_erase_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_erase_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_erase_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[6].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_erase_en_6_qs)
@@ -3782,20 +3782,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_scramble_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_scramble_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_scramble_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[6].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_scramble_en_6_qs)
@@ -3808,20 +3808,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_ecc_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_ecc_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_ecc_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[6].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_ecc_en_6_qs)
@@ -3834,20 +3834,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_6_he_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_he_en_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_he_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].he_en.q ),
+ .q (reg2hw.mp_region_cfg[6].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_6_he_en_6_qs)
@@ -3860,20 +3860,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_6_base_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_base_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_base_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].base.q ),
+ .q (reg2hw.mp_region_cfg[6].base.q),
// to register interface (read)
.qs (mp_region_cfg_6_base_6_qs)
@@ -3886,20 +3886,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_6_size_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_6_size_6_we & region_cfg_regwen_6_qs),
.wd (mp_region_cfg_6_size_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[6].size.q ),
+ .q (reg2hw.mp_region_cfg[6].size.q),
// to register interface (read)
.qs (mp_region_cfg_6_size_6_qs)
@@ -3915,20 +3915,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].en.q ),
+ .q (reg2hw.mp_region_cfg[7].en.q),
// to register interface (read)
.qs (mp_region_cfg_7_en_7_qs)
@@ -3941,20 +3941,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_rd_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_rd_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_rd_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].rd_en.q ),
+ .q (reg2hw.mp_region_cfg[7].rd_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_rd_en_7_qs)
@@ -3967,20 +3967,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_prog_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_prog_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_prog_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].prog_en.q ),
+ .q (reg2hw.mp_region_cfg[7].prog_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_prog_en_7_qs)
@@ -3993,20 +3993,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_erase_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_erase_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_erase_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].erase_en.q ),
+ .q (reg2hw.mp_region_cfg[7].erase_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_erase_en_7_qs)
@@ -4019,20 +4019,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_scramble_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_scramble_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_scramble_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].scramble_en.q ),
+ .q (reg2hw.mp_region_cfg[7].scramble_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_scramble_en_7_qs)
@@ -4045,20 +4045,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_ecc_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_ecc_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_ecc_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].ecc_en.q ),
+ .q (reg2hw.mp_region_cfg[7].ecc_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_ecc_en_7_qs)
@@ -4071,20 +4071,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_region_cfg_7_he_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_he_en_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_he_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].he_en.q ),
+ .q (reg2hw.mp_region_cfg[7].he_en.q),
// to register interface (read)
.qs (mp_region_cfg_7_he_en_7_qs)
@@ -4097,20 +4097,20 @@
.SWACCESS("RW"),
.RESVAL (9'h0)
) u_mp_region_cfg_7_base_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_base_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_base_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].base.q ),
+ .q (reg2hw.mp_region_cfg[7].base.q),
// to register interface (read)
.qs (mp_region_cfg_7_base_7_qs)
@@ -4123,20 +4123,20 @@
.SWACCESS("RW"),
.RESVAL (10'h0)
) u_mp_region_cfg_7_size_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_region_cfg_7_size_7_we & region_cfg_regwen_7_qs),
.wd (mp_region_cfg_7_size_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_region_cfg[7].size.q ),
+ .q (reg2hw.mp_region_cfg[7].size.q),
// to register interface (read)
.qs (mp_region_cfg_7_size_7_qs)
@@ -4152,8 +4152,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_rd_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_rd_en_we),
@@ -4161,11 +4161,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.rd_en.q ),
+ .q (reg2hw.default_region.rd_en.q),
// to register interface (read)
.qs (default_region_rd_en_qs)
@@ -4178,8 +4178,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_prog_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_prog_en_we),
@@ -4187,11 +4187,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.prog_en.q ),
+ .q (reg2hw.default_region.prog_en.q),
// to register interface (read)
.qs (default_region_prog_en_qs)
@@ -4204,8 +4204,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_erase_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_erase_en_we),
@@ -4213,11 +4213,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.erase_en.q ),
+ .q (reg2hw.default_region.erase_en.q),
// to register interface (read)
.qs (default_region_erase_en_qs)
@@ -4230,8 +4230,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_scramble_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_scramble_en_we),
@@ -4239,11 +4239,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.scramble_en.q ),
+ .q (reg2hw.default_region.scramble_en.q),
// to register interface (read)
.qs (default_region_scramble_en_qs)
@@ -4256,8 +4256,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_ecc_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_ecc_en_we),
@@ -4265,11 +4265,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.ecc_en.q ),
+ .q (reg2hw.default_region.ecc_en.q),
// to register interface (read)
.qs (default_region_ecc_en_qs)
@@ -4282,8 +4282,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_default_region_he_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (default_region_he_en_we),
@@ -4291,11 +4291,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.default_region.he_en.q ),
+ .q (reg2hw.default_region.he_en.q),
// to register interface (read)
.qs (default_region_he_en_qs)
@@ -4311,8 +4311,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_0_we),
@@ -4320,7 +4320,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4338,8 +4338,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_1_we),
@@ -4347,7 +4347,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4365,8 +4365,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_2_we),
@@ -4374,7 +4374,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4392,8 +4392,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_3_we),
@@ -4401,7 +4401,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4419,8 +4419,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_4_we),
@@ -4428,7 +4428,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4446,8 +4446,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_5_we),
@@ -4455,7 +4455,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4473,8 +4473,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_6_we),
@@ -4482,7 +4482,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4500,8 +4500,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_7_we),
@@ -4509,7 +4509,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4527,8 +4527,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_8_we),
@@ -4536,7 +4536,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4554,8 +4554,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info0_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info0_regwen_9_we),
@@ -4563,7 +4563,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -4584,20 +4584,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_en_0_qs)
@@ -4610,20 +4610,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_rd_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_rd_en_0_qs)
@@ -4636,20 +4636,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_prog_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_prog_en_0_qs)
@@ -4662,20 +4662,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_erase_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_erase_en_0_qs)
@@ -4688,20 +4688,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_scramble_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_scramble_en_0_qs)
@@ -4714,20 +4714,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_ecc_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_ecc_en_0_qs)
@@ -4740,20 +4740,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_0_he_en_0_we & bank0_info0_regwen_0_qs),
.wd (bank0_info0_page_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_0_he_en_0_qs)
@@ -4769,20 +4769,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_en_1_qs)
@@ -4795,20 +4795,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_rd_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_rd_en_1_qs)
@@ -4821,20 +4821,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_prog_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_prog_en_1_qs)
@@ -4847,20 +4847,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_erase_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_erase_en_1_qs)
@@ -4873,20 +4873,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_scramble_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_scramble_en_1_qs)
@@ -4899,20 +4899,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_ecc_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_ecc_en_1_qs)
@@ -4925,20 +4925,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_1_he_en_1_we & bank0_info0_regwen_1_qs),
.wd (bank0_info0_page_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[1].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[1].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_1_he_en_1_qs)
@@ -4954,20 +4954,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_en_2_qs)
@@ -4980,20 +4980,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_rd_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_rd_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_rd_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_rd_en_2_qs)
@@ -5006,20 +5006,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_prog_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_prog_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_prog_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_prog_en_2_qs)
@@ -5032,20 +5032,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_erase_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_erase_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_erase_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_erase_en_2_qs)
@@ -5058,20 +5058,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_scramble_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_scramble_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_scramble_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_scramble_en_2_qs)
@@ -5084,20 +5084,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_ecc_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_ecc_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_ecc_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_ecc_en_2_qs)
@@ -5110,20 +5110,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_2_he_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_2_he_en_2_we & bank0_info0_regwen_2_qs),
.wd (bank0_info0_page_cfg_2_he_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[2].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[2].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_2_he_en_2_qs)
@@ -5139,20 +5139,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_en_3_qs)
@@ -5165,20 +5165,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_rd_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_rd_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_rd_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_rd_en_3_qs)
@@ -5191,20 +5191,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_prog_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_prog_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_prog_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_prog_en_3_qs)
@@ -5217,20 +5217,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_erase_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_erase_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_erase_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_erase_en_3_qs)
@@ -5243,20 +5243,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_scramble_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_scramble_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_scramble_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_scramble_en_3_qs)
@@ -5269,20 +5269,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_ecc_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_ecc_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_ecc_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_ecc_en_3_qs)
@@ -5295,20 +5295,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_3_he_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_3_he_en_3_we & bank0_info0_regwen_3_qs),
.wd (bank0_info0_page_cfg_3_he_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[3].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[3].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_3_he_en_3_qs)
@@ -5324,20 +5324,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_en_4_qs)
@@ -5350,20 +5350,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_rd_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_rd_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_rd_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_rd_en_4_qs)
@@ -5376,20 +5376,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_prog_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_prog_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_prog_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_prog_en_4_qs)
@@ -5402,20 +5402,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_erase_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_erase_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_erase_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_erase_en_4_qs)
@@ -5428,20 +5428,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_scramble_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_scramble_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_scramble_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_scramble_en_4_qs)
@@ -5454,20 +5454,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_ecc_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_ecc_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_ecc_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_ecc_en_4_qs)
@@ -5480,20 +5480,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_4_he_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_4_he_en_4_we & bank0_info0_regwen_4_qs),
.wd (bank0_info0_page_cfg_4_he_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[4].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[4].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_4_he_en_4_qs)
@@ -5509,20 +5509,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_en_5_qs)
@@ -5535,20 +5535,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_rd_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_rd_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_rd_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_rd_en_5_qs)
@@ -5561,20 +5561,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_prog_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_prog_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_prog_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_prog_en_5_qs)
@@ -5587,20 +5587,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_erase_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_erase_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_erase_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_erase_en_5_qs)
@@ -5613,20 +5613,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_scramble_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_scramble_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_scramble_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_scramble_en_5_qs)
@@ -5639,20 +5639,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_ecc_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_ecc_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_ecc_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_ecc_en_5_qs)
@@ -5665,20 +5665,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_5_he_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_5_he_en_5_we & bank0_info0_regwen_5_qs),
.wd (bank0_info0_page_cfg_5_he_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[5].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[5].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_5_he_en_5_qs)
@@ -5694,20 +5694,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_en_6_qs)
@@ -5720,20 +5720,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_rd_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_rd_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_rd_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_rd_en_6_qs)
@@ -5746,20 +5746,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_prog_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_prog_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_prog_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_prog_en_6_qs)
@@ -5772,20 +5772,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_erase_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_erase_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_erase_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_erase_en_6_qs)
@@ -5798,20 +5798,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_scramble_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_scramble_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_scramble_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_scramble_en_6_qs)
@@ -5824,20 +5824,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_ecc_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_ecc_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_ecc_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_ecc_en_6_qs)
@@ -5850,20 +5850,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_6_he_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_6_he_en_6_we & bank0_info0_regwen_6_qs),
.wd (bank0_info0_page_cfg_6_he_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[6].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[6].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_6_he_en_6_qs)
@@ -5879,20 +5879,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_en_7_qs)
@@ -5905,20 +5905,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_rd_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_rd_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_rd_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_rd_en_7_qs)
@@ -5931,20 +5931,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_prog_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_prog_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_prog_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_prog_en_7_qs)
@@ -5957,20 +5957,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_erase_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_erase_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_erase_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_erase_en_7_qs)
@@ -5983,20 +5983,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_scramble_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_scramble_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_scramble_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_scramble_en_7_qs)
@@ -6009,20 +6009,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_ecc_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_ecc_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_ecc_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_ecc_en_7_qs)
@@ -6035,20 +6035,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_7_he_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_7_he_en_7_we & bank0_info0_regwen_7_qs),
.wd (bank0_info0_page_cfg_7_he_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[7].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[7].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_7_he_en_7_qs)
@@ -6064,20 +6064,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_en_8_qs)
@@ -6090,20 +6090,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_rd_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_rd_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_rd_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_rd_en_8_qs)
@@ -6116,20 +6116,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_prog_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_prog_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_prog_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_prog_en_8_qs)
@@ -6142,20 +6142,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_erase_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_erase_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_erase_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_erase_en_8_qs)
@@ -6168,20 +6168,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_scramble_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_scramble_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_scramble_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_scramble_en_8_qs)
@@ -6194,20 +6194,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_ecc_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_ecc_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_ecc_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_ecc_en_8_qs)
@@ -6220,20 +6220,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_8_he_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_8_he_en_8_we & bank0_info0_regwen_8_qs),
.wd (bank0_info0_page_cfg_8_he_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[8].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[8].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_8_he_en_8_qs)
@@ -6249,20 +6249,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_en_9_qs)
@@ -6275,20 +6275,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_rd_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_rd_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_rd_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].rd_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].rd_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_rd_en_9_qs)
@@ -6301,20 +6301,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_prog_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_prog_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_prog_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].prog_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].prog_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_prog_en_9_qs)
@@ -6327,20 +6327,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_erase_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_erase_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_erase_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].erase_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].erase_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_erase_en_9_qs)
@@ -6353,20 +6353,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_scramble_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_scramble_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_scramble_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].scramble_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].scramble_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_scramble_en_9_qs)
@@ -6379,20 +6379,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_ecc_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_ecc_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_ecc_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].ecc_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].ecc_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_ecc_en_9_qs)
@@ -6405,20 +6405,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info0_page_cfg_9_he_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info0_page_cfg_9_he_en_9_we & bank0_info0_regwen_9_qs),
.wd (bank0_info0_page_cfg_9_he_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info0_page_cfg[9].he_en.q ),
+ .q (reg2hw.bank0_info0_page_cfg[9].he_en.q),
// to register interface (read)
.qs (bank0_info0_page_cfg_9_he_en_9_qs)
@@ -6435,8 +6435,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info1_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info1_regwen_we),
@@ -6444,7 +6444,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6465,20 +6465,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_en_0_qs)
@@ -6491,20 +6491,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_rd_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_rd_en_0_qs)
@@ -6517,20 +6517,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_prog_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_prog_en_0_qs)
@@ -6543,20 +6543,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_erase_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_erase_en_0_qs)
@@ -6569,20 +6569,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_scramble_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_scramble_en_0_qs)
@@ -6595,20 +6595,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_ecc_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_ecc_en_0_qs)
@@ -6621,20 +6621,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info1_page_cfg_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info1_page_cfg_he_en_0_we & bank0_info1_regwen_qs),
.wd (bank0_info1_page_cfg_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info1_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank0_info1_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank0_info1_page_cfg_he_en_0_qs)
@@ -6651,8 +6651,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info2_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info2_regwen_0_we),
@@ -6660,7 +6660,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6678,8 +6678,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank0_info2_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank0_info2_regwen_1_we),
@@ -6687,7 +6687,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6708,20 +6708,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_en_0_qs)
@@ -6734,20 +6734,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_rd_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_rd_en_0_qs)
@@ -6760,20 +6760,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_prog_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_prog_en_0_qs)
@@ -6786,20 +6786,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_erase_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_erase_en_0_qs)
@@ -6812,20 +6812,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_scramble_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_scramble_en_0_qs)
@@ -6838,20 +6838,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_ecc_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_ecc_en_0_qs)
@@ -6864,20 +6864,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_0_he_en_0_we & bank0_info2_regwen_0_qs),
.wd (bank0_info2_page_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_0_he_en_0_qs)
@@ -6893,20 +6893,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_en_1_qs)
@@ -6919,20 +6919,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_rd_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].rd_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].rd_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_rd_en_1_qs)
@@ -6945,20 +6945,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_prog_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].prog_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].prog_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_prog_en_1_qs)
@@ -6971,20 +6971,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_erase_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].erase_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].erase_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_erase_en_1_qs)
@@ -6997,20 +6997,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_scramble_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].scramble_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].scramble_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_scramble_en_1_qs)
@@ -7023,20 +7023,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_ecc_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].ecc_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].ecc_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_ecc_en_1_qs)
@@ -7049,20 +7049,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank0_info2_page_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank0_info2_page_cfg_1_he_en_1_we & bank0_info2_regwen_1_qs),
.wd (bank0_info2_page_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank0_info2_page_cfg[1].he_en.q ),
+ .q (reg2hw.bank0_info2_page_cfg[1].he_en.q),
// to register interface (read)
.qs (bank0_info2_page_cfg_1_he_en_1_qs)
@@ -7079,8 +7079,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_0_we),
@@ -7088,7 +7088,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7106,8 +7106,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_1_we),
@@ -7115,7 +7115,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7133,8 +7133,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_2_we),
@@ -7142,7 +7142,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7160,8 +7160,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_3_we),
@@ -7169,7 +7169,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7187,8 +7187,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_4_we),
@@ -7196,7 +7196,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7214,8 +7214,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_5_we),
@@ -7223,7 +7223,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7241,8 +7241,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_6_we),
@@ -7250,7 +7250,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7268,8 +7268,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_7_we),
@@ -7277,7 +7277,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7295,8 +7295,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_8_we),
@@ -7304,7 +7304,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7322,8 +7322,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info0_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info0_regwen_9_we),
@@ -7331,7 +7331,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7352,20 +7352,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_en_0_qs)
@@ -7378,20 +7378,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_rd_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_rd_en_0_qs)
@@ -7404,20 +7404,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_prog_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_prog_en_0_qs)
@@ -7430,20 +7430,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_erase_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_erase_en_0_qs)
@@ -7456,20 +7456,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_scramble_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_scramble_en_0_qs)
@@ -7482,20 +7482,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_ecc_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_ecc_en_0_qs)
@@ -7508,20 +7508,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_0_he_en_0_we & bank1_info0_regwen_0_qs),
.wd (bank1_info0_page_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_0_he_en_0_qs)
@@ -7537,20 +7537,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_en_1_qs)
@@ -7563,20 +7563,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_rd_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_rd_en_1_qs)
@@ -7589,20 +7589,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_prog_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_prog_en_1_qs)
@@ -7615,20 +7615,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_erase_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_erase_en_1_qs)
@@ -7641,20 +7641,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_scramble_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_scramble_en_1_qs)
@@ -7667,20 +7667,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_ecc_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_ecc_en_1_qs)
@@ -7693,20 +7693,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_1_he_en_1_we & bank1_info0_regwen_1_qs),
.wd (bank1_info0_page_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[1].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[1].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_1_he_en_1_qs)
@@ -7722,20 +7722,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_en_2_qs)
@@ -7748,20 +7748,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_rd_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_rd_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_rd_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_rd_en_2_qs)
@@ -7774,20 +7774,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_prog_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_prog_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_prog_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_prog_en_2_qs)
@@ -7800,20 +7800,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_erase_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_erase_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_erase_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_erase_en_2_qs)
@@ -7826,20 +7826,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_scramble_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_scramble_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_scramble_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_scramble_en_2_qs)
@@ -7852,20 +7852,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_ecc_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_ecc_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_ecc_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_ecc_en_2_qs)
@@ -7878,20 +7878,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_2_he_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_2_he_en_2_we & bank1_info0_regwen_2_qs),
.wd (bank1_info0_page_cfg_2_he_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[2].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[2].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_2_he_en_2_qs)
@@ -7907,20 +7907,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_en_3_qs)
@@ -7933,20 +7933,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_rd_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_rd_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_rd_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_rd_en_3_qs)
@@ -7959,20 +7959,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_prog_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_prog_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_prog_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_prog_en_3_qs)
@@ -7985,20 +7985,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_erase_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_erase_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_erase_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_erase_en_3_qs)
@@ -8011,20 +8011,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_scramble_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_scramble_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_scramble_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_scramble_en_3_qs)
@@ -8037,20 +8037,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_ecc_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_ecc_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_ecc_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_ecc_en_3_qs)
@@ -8063,20 +8063,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_3_he_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_3_he_en_3_we & bank1_info0_regwen_3_qs),
.wd (bank1_info0_page_cfg_3_he_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[3].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[3].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_3_he_en_3_qs)
@@ -8092,20 +8092,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_en_4_qs)
@@ -8118,20 +8118,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_rd_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_rd_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_rd_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_rd_en_4_qs)
@@ -8144,20 +8144,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_prog_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_prog_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_prog_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_prog_en_4_qs)
@@ -8170,20 +8170,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_erase_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_erase_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_erase_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_erase_en_4_qs)
@@ -8196,20 +8196,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_scramble_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_scramble_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_scramble_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_scramble_en_4_qs)
@@ -8222,20 +8222,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_ecc_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_ecc_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_ecc_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_ecc_en_4_qs)
@@ -8248,20 +8248,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_4_he_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_4_he_en_4_we & bank1_info0_regwen_4_qs),
.wd (bank1_info0_page_cfg_4_he_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[4].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[4].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_4_he_en_4_qs)
@@ -8277,20 +8277,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_en_5_qs)
@@ -8303,20 +8303,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_rd_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_rd_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_rd_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_rd_en_5_qs)
@@ -8329,20 +8329,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_prog_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_prog_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_prog_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_prog_en_5_qs)
@@ -8355,20 +8355,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_erase_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_erase_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_erase_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_erase_en_5_qs)
@@ -8381,20 +8381,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_scramble_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_scramble_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_scramble_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_scramble_en_5_qs)
@@ -8407,20 +8407,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_ecc_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_ecc_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_ecc_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_ecc_en_5_qs)
@@ -8433,20 +8433,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_5_he_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_5_he_en_5_we & bank1_info0_regwen_5_qs),
.wd (bank1_info0_page_cfg_5_he_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[5].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[5].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_5_he_en_5_qs)
@@ -8462,20 +8462,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_en_6_qs)
@@ -8488,20 +8488,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_rd_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_rd_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_rd_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_rd_en_6_qs)
@@ -8514,20 +8514,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_prog_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_prog_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_prog_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_prog_en_6_qs)
@@ -8540,20 +8540,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_erase_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_erase_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_erase_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_erase_en_6_qs)
@@ -8566,20 +8566,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_scramble_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_scramble_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_scramble_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_scramble_en_6_qs)
@@ -8592,20 +8592,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_ecc_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_ecc_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_ecc_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_ecc_en_6_qs)
@@ -8618,20 +8618,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_6_he_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_6_he_en_6_we & bank1_info0_regwen_6_qs),
.wd (bank1_info0_page_cfg_6_he_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[6].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[6].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_6_he_en_6_qs)
@@ -8647,20 +8647,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_en_7_qs)
@@ -8673,20 +8673,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_rd_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_rd_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_rd_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_rd_en_7_qs)
@@ -8699,20 +8699,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_prog_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_prog_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_prog_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_prog_en_7_qs)
@@ -8725,20 +8725,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_erase_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_erase_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_erase_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_erase_en_7_qs)
@@ -8751,20 +8751,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_scramble_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_scramble_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_scramble_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_scramble_en_7_qs)
@@ -8777,20 +8777,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_ecc_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_ecc_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_ecc_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_ecc_en_7_qs)
@@ -8803,20 +8803,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_7_he_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_7_he_en_7_we & bank1_info0_regwen_7_qs),
.wd (bank1_info0_page_cfg_7_he_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[7].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[7].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_7_he_en_7_qs)
@@ -8832,20 +8832,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_en_8_qs)
@@ -8858,20 +8858,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_rd_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_rd_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_rd_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_rd_en_8_qs)
@@ -8884,20 +8884,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_prog_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_prog_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_prog_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_prog_en_8_qs)
@@ -8910,20 +8910,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_erase_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_erase_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_erase_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_erase_en_8_qs)
@@ -8936,20 +8936,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_scramble_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_scramble_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_scramble_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_scramble_en_8_qs)
@@ -8962,20 +8962,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_ecc_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_ecc_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_ecc_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_ecc_en_8_qs)
@@ -8988,20 +8988,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_8_he_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_8_he_en_8_we & bank1_info0_regwen_8_qs),
.wd (bank1_info0_page_cfg_8_he_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[8].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[8].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_8_he_en_8_qs)
@@ -9017,20 +9017,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_en_9_qs)
@@ -9043,20 +9043,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_rd_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_rd_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_rd_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].rd_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].rd_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_rd_en_9_qs)
@@ -9069,20 +9069,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_prog_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_prog_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_prog_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].prog_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].prog_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_prog_en_9_qs)
@@ -9095,20 +9095,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_erase_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_erase_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_erase_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].erase_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].erase_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_erase_en_9_qs)
@@ -9121,20 +9121,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_scramble_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_scramble_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_scramble_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].scramble_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].scramble_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_scramble_en_9_qs)
@@ -9147,20 +9147,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_ecc_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_ecc_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_ecc_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].ecc_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].ecc_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_ecc_en_9_qs)
@@ -9173,20 +9173,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info0_page_cfg_9_he_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info0_page_cfg_9_he_en_9_we & bank1_info0_regwen_9_qs),
.wd (bank1_info0_page_cfg_9_he_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info0_page_cfg[9].he_en.q ),
+ .q (reg2hw.bank1_info0_page_cfg[9].he_en.q),
// to register interface (read)
.qs (bank1_info0_page_cfg_9_he_en_9_qs)
@@ -9203,8 +9203,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info1_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info1_regwen_we),
@@ -9212,7 +9212,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9233,20 +9233,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_en_0_qs)
@@ -9259,20 +9259,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_rd_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_rd_en_0_qs)
@@ -9285,20 +9285,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_prog_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_prog_en_0_qs)
@@ -9311,20 +9311,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_erase_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_erase_en_0_qs)
@@ -9337,20 +9337,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_scramble_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_scramble_en_0_qs)
@@ -9363,20 +9363,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_ecc_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_ecc_en_0_qs)
@@ -9389,20 +9389,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info1_page_cfg_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info1_page_cfg_he_en_0_we & bank1_info1_regwen_qs),
.wd (bank1_info1_page_cfg_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info1_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank1_info1_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank1_info1_page_cfg_he_en_0_qs)
@@ -9419,8 +9419,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info2_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info2_regwen_0_we),
@@ -9428,7 +9428,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9446,8 +9446,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank1_info2_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank1_info2_regwen_1_we),
@@ -9455,7 +9455,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9476,20 +9476,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_en_0_qs)
@@ -9502,20 +9502,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_rd_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_rd_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_rd_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].rd_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].rd_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_rd_en_0_qs)
@@ -9528,20 +9528,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_prog_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_prog_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_prog_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].prog_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].prog_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_prog_en_0_qs)
@@ -9554,20 +9554,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_erase_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].erase_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].erase_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_erase_en_0_qs)
@@ -9580,20 +9580,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_scramble_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_scramble_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_scramble_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].scramble_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].scramble_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_scramble_en_0_qs)
@@ -9606,20 +9606,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_ecc_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_ecc_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_ecc_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].ecc_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].ecc_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_ecc_en_0_qs)
@@ -9632,20 +9632,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_0_he_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_0_he_en_0_we & bank1_info2_regwen_0_qs),
.wd (bank1_info2_page_cfg_0_he_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[0].he_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[0].he_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_0_he_en_0_qs)
@@ -9661,20 +9661,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_en_1_qs)
@@ -9687,20 +9687,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_rd_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_rd_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_rd_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].rd_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].rd_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_rd_en_1_qs)
@@ -9713,20 +9713,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_prog_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_prog_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_prog_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].prog_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].prog_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_prog_en_1_qs)
@@ -9739,20 +9739,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_erase_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].erase_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].erase_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_erase_en_1_qs)
@@ -9765,20 +9765,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_scramble_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_scramble_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_scramble_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].scramble_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].scramble_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_scramble_en_1_qs)
@@ -9791,20 +9791,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_ecc_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_ecc_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_ecc_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].ecc_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].ecc_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_ecc_en_1_qs)
@@ -9817,20 +9817,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_bank1_info2_page_cfg_1_he_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (bank1_info2_page_cfg_1_he_en_1_we & bank1_info2_regwen_1_qs),
.wd (bank1_info2_page_cfg_1_he_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.bank1_info2_page_cfg[1].he_en.q ),
+ .q (reg2hw.bank1_info2_page_cfg[1].he_en.q),
// to register interface (read)
.qs (bank1_info2_page_cfg_1_he_en_1_qs)
@@ -9845,8 +9845,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_bank_cfg_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (bank_cfg_regwen_we),
@@ -9854,7 +9854,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9875,20 +9875,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_bank_cfg_erase_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_bank_cfg_erase_en_0_we & bank_cfg_regwen_qs),
.wd (mp_bank_cfg_erase_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_bank_cfg[0].q ),
+ .q (reg2hw.mp_bank_cfg[0].q),
// to register interface (read)
.qs (mp_bank_cfg_erase_en_0_qs)
@@ -9901,20 +9901,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mp_bank_cfg_erase_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mp_bank_cfg_erase_en_1_we & bank_cfg_regwen_qs),
.wd (mp_bank_cfg_erase_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mp_bank_cfg[1].q ),
+ .q (reg2hw.mp_bank_cfg[1].q),
// to register interface (read)
.qs (mp_bank_cfg_erase_en_1_qs)
@@ -9930,8 +9930,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_op_status_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (op_status_done_we),
@@ -9939,7 +9939,7 @@
// from internal hardware
.de (hw2reg.op_status.done.de),
- .d (hw2reg.op_status.done.d ),
+ .d (hw2reg.op_status.done.d),
// to internal hardware
.qe (),
@@ -9956,8 +9956,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_op_status_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (op_status_err_we),
@@ -9965,7 +9965,7 @@
// from internal hardware
.de (hw2reg.op_status.err.de),
- .d (hw2reg.op_status.err.d ),
+ .d (hw2reg.op_status.err.d),
// to internal hardware
.qe (),
@@ -9984,15 +9984,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_rd_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.rd_full.de),
- .d (hw2reg.status.rd_full.d ),
+ .d (hw2reg.status.rd_full.d),
// to internal hardware
.qe (),
@@ -10009,15 +10010,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_status_rd_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.rd_empty.de),
- .d (hw2reg.status.rd_empty.d ),
+ .d (hw2reg.status.rd_empty.d),
// to internal hardware
.qe (),
@@ -10034,15 +10036,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_prog_full (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.prog_full.de),
- .d (hw2reg.status.prog_full.d ),
+ .d (hw2reg.status.prog_full.d),
// to internal hardware
.qe (),
@@ -10059,15 +10062,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_status_prog_empty (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.prog_empty.de),
- .d (hw2reg.status.prog_empty.d ),
+ .d (hw2reg.status.prog_empty.d),
// to internal hardware
.qe (),
@@ -10084,15 +10088,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_init_wip (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.init_wip.de),
- .d (hw2reg.status.init_wip.d ),
+ .d (hw2reg.status.init_wip.d),
// to internal hardware
.qe (),
@@ -10111,8 +10116,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_flash_err_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_flash_err_en_we),
@@ -10120,11 +10125,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.flash_err_en.q ),
+ .q (reg2hw.err_code_intr_en.flash_err_en.q),
// to register interface (read)
.qs (err_code_intr_en_flash_err_en_qs)
@@ -10137,8 +10142,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_flash_alert_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_flash_alert_en_we),
@@ -10146,11 +10151,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.flash_alert_en.q ),
+ .q (reg2hw.err_code_intr_en.flash_alert_en.q),
// to register interface (read)
.qs (err_code_intr_en_flash_alert_en_qs)
@@ -10163,8 +10168,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_mp_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_mp_err_we),
@@ -10172,11 +10177,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.mp_err.q ),
+ .q (reg2hw.err_code_intr_en.mp_err.q),
// to register interface (read)
.qs (err_code_intr_en_mp_err_qs)
@@ -10189,8 +10194,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_ecc_single_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_ecc_single_err_we),
@@ -10198,11 +10203,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.ecc_single_err.q ),
+ .q (reg2hw.err_code_intr_en.ecc_single_err.q),
// to register interface (read)
.qs (err_code_intr_en_ecc_single_err_qs)
@@ -10215,8 +10220,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_err_code_intr_en_ecc_multi_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_intr_en_ecc_multi_err_we),
@@ -10224,11 +10229,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.err_code_intr_en.ecc_multi_err.q ),
+ .q (reg2hw.err_code_intr_en.ecc_multi_err.q),
// to register interface (read)
.qs (err_code_intr_en_ecc_multi_err_qs)
@@ -10243,8 +10248,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_flash_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_flash_err_we),
@@ -10252,11 +10257,11 @@
// from internal hardware
.de (hw2reg.err_code.flash_err.de),
- .d (hw2reg.err_code.flash_err.d ),
+ .d (hw2reg.err_code.flash_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.flash_err.q ),
+ .q (reg2hw.err_code.flash_err.q),
// to register interface (read)
.qs (err_code_flash_err_qs)
@@ -10269,8 +10274,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_flash_alert (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_flash_alert_we),
@@ -10278,11 +10283,11 @@
// from internal hardware
.de (hw2reg.err_code.flash_alert.de),
- .d (hw2reg.err_code.flash_alert.d ),
+ .d (hw2reg.err_code.flash_alert.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.flash_alert.q ),
+ .q (reg2hw.err_code.flash_alert.q),
// to register interface (read)
.qs (err_code_flash_alert_qs)
@@ -10295,8 +10300,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_mp_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_mp_err_we),
@@ -10304,11 +10309,11 @@
// from internal hardware
.de (hw2reg.err_code.mp_err.de),
- .d (hw2reg.err_code.mp_err.d ),
+ .d (hw2reg.err_code.mp_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.mp_err.q ),
+ .q (reg2hw.err_code.mp_err.q),
// to register interface (read)
.qs (err_code_mp_err_qs)
@@ -10321,8 +10326,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_ecc_single_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_ecc_single_err_we),
@@ -10330,11 +10335,11 @@
// from internal hardware
.de (hw2reg.err_code.ecc_single_err.de),
- .d (hw2reg.err_code.ecc_single_err.d ),
+ .d (hw2reg.err_code.ecc_single_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.ecc_single_err.q ),
+ .q (reg2hw.err_code.ecc_single_err.q),
// to register interface (read)
.qs (err_code_ecc_single_err_qs)
@@ -10347,8 +10352,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_err_code_ecc_multi_err (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (err_code_ecc_multi_err_we),
@@ -10356,11 +10361,11 @@
// from internal hardware
.de (hw2reg.err_code.ecc_multi_err.de),
- .d (hw2reg.err_code.ecc_multi_err.d ),
+ .d (hw2reg.err_code.ecc_multi_err.d),
// to internal hardware
.qe (),
- .q (reg2hw.err_code.ecc_multi_err.q ),
+ .q (reg2hw.err_code.ecc_multi_err.q),
// to register interface (read)
.qs (err_code_ecc_multi_err_qs)
@@ -10374,15 +10379,16 @@
.SWACCESS("RO"),
.RESVAL (9'h0)
) u_err_addr (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.err_addr.de),
- .d (hw2reg.err_addr.d ),
+ .d (hw2reg.err_addr.d),
// to internal hardware
.qe (),
@@ -10400,8 +10406,8 @@
.SWACCESS("W1C"),
.RESVAL (8'h0)
) u_ecc_single_err_cnt (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ecc_single_err_cnt_we),
@@ -10409,11 +10415,11 @@
// from internal hardware
.de (hw2reg.ecc_single_err_cnt.de),
- .d (hw2reg.ecc_single_err_cnt.d ),
+ .d (hw2reg.ecc_single_err_cnt.d),
// to internal hardware
.qe (),
- .q (reg2hw.ecc_single_err_cnt.q ),
+ .q (reg2hw.ecc_single_err_cnt.q),
// to register interface (read)
.qs (ecc_single_err_cnt_qs)
@@ -10429,15 +10435,16 @@
.SWACCESS("RO"),
.RESVAL (20'h0)
) u_ecc_single_err_addr_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ecc_single_err_addr[0].de),
- .d (hw2reg.ecc_single_err_addr[0].d ),
+ .d (hw2reg.ecc_single_err_addr[0].d),
// to internal hardware
.qe (),
@@ -10455,15 +10462,16 @@
.SWACCESS("RO"),
.RESVAL (20'h0)
) u_ecc_single_err_addr_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ecc_single_err_addr[1].de),
- .d (hw2reg.ecc_single_err_addr[1].d ),
+ .d (hw2reg.ecc_single_err_addr[1].d),
// to internal hardware
.qe (),
@@ -10481,8 +10489,8 @@
.SWACCESS("W1C"),
.RESVAL (8'h0)
) u_ecc_multi_err_cnt (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ecc_multi_err_cnt_we),
@@ -10490,11 +10498,11 @@
// from internal hardware
.de (hw2reg.ecc_multi_err_cnt.de),
- .d (hw2reg.ecc_multi_err_cnt.d ),
+ .d (hw2reg.ecc_multi_err_cnt.d),
// to internal hardware
.qe (),
- .q (reg2hw.ecc_multi_err_cnt.q ),
+ .q (reg2hw.ecc_multi_err_cnt.q),
// to register interface (read)
.qs (ecc_multi_err_cnt_qs)
@@ -10510,15 +10518,16 @@
.SWACCESS("RO"),
.RESVAL (20'h0)
) u_ecc_multi_err_addr_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ecc_multi_err_addr[0].de),
- .d (hw2reg.ecc_multi_err_addr[0].d ),
+ .d (hw2reg.ecc_multi_err_addr[0].d),
// to internal hardware
.qe (),
@@ -10536,15 +10545,16 @@
.SWACCESS("RO"),
.RESVAL (20'h0)
) u_ecc_multi_err_addr_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ecc_multi_err_addr[1].de),
- .d (hw2reg.ecc_multi_err_addr[1].d ),
+ .d (hw2reg.ecc_multi_err_addr[1].d),
// to internal hardware
.qe (),
@@ -10562,8 +10572,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_phy_err_cfg_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_err_cfg_regwen_we),
@@ -10571,7 +10581,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10589,20 +10599,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_err_cfg (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (phy_err_cfg_we & phy_err_cfg_regwen_qs),
.wd (phy_err_cfg_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_err_cfg.q ),
+ .q (reg2hw.phy_err_cfg.q),
// to register interface (read)
.qs (phy_err_cfg_qs)
@@ -10617,8 +10627,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_alert_cfg_alert_ack (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_alert_cfg_alert_ack_we),
@@ -10626,11 +10636,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_alert_cfg.alert_ack.q ),
+ .q (reg2hw.phy_alert_cfg.alert_ack.q),
// to register interface (read)
.qs (phy_alert_cfg_alert_ack_qs)
@@ -10643,8 +10653,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_phy_alert_cfg_alert_trig (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (phy_alert_cfg_alert_trig_we),
@@ -10652,11 +10662,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.phy_alert_cfg.alert_trig.q ),
+ .q (reg2hw.phy_alert_cfg.alert_trig.q),
// to register interface (read)
.qs (phy_alert_cfg_alert_trig_qs)
@@ -10671,15 +10681,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_phy_status_init_wip (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.phy_status.init_wip.de),
- .d (hw2reg.phy_status.init_wip.d ),
+ .d (hw2reg.phy_status.init_wip.d),
// to internal hardware
.qe (),
@@ -10696,15 +10707,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_phy_status_prog_normal_avail (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.phy_status.prog_normal_avail.de),
- .d (hw2reg.phy_status.prog_normal_avail.d ),
+ .d (hw2reg.phy_status.prog_normal_avail.d),
// to internal hardware
.qe (),
@@ -10721,15 +10733,16 @@
.SWACCESS("RO"),
.RESVAL (1'h1)
) u_phy_status_prog_repair_avail (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.phy_status.prog_repair_avail.de),
- .d (hw2reg.phy_status.prog_repair_avail.d ),
+ .d (hw2reg.phy_status.prog_repair_avail.d),
// to internal hardware
.qe (),
@@ -10747,8 +10760,8 @@
.SWACCESS("RW"),
.RESVAL (32'h0)
) u_scratch (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (scratch_we),
@@ -10756,11 +10769,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.scratch.q ),
+ .q (reg2hw.scratch.q),
// to register interface (read)
.qs (scratch_qs)
@@ -10775,8 +10788,8 @@
.SWACCESS("RW"),
.RESVAL (5'hf)
) u_fifo_lvl_prog (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_lvl_prog_we),
@@ -10784,11 +10797,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fifo_lvl.prog.q ),
+ .q (reg2hw.fifo_lvl.prog.q),
// to register interface (read)
.qs (fifo_lvl_prog_qs)
@@ -10801,8 +10814,8 @@
.SWACCESS("RW"),
.RESVAL (5'hf)
) u_fifo_lvl_rd (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_lvl_rd_we),
@@ -10810,11 +10823,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fifo_lvl.rd.q ),
+ .q (reg2hw.fifo_lvl.rd.q),
// to register interface (read)
.qs (fifo_lvl_rd_qs)
@@ -10828,8 +10841,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_fifo_rst (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (fifo_rst_we),
@@ -10837,11 +10850,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.fifo_rst.q ),
+ .q (reg2hw.fifo_rst.q),
// to register interface (read)
.qs (fifo_rst_qs)
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
index 37afd2f..9da5bb7 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -2276,8 +2276,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_0_we),
@@ -2285,7 +2285,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2303,8 +2303,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_1_we),
@@ -2312,7 +2312,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2330,8 +2330,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_2_we),
@@ -2339,7 +2339,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2357,8 +2357,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_3_we),
@@ -2366,7 +2366,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2384,8 +2384,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_4_we),
@@ -2393,7 +2393,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2411,8 +2411,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_5_we),
@@ -2420,7 +2420,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2438,8 +2438,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_6_we),
@@ -2447,7 +2447,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2465,8 +2465,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_7_we),
@@ -2474,7 +2474,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2492,8 +2492,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_8_we),
@@ -2501,7 +2501,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2519,8 +2519,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_9_we),
@@ -2528,7 +2528,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2546,8 +2546,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_10_we),
@@ -2555,7 +2555,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2573,8 +2573,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_11_we),
@@ -2582,7 +2582,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2600,8 +2600,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_12_we),
@@ -2609,7 +2609,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2627,8 +2627,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_13_we),
@@ -2636,7 +2636,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2654,8 +2654,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_14_we),
@@ -2663,7 +2663,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2681,8 +2681,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_15_we),
@@ -2690,7 +2690,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2708,8 +2708,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_16_we),
@@ -2717,7 +2717,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2735,8 +2735,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_17_we),
@@ -2744,7 +2744,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2762,8 +2762,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_18_we),
@@ -2771,7 +2771,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2789,8 +2789,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_19_we),
@@ -2798,7 +2798,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2816,8 +2816,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_20_we),
@@ -2825,7 +2825,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2843,8 +2843,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_21_we),
@@ -2852,7 +2852,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2870,8 +2870,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_22_we),
@@ -2879,7 +2879,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2897,8 +2897,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_23_we),
@@ -2906,7 +2906,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2924,8 +2924,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_24_we),
@@ -2933,7 +2933,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2951,8 +2951,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_25_we),
@@ -2960,7 +2960,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -2978,8 +2978,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_26_we),
@@ -2987,7 +2987,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3005,8 +3005,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_27_we),
@@ -3014,7 +3014,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3032,8 +3032,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_28_we),
@@ -3041,7 +3041,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3059,8 +3059,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_29_we),
@@ -3068,7 +3068,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3086,8 +3086,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_30_we),
@@ -3095,7 +3095,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3113,8 +3113,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_31_we),
@@ -3122,7 +3122,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3140,8 +3140,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_32_we),
@@ -3149,7 +3149,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3167,8 +3167,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_33_we),
@@ -3176,7 +3176,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3194,8 +3194,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_34_we),
@@ -3203,7 +3203,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3221,8 +3221,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_35_we),
@@ -3230,7 +3230,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3248,8 +3248,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_36_we),
@@ -3257,7 +3257,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3275,8 +3275,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_37_we),
@@ -3284,7 +3284,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3302,8 +3302,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_38_we),
@@ -3311,7 +3311,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3329,8 +3329,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_39_we),
@@ -3338,7 +3338,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3356,8 +3356,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_40_we),
@@ -3365,7 +3365,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3383,8 +3383,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_41_we),
@@ -3392,7 +3392,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3410,8 +3410,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_42_we),
@@ -3419,7 +3419,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3437,8 +3437,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_43_we),
@@ -3446,7 +3446,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3464,8 +3464,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_44_we),
@@ -3473,7 +3473,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3491,8 +3491,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_45_we),
@@ -3500,7 +3500,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3518,8 +3518,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_46_we),
@@ -3527,7 +3527,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3545,8 +3545,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_47 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_47_we),
@@ -3554,7 +3554,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3572,8 +3572,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_48 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_48_we),
@@ -3581,7 +3581,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3599,8 +3599,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_49 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_49_we),
@@ -3608,7 +3608,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3626,8 +3626,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_50 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_50_we),
@@ -3635,7 +3635,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3653,8 +3653,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_51 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_51_we),
@@ -3662,7 +3662,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3680,8 +3680,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_52_we),
@@ -3689,7 +3689,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3707,8 +3707,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_53_we),
@@ -3716,7 +3716,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3734,8 +3734,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_periph_insel_regwen_54 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_periph_insel_regwen_54_we),
@@ -3743,7 +3743,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -3763,20 +3763,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs),
.wd (mio_periph_insel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[0].q ),
+ .q (reg2hw.mio_periph_insel[0].q),
// to register interface (read)
.qs (mio_periph_insel_0_qs)
@@ -3790,20 +3790,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs),
.wd (mio_periph_insel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[1].q ),
+ .q (reg2hw.mio_periph_insel[1].q),
// to register interface (read)
.qs (mio_periph_insel_1_qs)
@@ -3817,20 +3817,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs),
.wd (mio_periph_insel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[2].q ),
+ .q (reg2hw.mio_periph_insel[2].q),
// to register interface (read)
.qs (mio_periph_insel_2_qs)
@@ -3844,20 +3844,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs),
.wd (mio_periph_insel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[3].q ),
+ .q (reg2hw.mio_periph_insel[3].q),
// to register interface (read)
.qs (mio_periph_insel_3_qs)
@@ -3871,20 +3871,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_4_we & mio_periph_insel_regwen_4_qs),
.wd (mio_periph_insel_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[4].q ),
+ .q (reg2hw.mio_periph_insel[4].q),
// to register interface (read)
.qs (mio_periph_insel_4_qs)
@@ -3898,20 +3898,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_5_we & mio_periph_insel_regwen_5_qs),
.wd (mio_periph_insel_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[5].q ),
+ .q (reg2hw.mio_periph_insel[5].q),
// to register interface (read)
.qs (mio_periph_insel_5_qs)
@@ -3925,20 +3925,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_6_we & mio_periph_insel_regwen_6_qs),
.wd (mio_periph_insel_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[6].q ),
+ .q (reg2hw.mio_periph_insel[6].q),
// to register interface (read)
.qs (mio_periph_insel_6_qs)
@@ -3952,20 +3952,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_7_we & mio_periph_insel_regwen_7_qs),
.wd (mio_periph_insel_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[7].q ),
+ .q (reg2hw.mio_periph_insel[7].q),
// to register interface (read)
.qs (mio_periph_insel_7_qs)
@@ -3979,20 +3979,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_8_we & mio_periph_insel_regwen_8_qs),
.wd (mio_periph_insel_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[8].q ),
+ .q (reg2hw.mio_periph_insel[8].q),
// to register interface (read)
.qs (mio_periph_insel_8_qs)
@@ -4006,20 +4006,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_9_we & mio_periph_insel_regwen_9_qs),
.wd (mio_periph_insel_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[9].q ),
+ .q (reg2hw.mio_periph_insel[9].q),
// to register interface (read)
.qs (mio_periph_insel_9_qs)
@@ -4033,20 +4033,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_10_we & mio_periph_insel_regwen_10_qs),
.wd (mio_periph_insel_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[10].q ),
+ .q (reg2hw.mio_periph_insel[10].q),
// to register interface (read)
.qs (mio_periph_insel_10_qs)
@@ -4060,20 +4060,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_11_we & mio_periph_insel_regwen_11_qs),
.wd (mio_periph_insel_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[11].q ),
+ .q (reg2hw.mio_periph_insel[11].q),
// to register interface (read)
.qs (mio_periph_insel_11_qs)
@@ -4087,20 +4087,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_12_we & mio_periph_insel_regwen_12_qs),
.wd (mio_periph_insel_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[12].q ),
+ .q (reg2hw.mio_periph_insel[12].q),
// to register interface (read)
.qs (mio_periph_insel_12_qs)
@@ -4114,20 +4114,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_13_we & mio_periph_insel_regwen_13_qs),
.wd (mio_periph_insel_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[13].q ),
+ .q (reg2hw.mio_periph_insel[13].q),
// to register interface (read)
.qs (mio_periph_insel_13_qs)
@@ -4141,20 +4141,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_14_we & mio_periph_insel_regwen_14_qs),
.wd (mio_periph_insel_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[14].q ),
+ .q (reg2hw.mio_periph_insel[14].q),
// to register interface (read)
.qs (mio_periph_insel_14_qs)
@@ -4168,20 +4168,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_15_we & mio_periph_insel_regwen_15_qs),
.wd (mio_periph_insel_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[15].q ),
+ .q (reg2hw.mio_periph_insel[15].q),
// to register interface (read)
.qs (mio_periph_insel_15_qs)
@@ -4195,20 +4195,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_16_we & mio_periph_insel_regwen_16_qs),
.wd (mio_periph_insel_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[16].q ),
+ .q (reg2hw.mio_periph_insel[16].q),
// to register interface (read)
.qs (mio_periph_insel_16_qs)
@@ -4222,20 +4222,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_17_we & mio_periph_insel_regwen_17_qs),
.wd (mio_periph_insel_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[17].q ),
+ .q (reg2hw.mio_periph_insel[17].q),
// to register interface (read)
.qs (mio_periph_insel_17_qs)
@@ -4249,20 +4249,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_18_we & mio_periph_insel_regwen_18_qs),
.wd (mio_periph_insel_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[18].q ),
+ .q (reg2hw.mio_periph_insel[18].q),
// to register interface (read)
.qs (mio_periph_insel_18_qs)
@@ -4276,20 +4276,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_19_we & mio_periph_insel_regwen_19_qs),
.wd (mio_periph_insel_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[19].q ),
+ .q (reg2hw.mio_periph_insel[19].q),
// to register interface (read)
.qs (mio_periph_insel_19_qs)
@@ -4303,20 +4303,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_20_we & mio_periph_insel_regwen_20_qs),
.wd (mio_periph_insel_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[20].q ),
+ .q (reg2hw.mio_periph_insel[20].q),
// to register interface (read)
.qs (mio_periph_insel_20_qs)
@@ -4330,20 +4330,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_21_we & mio_periph_insel_regwen_21_qs),
.wd (mio_periph_insel_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[21].q ),
+ .q (reg2hw.mio_periph_insel[21].q),
// to register interface (read)
.qs (mio_periph_insel_21_qs)
@@ -4357,20 +4357,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_22_we & mio_periph_insel_regwen_22_qs),
.wd (mio_periph_insel_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[22].q ),
+ .q (reg2hw.mio_periph_insel[22].q),
// to register interface (read)
.qs (mio_periph_insel_22_qs)
@@ -4384,20 +4384,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_23_we & mio_periph_insel_regwen_23_qs),
.wd (mio_periph_insel_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[23].q ),
+ .q (reg2hw.mio_periph_insel[23].q),
// to register interface (read)
.qs (mio_periph_insel_23_qs)
@@ -4411,20 +4411,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_24_we & mio_periph_insel_regwen_24_qs),
.wd (mio_periph_insel_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[24].q ),
+ .q (reg2hw.mio_periph_insel[24].q),
// to register interface (read)
.qs (mio_periph_insel_24_qs)
@@ -4438,20 +4438,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_25_we & mio_periph_insel_regwen_25_qs),
.wd (mio_periph_insel_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[25].q ),
+ .q (reg2hw.mio_periph_insel[25].q),
// to register interface (read)
.qs (mio_periph_insel_25_qs)
@@ -4465,20 +4465,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_26_we & mio_periph_insel_regwen_26_qs),
.wd (mio_periph_insel_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[26].q ),
+ .q (reg2hw.mio_periph_insel[26].q),
// to register interface (read)
.qs (mio_periph_insel_26_qs)
@@ -4492,20 +4492,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_27_we & mio_periph_insel_regwen_27_qs),
.wd (mio_periph_insel_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[27].q ),
+ .q (reg2hw.mio_periph_insel[27].q),
// to register interface (read)
.qs (mio_periph_insel_27_qs)
@@ -4519,20 +4519,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_28_we & mio_periph_insel_regwen_28_qs),
.wd (mio_periph_insel_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[28].q ),
+ .q (reg2hw.mio_periph_insel[28].q),
// to register interface (read)
.qs (mio_periph_insel_28_qs)
@@ -4546,20 +4546,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_29_we & mio_periph_insel_regwen_29_qs),
.wd (mio_periph_insel_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[29].q ),
+ .q (reg2hw.mio_periph_insel[29].q),
// to register interface (read)
.qs (mio_periph_insel_29_qs)
@@ -4573,20 +4573,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_30_we & mio_periph_insel_regwen_30_qs),
.wd (mio_periph_insel_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[30].q ),
+ .q (reg2hw.mio_periph_insel[30].q),
// to register interface (read)
.qs (mio_periph_insel_30_qs)
@@ -4600,20 +4600,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_31_we & mio_periph_insel_regwen_31_qs),
.wd (mio_periph_insel_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[31].q ),
+ .q (reg2hw.mio_periph_insel[31].q),
// to register interface (read)
.qs (mio_periph_insel_31_qs)
@@ -4627,20 +4627,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_32_we & mio_periph_insel_regwen_32_qs),
.wd (mio_periph_insel_32_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[32].q ),
+ .q (reg2hw.mio_periph_insel[32].q),
// to register interface (read)
.qs (mio_periph_insel_32_qs)
@@ -4654,20 +4654,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_33_we & mio_periph_insel_regwen_33_qs),
.wd (mio_periph_insel_33_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[33].q ),
+ .q (reg2hw.mio_periph_insel[33].q),
// to register interface (read)
.qs (mio_periph_insel_33_qs)
@@ -4681,20 +4681,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_34_we & mio_periph_insel_regwen_34_qs),
.wd (mio_periph_insel_34_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[34].q ),
+ .q (reg2hw.mio_periph_insel[34].q),
// to register interface (read)
.qs (mio_periph_insel_34_qs)
@@ -4708,20 +4708,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_35_we & mio_periph_insel_regwen_35_qs),
.wd (mio_periph_insel_35_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[35].q ),
+ .q (reg2hw.mio_periph_insel[35].q),
// to register interface (read)
.qs (mio_periph_insel_35_qs)
@@ -4735,20 +4735,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_36_we & mio_periph_insel_regwen_36_qs),
.wd (mio_periph_insel_36_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[36].q ),
+ .q (reg2hw.mio_periph_insel[36].q),
// to register interface (read)
.qs (mio_periph_insel_36_qs)
@@ -4762,20 +4762,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_37_we & mio_periph_insel_regwen_37_qs),
.wd (mio_periph_insel_37_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[37].q ),
+ .q (reg2hw.mio_periph_insel[37].q),
// to register interface (read)
.qs (mio_periph_insel_37_qs)
@@ -4789,20 +4789,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_38_we & mio_periph_insel_regwen_38_qs),
.wd (mio_periph_insel_38_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[38].q ),
+ .q (reg2hw.mio_periph_insel[38].q),
// to register interface (read)
.qs (mio_periph_insel_38_qs)
@@ -4816,20 +4816,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_39_we & mio_periph_insel_regwen_39_qs),
.wd (mio_periph_insel_39_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[39].q ),
+ .q (reg2hw.mio_periph_insel[39].q),
// to register interface (read)
.qs (mio_periph_insel_39_qs)
@@ -4843,20 +4843,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_40_we & mio_periph_insel_regwen_40_qs),
.wd (mio_periph_insel_40_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[40].q ),
+ .q (reg2hw.mio_periph_insel[40].q),
// to register interface (read)
.qs (mio_periph_insel_40_qs)
@@ -4870,20 +4870,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_41_we & mio_periph_insel_regwen_41_qs),
.wd (mio_periph_insel_41_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[41].q ),
+ .q (reg2hw.mio_periph_insel[41].q),
// to register interface (read)
.qs (mio_periph_insel_41_qs)
@@ -4897,20 +4897,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_42_we & mio_periph_insel_regwen_42_qs),
.wd (mio_periph_insel_42_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[42].q ),
+ .q (reg2hw.mio_periph_insel[42].q),
// to register interface (read)
.qs (mio_periph_insel_42_qs)
@@ -4924,20 +4924,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_43_we & mio_periph_insel_regwen_43_qs),
.wd (mio_periph_insel_43_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[43].q ),
+ .q (reg2hw.mio_periph_insel[43].q),
// to register interface (read)
.qs (mio_periph_insel_43_qs)
@@ -4951,20 +4951,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_44_we & mio_periph_insel_regwen_44_qs),
.wd (mio_periph_insel_44_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[44].q ),
+ .q (reg2hw.mio_periph_insel[44].q),
// to register interface (read)
.qs (mio_periph_insel_44_qs)
@@ -4978,20 +4978,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_45_we & mio_periph_insel_regwen_45_qs),
.wd (mio_periph_insel_45_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[45].q ),
+ .q (reg2hw.mio_periph_insel[45].q),
// to register interface (read)
.qs (mio_periph_insel_45_qs)
@@ -5005,20 +5005,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_46_we & mio_periph_insel_regwen_46_qs),
.wd (mio_periph_insel_46_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[46].q ),
+ .q (reg2hw.mio_periph_insel[46].q),
// to register interface (read)
.qs (mio_periph_insel_46_qs)
@@ -5032,20 +5032,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_47 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_47_we & mio_periph_insel_regwen_47_qs),
.wd (mio_periph_insel_47_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[47].q ),
+ .q (reg2hw.mio_periph_insel[47].q),
// to register interface (read)
.qs (mio_periph_insel_47_qs)
@@ -5059,20 +5059,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_48 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_48_we & mio_periph_insel_regwen_48_qs),
.wd (mio_periph_insel_48_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[48].q ),
+ .q (reg2hw.mio_periph_insel[48].q),
// to register interface (read)
.qs (mio_periph_insel_48_qs)
@@ -5086,20 +5086,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_49 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_49_we & mio_periph_insel_regwen_49_qs),
.wd (mio_periph_insel_49_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[49].q ),
+ .q (reg2hw.mio_periph_insel[49].q),
// to register interface (read)
.qs (mio_periph_insel_49_qs)
@@ -5113,20 +5113,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_50 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_50_we & mio_periph_insel_regwen_50_qs),
.wd (mio_periph_insel_50_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[50].q ),
+ .q (reg2hw.mio_periph_insel[50].q),
// to register interface (read)
.qs (mio_periph_insel_50_qs)
@@ -5140,20 +5140,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_51 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_51_we & mio_periph_insel_regwen_51_qs),
.wd (mio_periph_insel_51_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[51].q ),
+ .q (reg2hw.mio_periph_insel[51].q),
// to register interface (read)
.qs (mio_periph_insel_51_qs)
@@ -5167,20 +5167,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_52_we & mio_periph_insel_regwen_52_qs),
.wd (mio_periph_insel_52_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[52].q ),
+ .q (reg2hw.mio_periph_insel[52].q),
// to register interface (read)
.qs (mio_periph_insel_52_qs)
@@ -5194,20 +5194,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_53_we & mio_periph_insel_regwen_53_qs),
.wd (mio_periph_insel_53_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[53].q ),
+ .q (reg2hw.mio_periph_insel[53].q),
// to register interface (read)
.qs (mio_periph_insel_53_qs)
@@ -5221,20 +5221,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_mio_periph_insel_54 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_periph_insel_54_we & mio_periph_insel_regwen_54_qs),
.wd (mio_periph_insel_54_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_periph_insel[54].q ),
+ .q (reg2hw.mio_periph_insel[54].q),
// to register interface (read)
.qs (mio_periph_insel_54_qs)
@@ -5250,8 +5250,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_0_we),
@@ -5259,7 +5259,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5277,8 +5277,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_1_we),
@@ -5286,7 +5286,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5304,8 +5304,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_2_we),
@@ -5313,7 +5313,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5331,8 +5331,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_3_we),
@@ -5340,7 +5340,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5358,8 +5358,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_4_we),
@@ -5367,7 +5367,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5385,8 +5385,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_5_we),
@@ -5394,7 +5394,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5412,8 +5412,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_6_we),
@@ -5421,7 +5421,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5439,8 +5439,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_7_we),
@@ -5448,7 +5448,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5466,8 +5466,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_8_we),
@@ -5475,7 +5475,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5493,8 +5493,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_9_we),
@@ -5502,7 +5502,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5520,8 +5520,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_10_we),
@@ -5529,7 +5529,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5547,8 +5547,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_11_we),
@@ -5556,7 +5556,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5574,8 +5574,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_12_we),
@@ -5583,7 +5583,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5601,8 +5601,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_13_we),
@@ -5610,7 +5610,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5628,8 +5628,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_14_we),
@@ -5637,7 +5637,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5655,8 +5655,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_15_we),
@@ -5664,7 +5664,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5682,8 +5682,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_16_we),
@@ -5691,7 +5691,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5709,8 +5709,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_17_we),
@@ -5718,7 +5718,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5736,8 +5736,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_18_we),
@@ -5745,7 +5745,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5763,8 +5763,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_19_we),
@@ -5772,7 +5772,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5790,8 +5790,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_20_we),
@@ -5799,7 +5799,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5817,8 +5817,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_21_we),
@@ -5826,7 +5826,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5844,8 +5844,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_22_we),
@@ -5853,7 +5853,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5871,8 +5871,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_23_we),
@@ -5880,7 +5880,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5898,8 +5898,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_24_we),
@@ -5907,7 +5907,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5925,8 +5925,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_25_we),
@@ -5934,7 +5934,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5952,8 +5952,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_26_we),
@@ -5961,7 +5961,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -5979,8 +5979,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_27_we),
@@ -5988,7 +5988,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6006,8 +6006,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_28_we),
@@ -6015,7 +6015,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6033,8 +6033,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_29_we),
@@ -6042,7 +6042,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6060,8 +6060,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_30_we),
@@ -6069,7 +6069,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6087,8 +6087,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_31_we),
@@ -6096,7 +6096,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6114,8 +6114,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_32_we),
@@ -6123,7 +6123,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6141,8 +6141,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_33_we),
@@ -6150,7 +6150,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6168,8 +6168,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_34_we),
@@ -6177,7 +6177,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6195,8 +6195,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_35_we),
@@ -6204,7 +6204,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6222,8 +6222,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_36_we),
@@ -6231,7 +6231,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6249,8 +6249,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_37_we),
@@ -6258,7 +6258,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6276,8 +6276,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_38_we),
@@ -6285,7 +6285,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6303,8 +6303,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_39_we),
@@ -6312,7 +6312,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6330,8 +6330,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_40_we),
@@ -6339,7 +6339,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6357,8 +6357,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_41_we),
@@ -6366,7 +6366,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6384,8 +6384,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_42_we),
@@ -6393,7 +6393,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6411,8 +6411,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_43_we),
@@ -6420,7 +6420,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6438,8 +6438,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_44_we),
@@ -6447,7 +6447,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6465,8 +6465,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_45_we),
@@ -6474,7 +6474,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6492,8 +6492,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_outsel_regwen_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_outsel_regwen_46_we),
@@ -6501,7 +6501,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -6521,20 +6521,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_0_we & mio_outsel_regwen_0_qs),
.wd (mio_outsel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[0].q ),
+ .q (reg2hw.mio_outsel[0].q),
// to register interface (read)
.qs (mio_outsel_0_qs)
@@ -6548,20 +6548,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_1_we & mio_outsel_regwen_1_qs),
.wd (mio_outsel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[1].q ),
+ .q (reg2hw.mio_outsel[1].q),
// to register interface (read)
.qs (mio_outsel_1_qs)
@@ -6575,20 +6575,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_2_we & mio_outsel_regwen_2_qs),
.wd (mio_outsel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[2].q ),
+ .q (reg2hw.mio_outsel[2].q),
// to register interface (read)
.qs (mio_outsel_2_qs)
@@ -6602,20 +6602,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_3_we & mio_outsel_regwen_3_qs),
.wd (mio_outsel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[3].q ),
+ .q (reg2hw.mio_outsel[3].q),
// to register interface (read)
.qs (mio_outsel_3_qs)
@@ -6629,20 +6629,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_4_we & mio_outsel_regwen_4_qs),
.wd (mio_outsel_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[4].q ),
+ .q (reg2hw.mio_outsel[4].q),
// to register interface (read)
.qs (mio_outsel_4_qs)
@@ -6656,20 +6656,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_5_we & mio_outsel_regwen_5_qs),
.wd (mio_outsel_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[5].q ),
+ .q (reg2hw.mio_outsel[5].q),
// to register interface (read)
.qs (mio_outsel_5_qs)
@@ -6683,20 +6683,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_6_we & mio_outsel_regwen_6_qs),
.wd (mio_outsel_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[6].q ),
+ .q (reg2hw.mio_outsel[6].q),
// to register interface (read)
.qs (mio_outsel_6_qs)
@@ -6710,20 +6710,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_7_we & mio_outsel_regwen_7_qs),
.wd (mio_outsel_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[7].q ),
+ .q (reg2hw.mio_outsel[7].q),
// to register interface (read)
.qs (mio_outsel_7_qs)
@@ -6737,20 +6737,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_8_we & mio_outsel_regwen_8_qs),
.wd (mio_outsel_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[8].q ),
+ .q (reg2hw.mio_outsel[8].q),
// to register interface (read)
.qs (mio_outsel_8_qs)
@@ -6764,20 +6764,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_9_we & mio_outsel_regwen_9_qs),
.wd (mio_outsel_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[9].q ),
+ .q (reg2hw.mio_outsel[9].q),
// to register interface (read)
.qs (mio_outsel_9_qs)
@@ -6791,20 +6791,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_10_we & mio_outsel_regwen_10_qs),
.wd (mio_outsel_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[10].q ),
+ .q (reg2hw.mio_outsel[10].q),
// to register interface (read)
.qs (mio_outsel_10_qs)
@@ -6818,20 +6818,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_11_we & mio_outsel_regwen_11_qs),
.wd (mio_outsel_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[11].q ),
+ .q (reg2hw.mio_outsel[11].q),
// to register interface (read)
.qs (mio_outsel_11_qs)
@@ -6845,20 +6845,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_12_we & mio_outsel_regwen_12_qs),
.wd (mio_outsel_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[12].q ),
+ .q (reg2hw.mio_outsel[12].q),
// to register interface (read)
.qs (mio_outsel_12_qs)
@@ -6872,20 +6872,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_13_we & mio_outsel_regwen_13_qs),
.wd (mio_outsel_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[13].q ),
+ .q (reg2hw.mio_outsel[13].q),
// to register interface (read)
.qs (mio_outsel_13_qs)
@@ -6899,20 +6899,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_14_we & mio_outsel_regwen_14_qs),
.wd (mio_outsel_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[14].q ),
+ .q (reg2hw.mio_outsel[14].q),
// to register interface (read)
.qs (mio_outsel_14_qs)
@@ -6926,20 +6926,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_15_we & mio_outsel_regwen_15_qs),
.wd (mio_outsel_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[15].q ),
+ .q (reg2hw.mio_outsel[15].q),
// to register interface (read)
.qs (mio_outsel_15_qs)
@@ -6953,20 +6953,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_16_we & mio_outsel_regwen_16_qs),
.wd (mio_outsel_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[16].q ),
+ .q (reg2hw.mio_outsel[16].q),
// to register interface (read)
.qs (mio_outsel_16_qs)
@@ -6980,20 +6980,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_17_we & mio_outsel_regwen_17_qs),
.wd (mio_outsel_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[17].q ),
+ .q (reg2hw.mio_outsel[17].q),
// to register interface (read)
.qs (mio_outsel_17_qs)
@@ -7007,20 +7007,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_18_we & mio_outsel_regwen_18_qs),
.wd (mio_outsel_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[18].q ),
+ .q (reg2hw.mio_outsel[18].q),
// to register interface (read)
.qs (mio_outsel_18_qs)
@@ -7034,20 +7034,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_19_we & mio_outsel_regwen_19_qs),
.wd (mio_outsel_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[19].q ),
+ .q (reg2hw.mio_outsel[19].q),
// to register interface (read)
.qs (mio_outsel_19_qs)
@@ -7061,20 +7061,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_20_we & mio_outsel_regwen_20_qs),
.wd (mio_outsel_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[20].q ),
+ .q (reg2hw.mio_outsel[20].q),
// to register interface (read)
.qs (mio_outsel_20_qs)
@@ -7088,20 +7088,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_21_we & mio_outsel_regwen_21_qs),
.wd (mio_outsel_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[21].q ),
+ .q (reg2hw.mio_outsel[21].q),
// to register interface (read)
.qs (mio_outsel_21_qs)
@@ -7115,20 +7115,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_22_we & mio_outsel_regwen_22_qs),
.wd (mio_outsel_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[22].q ),
+ .q (reg2hw.mio_outsel[22].q),
// to register interface (read)
.qs (mio_outsel_22_qs)
@@ -7142,20 +7142,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_23_we & mio_outsel_regwen_23_qs),
.wd (mio_outsel_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[23].q ),
+ .q (reg2hw.mio_outsel[23].q),
// to register interface (read)
.qs (mio_outsel_23_qs)
@@ -7169,20 +7169,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_24_we & mio_outsel_regwen_24_qs),
.wd (mio_outsel_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[24].q ),
+ .q (reg2hw.mio_outsel[24].q),
// to register interface (read)
.qs (mio_outsel_24_qs)
@@ -7196,20 +7196,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_25_we & mio_outsel_regwen_25_qs),
.wd (mio_outsel_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[25].q ),
+ .q (reg2hw.mio_outsel[25].q),
// to register interface (read)
.qs (mio_outsel_25_qs)
@@ -7223,20 +7223,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_26_we & mio_outsel_regwen_26_qs),
.wd (mio_outsel_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[26].q ),
+ .q (reg2hw.mio_outsel[26].q),
// to register interface (read)
.qs (mio_outsel_26_qs)
@@ -7250,20 +7250,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_27_we & mio_outsel_regwen_27_qs),
.wd (mio_outsel_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[27].q ),
+ .q (reg2hw.mio_outsel[27].q),
// to register interface (read)
.qs (mio_outsel_27_qs)
@@ -7277,20 +7277,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_28_we & mio_outsel_regwen_28_qs),
.wd (mio_outsel_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[28].q ),
+ .q (reg2hw.mio_outsel[28].q),
// to register interface (read)
.qs (mio_outsel_28_qs)
@@ -7304,20 +7304,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_29_we & mio_outsel_regwen_29_qs),
.wd (mio_outsel_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[29].q ),
+ .q (reg2hw.mio_outsel[29].q),
// to register interface (read)
.qs (mio_outsel_29_qs)
@@ -7331,20 +7331,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_30_we & mio_outsel_regwen_30_qs),
.wd (mio_outsel_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[30].q ),
+ .q (reg2hw.mio_outsel[30].q),
// to register interface (read)
.qs (mio_outsel_30_qs)
@@ -7358,20 +7358,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_31_we & mio_outsel_regwen_31_qs),
.wd (mio_outsel_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[31].q ),
+ .q (reg2hw.mio_outsel[31].q),
// to register interface (read)
.qs (mio_outsel_31_qs)
@@ -7385,20 +7385,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_32_we & mio_outsel_regwen_32_qs),
.wd (mio_outsel_32_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[32].q ),
+ .q (reg2hw.mio_outsel[32].q),
// to register interface (read)
.qs (mio_outsel_32_qs)
@@ -7412,20 +7412,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_33_we & mio_outsel_regwen_33_qs),
.wd (mio_outsel_33_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[33].q ),
+ .q (reg2hw.mio_outsel[33].q),
// to register interface (read)
.qs (mio_outsel_33_qs)
@@ -7439,20 +7439,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_34_we & mio_outsel_regwen_34_qs),
.wd (mio_outsel_34_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[34].q ),
+ .q (reg2hw.mio_outsel[34].q),
// to register interface (read)
.qs (mio_outsel_34_qs)
@@ -7466,20 +7466,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_35_we & mio_outsel_regwen_35_qs),
.wd (mio_outsel_35_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[35].q ),
+ .q (reg2hw.mio_outsel[35].q),
// to register interface (read)
.qs (mio_outsel_35_qs)
@@ -7493,20 +7493,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_36_we & mio_outsel_regwen_36_qs),
.wd (mio_outsel_36_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[36].q ),
+ .q (reg2hw.mio_outsel[36].q),
// to register interface (read)
.qs (mio_outsel_36_qs)
@@ -7520,20 +7520,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_37_we & mio_outsel_regwen_37_qs),
.wd (mio_outsel_37_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[37].q ),
+ .q (reg2hw.mio_outsel[37].q),
// to register interface (read)
.qs (mio_outsel_37_qs)
@@ -7547,20 +7547,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_38_we & mio_outsel_regwen_38_qs),
.wd (mio_outsel_38_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[38].q ),
+ .q (reg2hw.mio_outsel[38].q),
// to register interface (read)
.qs (mio_outsel_38_qs)
@@ -7574,20 +7574,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_39_we & mio_outsel_regwen_39_qs),
.wd (mio_outsel_39_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[39].q ),
+ .q (reg2hw.mio_outsel[39].q),
// to register interface (read)
.qs (mio_outsel_39_qs)
@@ -7601,20 +7601,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_40_we & mio_outsel_regwen_40_qs),
.wd (mio_outsel_40_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[40].q ),
+ .q (reg2hw.mio_outsel[40].q),
// to register interface (read)
.qs (mio_outsel_40_qs)
@@ -7628,20 +7628,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_41_we & mio_outsel_regwen_41_qs),
.wd (mio_outsel_41_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[41].q ),
+ .q (reg2hw.mio_outsel[41].q),
// to register interface (read)
.qs (mio_outsel_41_qs)
@@ -7655,20 +7655,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_42_we & mio_outsel_regwen_42_qs),
.wd (mio_outsel_42_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[42].q ),
+ .q (reg2hw.mio_outsel[42].q),
// to register interface (read)
.qs (mio_outsel_42_qs)
@@ -7682,20 +7682,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_43_we & mio_outsel_regwen_43_qs),
.wd (mio_outsel_43_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[43].q ),
+ .q (reg2hw.mio_outsel[43].q),
// to register interface (read)
.qs (mio_outsel_43_qs)
@@ -7709,20 +7709,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_44_we & mio_outsel_regwen_44_qs),
.wd (mio_outsel_44_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[44].q ),
+ .q (reg2hw.mio_outsel[44].q),
// to register interface (read)
.qs (mio_outsel_44_qs)
@@ -7736,20 +7736,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_45_we & mio_outsel_regwen_45_qs),
.wd (mio_outsel_45_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[45].q ),
+ .q (reg2hw.mio_outsel[45].q),
// to register interface (read)
.qs (mio_outsel_45_qs)
@@ -7763,20 +7763,20 @@
.SWACCESS("RW"),
.RESVAL (7'h2)
) u_mio_outsel_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_outsel_46_we & mio_outsel_regwen_46_qs),
.wd (mio_outsel_46_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_outsel[46].q ),
+ .q (reg2hw.mio_outsel[46].q),
// to register interface (read)
.qs (mio_outsel_46_qs)
@@ -7792,8 +7792,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_0_we),
@@ -7801,7 +7801,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7819,8 +7819,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_1_we),
@@ -7828,7 +7828,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7846,8 +7846,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_2_we),
@@ -7855,7 +7855,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7873,8 +7873,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_3_we),
@@ -7882,7 +7882,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7900,8 +7900,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_4_we),
@@ -7909,7 +7909,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7927,8 +7927,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_5_we),
@@ -7936,7 +7936,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7954,8 +7954,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_6_we),
@@ -7963,7 +7963,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -7981,8 +7981,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_7_we),
@@ -7990,7 +7990,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8008,8 +8008,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_8_we),
@@ -8017,7 +8017,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8035,8 +8035,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_9_we),
@@ -8044,7 +8044,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8062,8 +8062,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_10_we),
@@ -8071,7 +8071,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8089,8 +8089,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_11_we),
@@ -8098,7 +8098,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8116,8 +8116,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_12_we),
@@ -8125,7 +8125,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8143,8 +8143,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_13_we),
@@ -8152,7 +8152,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8170,8 +8170,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_14_we),
@@ -8179,7 +8179,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8197,8 +8197,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_15_we),
@@ -8206,7 +8206,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8224,8 +8224,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_16_we),
@@ -8233,7 +8233,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8251,8 +8251,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_17_we),
@@ -8260,7 +8260,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8278,8 +8278,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_18_we),
@@ -8287,7 +8287,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8305,8 +8305,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_19_we),
@@ -8314,7 +8314,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8332,8 +8332,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_20_we),
@@ -8341,7 +8341,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8359,8 +8359,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_21_we),
@@ -8368,7 +8368,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8386,8 +8386,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_22_we),
@@ -8395,7 +8395,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8413,8 +8413,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_23_we),
@@ -8422,7 +8422,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8440,8 +8440,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_24_we),
@@ -8449,7 +8449,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8467,8 +8467,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_25_we),
@@ -8476,7 +8476,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8494,8 +8494,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_26_we),
@@ -8503,7 +8503,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8521,8 +8521,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_27_we),
@@ -8530,7 +8530,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8548,8 +8548,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_28_we),
@@ -8557,7 +8557,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8575,8 +8575,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_29_we),
@@ -8584,7 +8584,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8602,8 +8602,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_30_we),
@@ -8611,7 +8611,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8629,8 +8629,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_31_we),
@@ -8638,7 +8638,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8656,8 +8656,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_32_we),
@@ -8665,7 +8665,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8683,8 +8683,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_33_we),
@@ -8692,7 +8692,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8710,8 +8710,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_34_we),
@@ -8719,7 +8719,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8737,8 +8737,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_35_we),
@@ -8746,7 +8746,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8764,8 +8764,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_36_we),
@@ -8773,7 +8773,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8791,8 +8791,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_37_we),
@@ -8800,7 +8800,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8818,8 +8818,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_38_we),
@@ -8827,7 +8827,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8845,8 +8845,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_39_we),
@@ -8854,7 +8854,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8872,8 +8872,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_40_we),
@@ -8881,7 +8881,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8899,8 +8899,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_41_we),
@@ -8908,7 +8908,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8926,8 +8926,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_42_we),
@@ -8935,7 +8935,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8953,8 +8953,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_43_we),
@@ -8962,7 +8962,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -8980,8 +8980,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_44_we),
@@ -8989,7 +8989,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9007,8 +9007,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_45_we),
@@ -9016,7 +9016,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9034,8 +9034,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_attr_regwen_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_attr_regwen_46_we),
@@ -9043,7 +9043,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9062,13 +9062,12 @@
.DW (13)
) u_mio_pad_attr_0 (
.re (mio_pad_attr_0_re),
- // qualified with register enable
.we (mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs),
.wd (mio_pad_attr_0_wd),
.d (hw2reg.mio_pad_attr[0].d),
.qre (),
.qe (reg2hw.mio_pad_attr[0].qe),
- .q (reg2hw.mio_pad_attr[0].q ),
+ .q (reg2hw.mio_pad_attr[0].q),
.qs (mio_pad_attr_0_qs)
);
@@ -9079,13 +9078,12 @@
.DW (13)
) u_mio_pad_attr_1 (
.re (mio_pad_attr_1_re),
- // qualified with register enable
.we (mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs),
.wd (mio_pad_attr_1_wd),
.d (hw2reg.mio_pad_attr[1].d),
.qre (),
.qe (reg2hw.mio_pad_attr[1].qe),
- .q (reg2hw.mio_pad_attr[1].q ),
+ .q (reg2hw.mio_pad_attr[1].q),
.qs (mio_pad_attr_1_qs)
);
@@ -9096,13 +9094,12 @@
.DW (13)
) u_mio_pad_attr_2 (
.re (mio_pad_attr_2_re),
- // qualified with register enable
.we (mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs),
.wd (mio_pad_attr_2_wd),
.d (hw2reg.mio_pad_attr[2].d),
.qre (),
.qe (reg2hw.mio_pad_attr[2].qe),
- .q (reg2hw.mio_pad_attr[2].q ),
+ .q (reg2hw.mio_pad_attr[2].q),
.qs (mio_pad_attr_2_qs)
);
@@ -9113,13 +9110,12 @@
.DW (13)
) u_mio_pad_attr_3 (
.re (mio_pad_attr_3_re),
- // qualified with register enable
.we (mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs),
.wd (mio_pad_attr_3_wd),
.d (hw2reg.mio_pad_attr[3].d),
.qre (),
.qe (reg2hw.mio_pad_attr[3].qe),
- .q (reg2hw.mio_pad_attr[3].q ),
+ .q (reg2hw.mio_pad_attr[3].q),
.qs (mio_pad_attr_3_qs)
);
@@ -9130,13 +9126,12 @@
.DW (13)
) u_mio_pad_attr_4 (
.re (mio_pad_attr_4_re),
- // qualified with register enable
.we (mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs),
.wd (mio_pad_attr_4_wd),
.d (hw2reg.mio_pad_attr[4].d),
.qre (),
.qe (reg2hw.mio_pad_attr[4].qe),
- .q (reg2hw.mio_pad_attr[4].q ),
+ .q (reg2hw.mio_pad_attr[4].q),
.qs (mio_pad_attr_4_qs)
);
@@ -9147,13 +9142,12 @@
.DW (13)
) u_mio_pad_attr_5 (
.re (mio_pad_attr_5_re),
- // qualified with register enable
.we (mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs),
.wd (mio_pad_attr_5_wd),
.d (hw2reg.mio_pad_attr[5].d),
.qre (),
.qe (reg2hw.mio_pad_attr[5].qe),
- .q (reg2hw.mio_pad_attr[5].q ),
+ .q (reg2hw.mio_pad_attr[5].q),
.qs (mio_pad_attr_5_qs)
);
@@ -9164,13 +9158,12 @@
.DW (13)
) u_mio_pad_attr_6 (
.re (mio_pad_attr_6_re),
- // qualified with register enable
.we (mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs),
.wd (mio_pad_attr_6_wd),
.d (hw2reg.mio_pad_attr[6].d),
.qre (),
.qe (reg2hw.mio_pad_attr[6].qe),
- .q (reg2hw.mio_pad_attr[6].q ),
+ .q (reg2hw.mio_pad_attr[6].q),
.qs (mio_pad_attr_6_qs)
);
@@ -9181,13 +9174,12 @@
.DW (13)
) u_mio_pad_attr_7 (
.re (mio_pad_attr_7_re),
- // qualified with register enable
.we (mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs),
.wd (mio_pad_attr_7_wd),
.d (hw2reg.mio_pad_attr[7].d),
.qre (),
.qe (reg2hw.mio_pad_attr[7].qe),
- .q (reg2hw.mio_pad_attr[7].q ),
+ .q (reg2hw.mio_pad_attr[7].q),
.qs (mio_pad_attr_7_qs)
);
@@ -9198,13 +9190,12 @@
.DW (13)
) u_mio_pad_attr_8 (
.re (mio_pad_attr_8_re),
- // qualified with register enable
.we (mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs),
.wd (mio_pad_attr_8_wd),
.d (hw2reg.mio_pad_attr[8].d),
.qre (),
.qe (reg2hw.mio_pad_attr[8].qe),
- .q (reg2hw.mio_pad_attr[8].q ),
+ .q (reg2hw.mio_pad_attr[8].q),
.qs (mio_pad_attr_8_qs)
);
@@ -9215,13 +9206,12 @@
.DW (13)
) u_mio_pad_attr_9 (
.re (mio_pad_attr_9_re),
- // qualified with register enable
.we (mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs),
.wd (mio_pad_attr_9_wd),
.d (hw2reg.mio_pad_attr[9].d),
.qre (),
.qe (reg2hw.mio_pad_attr[9].qe),
- .q (reg2hw.mio_pad_attr[9].q ),
+ .q (reg2hw.mio_pad_attr[9].q),
.qs (mio_pad_attr_9_qs)
);
@@ -9232,13 +9222,12 @@
.DW (13)
) u_mio_pad_attr_10 (
.re (mio_pad_attr_10_re),
- // qualified with register enable
.we (mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs),
.wd (mio_pad_attr_10_wd),
.d (hw2reg.mio_pad_attr[10].d),
.qre (),
.qe (reg2hw.mio_pad_attr[10].qe),
- .q (reg2hw.mio_pad_attr[10].q ),
+ .q (reg2hw.mio_pad_attr[10].q),
.qs (mio_pad_attr_10_qs)
);
@@ -9249,13 +9238,12 @@
.DW (13)
) u_mio_pad_attr_11 (
.re (mio_pad_attr_11_re),
- // qualified with register enable
.we (mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs),
.wd (mio_pad_attr_11_wd),
.d (hw2reg.mio_pad_attr[11].d),
.qre (),
.qe (reg2hw.mio_pad_attr[11].qe),
- .q (reg2hw.mio_pad_attr[11].q ),
+ .q (reg2hw.mio_pad_attr[11].q),
.qs (mio_pad_attr_11_qs)
);
@@ -9266,13 +9254,12 @@
.DW (13)
) u_mio_pad_attr_12 (
.re (mio_pad_attr_12_re),
- // qualified with register enable
.we (mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs),
.wd (mio_pad_attr_12_wd),
.d (hw2reg.mio_pad_attr[12].d),
.qre (),
.qe (reg2hw.mio_pad_attr[12].qe),
- .q (reg2hw.mio_pad_attr[12].q ),
+ .q (reg2hw.mio_pad_attr[12].q),
.qs (mio_pad_attr_12_qs)
);
@@ -9283,13 +9270,12 @@
.DW (13)
) u_mio_pad_attr_13 (
.re (mio_pad_attr_13_re),
- // qualified with register enable
.we (mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs),
.wd (mio_pad_attr_13_wd),
.d (hw2reg.mio_pad_attr[13].d),
.qre (),
.qe (reg2hw.mio_pad_attr[13].qe),
- .q (reg2hw.mio_pad_attr[13].q ),
+ .q (reg2hw.mio_pad_attr[13].q),
.qs (mio_pad_attr_13_qs)
);
@@ -9300,13 +9286,12 @@
.DW (13)
) u_mio_pad_attr_14 (
.re (mio_pad_attr_14_re),
- // qualified with register enable
.we (mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs),
.wd (mio_pad_attr_14_wd),
.d (hw2reg.mio_pad_attr[14].d),
.qre (),
.qe (reg2hw.mio_pad_attr[14].qe),
- .q (reg2hw.mio_pad_attr[14].q ),
+ .q (reg2hw.mio_pad_attr[14].q),
.qs (mio_pad_attr_14_qs)
);
@@ -9317,13 +9302,12 @@
.DW (13)
) u_mio_pad_attr_15 (
.re (mio_pad_attr_15_re),
- // qualified with register enable
.we (mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs),
.wd (mio_pad_attr_15_wd),
.d (hw2reg.mio_pad_attr[15].d),
.qre (),
.qe (reg2hw.mio_pad_attr[15].qe),
- .q (reg2hw.mio_pad_attr[15].q ),
+ .q (reg2hw.mio_pad_attr[15].q),
.qs (mio_pad_attr_15_qs)
);
@@ -9334,13 +9318,12 @@
.DW (13)
) u_mio_pad_attr_16 (
.re (mio_pad_attr_16_re),
- // qualified with register enable
.we (mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs),
.wd (mio_pad_attr_16_wd),
.d (hw2reg.mio_pad_attr[16].d),
.qre (),
.qe (reg2hw.mio_pad_attr[16].qe),
- .q (reg2hw.mio_pad_attr[16].q ),
+ .q (reg2hw.mio_pad_attr[16].q),
.qs (mio_pad_attr_16_qs)
);
@@ -9351,13 +9334,12 @@
.DW (13)
) u_mio_pad_attr_17 (
.re (mio_pad_attr_17_re),
- // qualified with register enable
.we (mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs),
.wd (mio_pad_attr_17_wd),
.d (hw2reg.mio_pad_attr[17].d),
.qre (),
.qe (reg2hw.mio_pad_attr[17].qe),
- .q (reg2hw.mio_pad_attr[17].q ),
+ .q (reg2hw.mio_pad_attr[17].q),
.qs (mio_pad_attr_17_qs)
);
@@ -9368,13 +9350,12 @@
.DW (13)
) u_mio_pad_attr_18 (
.re (mio_pad_attr_18_re),
- // qualified with register enable
.we (mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs),
.wd (mio_pad_attr_18_wd),
.d (hw2reg.mio_pad_attr[18].d),
.qre (),
.qe (reg2hw.mio_pad_attr[18].qe),
- .q (reg2hw.mio_pad_attr[18].q ),
+ .q (reg2hw.mio_pad_attr[18].q),
.qs (mio_pad_attr_18_qs)
);
@@ -9385,13 +9366,12 @@
.DW (13)
) u_mio_pad_attr_19 (
.re (mio_pad_attr_19_re),
- // qualified with register enable
.we (mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs),
.wd (mio_pad_attr_19_wd),
.d (hw2reg.mio_pad_attr[19].d),
.qre (),
.qe (reg2hw.mio_pad_attr[19].qe),
- .q (reg2hw.mio_pad_attr[19].q ),
+ .q (reg2hw.mio_pad_attr[19].q),
.qs (mio_pad_attr_19_qs)
);
@@ -9402,13 +9382,12 @@
.DW (13)
) u_mio_pad_attr_20 (
.re (mio_pad_attr_20_re),
- // qualified with register enable
.we (mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs),
.wd (mio_pad_attr_20_wd),
.d (hw2reg.mio_pad_attr[20].d),
.qre (),
.qe (reg2hw.mio_pad_attr[20].qe),
- .q (reg2hw.mio_pad_attr[20].q ),
+ .q (reg2hw.mio_pad_attr[20].q),
.qs (mio_pad_attr_20_qs)
);
@@ -9419,13 +9398,12 @@
.DW (13)
) u_mio_pad_attr_21 (
.re (mio_pad_attr_21_re),
- // qualified with register enable
.we (mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs),
.wd (mio_pad_attr_21_wd),
.d (hw2reg.mio_pad_attr[21].d),
.qre (),
.qe (reg2hw.mio_pad_attr[21].qe),
- .q (reg2hw.mio_pad_attr[21].q ),
+ .q (reg2hw.mio_pad_attr[21].q),
.qs (mio_pad_attr_21_qs)
);
@@ -9436,13 +9414,12 @@
.DW (13)
) u_mio_pad_attr_22 (
.re (mio_pad_attr_22_re),
- // qualified with register enable
.we (mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs),
.wd (mio_pad_attr_22_wd),
.d (hw2reg.mio_pad_attr[22].d),
.qre (),
.qe (reg2hw.mio_pad_attr[22].qe),
- .q (reg2hw.mio_pad_attr[22].q ),
+ .q (reg2hw.mio_pad_attr[22].q),
.qs (mio_pad_attr_22_qs)
);
@@ -9453,13 +9430,12 @@
.DW (13)
) u_mio_pad_attr_23 (
.re (mio_pad_attr_23_re),
- // qualified with register enable
.we (mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs),
.wd (mio_pad_attr_23_wd),
.d (hw2reg.mio_pad_attr[23].d),
.qre (),
.qe (reg2hw.mio_pad_attr[23].qe),
- .q (reg2hw.mio_pad_attr[23].q ),
+ .q (reg2hw.mio_pad_attr[23].q),
.qs (mio_pad_attr_23_qs)
);
@@ -9470,13 +9446,12 @@
.DW (13)
) u_mio_pad_attr_24 (
.re (mio_pad_attr_24_re),
- // qualified with register enable
.we (mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs),
.wd (mio_pad_attr_24_wd),
.d (hw2reg.mio_pad_attr[24].d),
.qre (),
.qe (reg2hw.mio_pad_attr[24].qe),
- .q (reg2hw.mio_pad_attr[24].q ),
+ .q (reg2hw.mio_pad_attr[24].q),
.qs (mio_pad_attr_24_qs)
);
@@ -9487,13 +9462,12 @@
.DW (13)
) u_mio_pad_attr_25 (
.re (mio_pad_attr_25_re),
- // qualified with register enable
.we (mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs),
.wd (mio_pad_attr_25_wd),
.d (hw2reg.mio_pad_attr[25].d),
.qre (),
.qe (reg2hw.mio_pad_attr[25].qe),
- .q (reg2hw.mio_pad_attr[25].q ),
+ .q (reg2hw.mio_pad_attr[25].q),
.qs (mio_pad_attr_25_qs)
);
@@ -9504,13 +9478,12 @@
.DW (13)
) u_mio_pad_attr_26 (
.re (mio_pad_attr_26_re),
- // qualified with register enable
.we (mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs),
.wd (mio_pad_attr_26_wd),
.d (hw2reg.mio_pad_attr[26].d),
.qre (),
.qe (reg2hw.mio_pad_attr[26].qe),
- .q (reg2hw.mio_pad_attr[26].q ),
+ .q (reg2hw.mio_pad_attr[26].q),
.qs (mio_pad_attr_26_qs)
);
@@ -9521,13 +9494,12 @@
.DW (13)
) u_mio_pad_attr_27 (
.re (mio_pad_attr_27_re),
- // qualified with register enable
.we (mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs),
.wd (mio_pad_attr_27_wd),
.d (hw2reg.mio_pad_attr[27].d),
.qre (),
.qe (reg2hw.mio_pad_attr[27].qe),
- .q (reg2hw.mio_pad_attr[27].q ),
+ .q (reg2hw.mio_pad_attr[27].q),
.qs (mio_pad_attr_27_qs)
);
@@ -9538,13 +9510,12 @@
.DW (13)
) u_mio_pad_attr_28 (
.re (mio_pad_attr_28_re),
- // qualified with register enable
.we (mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs),
.wd (mio_pad_attr_28_wd),
.d (hw2reg.mio_pad_attr[28].d),
.qre (),
.qe (reg2hw.mio_pad_attr[28].qe),
- .q (reg2hw.mio_pad_attr[28].q ),
+ .q (reg2hw.mio_pad_attr[28].q),
.qs (mio_pad_attr_28_qs)
);
@@ -9555,13 +9526,12 @@
.DW (13)
) u_mio_pad_attr_29 (
.re (mio_pad_attr_29_re),
- // qualified with register enable
.we (mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs),
.wd (mio_pad_attr_29_wd),
.d (hw2reg.mio_pad_attr[29].d),
.qre (),
.qe (reg2hw.mio_pad_attr[29].qe),
- .q (reg2hw.mio_pad_attr[29].q ),
+ .q (reg2hw.mio_pad_attr[29].q),
.qs (mio_pad_attr_29_qs)
);
@@ -9572,13 +9542,12 @@
.DW (13)
) u_mio_pad_attr_30 (
.re (mio_pad_attr_30_re),
- // qualified with register enable
.we (mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs),
.wd (mio_pad_attr_30_wd),
.d (hw2reg.mio_pad_attr[30].d),
.qre (),
.qe (reg2hw.mio_pad_attr[30].qe),
- .q (reg2hw.mio_pad_attr[30].q ),
+ .q (reg2hw.mio_pad_attr[30].q),
.qs (mio_pad_attr_30_qs)
);
@@ -9589,13 +9558,12 @@
.DW (13)
) u_mio_pad_attr_31 (
.re (mio_pad_attr_31_re),
- // qualified with register enable
.we (mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs),
.wd (mio_pad_attr_31_wd),
.d (hw2reg.mio_pad_attr[31].d),
.qre (),
.qe (reg2hw.mio_pad_attr[31].qe),
- .q (reg2hw.mio_pad_attr[31].q ),
+ .q (reg2hw.mio_pad_attr[31].q),
.qs (mio_pad_attr_31_qs)
);
@@ -9606,13 +9574,12 @@
.DW (13)
) u_mio_pad_attr_32 (
.re (mio_pad_attr_32_re),
- // qualified with register enable
.we (mio_pad_attr_32_we & mio_pad_attr_regwen_32_qs),
.wd (mio_pad_attr_32_wd),
.d (hw2reg.mio_pad_attr[32].d),
.qre (),
.qe (reg2hw.mio_pad_attr[32].qe),
- .q (reg2hw.mio_pad_attr[32].q ),
+ .q (reg2hw.mio_pad_attr[32].q),
.qs (mio_pad_attr_32_qs)
);
@@ -9623,13 +9590,12 @@
.DW (13)
) u_mio_pad_attr_33 (
.re (mio_pad_attr_33_re),
- // qualified with register enable
.we (mio_pad_attr_33_we & mio_pad_attr_regwen_33_qs),
.wd (mio_pad_attr_33_wd),
.d (hw2reg.mio_pad_attr[33].d),
.qre (),
.qe (reg2hw.mio_pad_attr[33].qe),
- .q (reg2hw.mio_pad_attr[33].q ),
+ .q (reg2hw.mio_pad_attr[33].q),
.qs (mio_pad_attr_33_qs)
);
@@ -9640,13 +9606,12 @@
.DW (13)
) u_mio_pad_attr_34 (
.re (mio_pad_attr_34_re),
- // qualified with register enable
.we (mio_pad_attr_34_we & mio_pad_attr_regwen_34_qs),
.wd (mio_pad_attr_34_wd),
.d (hw2reg.mio_pad_attr[34].d),
.qre (),
.qe (reg2hw.mio_pad_attr[34].qe),
- .q (reg2hw.mio_pad_attr[34].q ),
+ .q (reg2hw.mio_pad_attr[34].q),
.qs (mio_pad_attr_34_qs)
);
@@ -9657,13 +9622,12 @@
.DW (13)
) u_mio_pad_attr_35 (
.re (mio_pad_attr_35_re),
- // qualified with register enable
.we (mio_pad_attr_35_we & mio_pad_attr_regwen_35_qs),
.wd (mio_pad_attr_35_wd),
.d (hw2reg.mio_pad_attr[35].d),
.qre (),
.qe (reg2hw.mio_pad_attr[35].qe),
- .q (reg2hw.mio_pad_attr[35].q ),
+ .q (reg2hw.mio_pad_attr[35].q),
.qs (mio_pad_attr_35_qs)
);
@@ -9674,13 +9638,12 @@
.DW (13)
) u_mio_pad_attr_36 (
.re (mio_pad_attr_36_re),
- // qualified with register enable
.we (mio_pad_attr_36_we & mio_pad_attr_regwen_36_qs),
.wd (mio_pad_attr_36_wd),
.d (hw2reg.mio_pad_attr[36].d),
.qre (),
.qe (reg2hw.mio_pad_attr[36].qe),
- .q (reg2hw.mio_pad_attr[36].q ),
+ .q (reg2hw.mio_pad_attr[36].q),
.qs (mio_pad_attr_36_qs)
);
@@ -9691,13 +9654,12 @@
.DW (13)
) u_mio_pad_attr_37 (
.re (mio_pad_attr_37_re),
- // qualified with register enable
.we (mio_pad_attr_37_we & mio_pad_attr_regwen_37_qs),
.wd (mio_pad_attr_37_wd),
.d (hw2reg.mio_pad_attr[37].d),
.qre (),
.qe (reg2hw.mio_pad_attr[37].qe),
- .q (reg2hw.mio_pad_attr[37].q ),
+ .q (reg2hw.mio_pad_attr[37].q),
.qs (mio_pad_attr_37_qs)
);
@@ -9708,13 +9670,12 @@
.DW (13)
) u_mio_pad_attr_38 (
.re (mio_pad_attr_38_re),
- // qualified with register enable
.we (mio_pad_attr_38_we & mio_pad_attr_regwen_38_qs),
.wd (mio_pad_attr_38_wd),
.d (hw2reg.mio_pad_attr[38].d),
.qre (),
.qe (reg2hw.mio_pad_attr[38].qe),
- .q (reg2hw.mio_pad_attr[38].q ),
+ .q (reg2hw.mio_pad_attr[38].q),
.qs (mio_pad_attr_38_qs)
);
@@ -9725,13 +9686,12 @@
.DW (13)
) u_mio_pad_attr_39 (
.re (mio_pad_attr_39_re),
- // qualified with register enable
.we (mio_pad_attr_39_we & mio_pad_attr_regwen_39_qs),
.wd (mio_pad_attr_39_wd),
.d (hw2reg.mio_pad_attr[39].d),
.qre (),
.qe (reg2hw.mio_pad_attr[39].qe),
- .q (reg2hw.mio_pad_attr[39].q ),
+ .q (reg2hw.mio_pad_attr[39].q),
.qs (mio_pad_attr_39_qs)
);
@@ -9742,13 +9702,12 @@
.DW (13)
) u_mio_pad_attr_40 (
.re (mio_pad_attr_40_re),
- // qualified with register enable
.we (mio_pad_attr_40_we & mio_pad_attr_regwen_40_qs),
.wd (mio_pad_attr_40_wd),
.d (hw2reg.mio_pad_attr[40].d),
.qre (),
.qe (reg2hw.mio_pad_attr[40].qe),
- .q (reg2hw.mio_pad_attr[40].q ),
+ .q (reg2hw.mio_pad_attr[40].q),
.qs (mio_pad_attr_40_qs)
);
@@ -9759,13 +9718,12 @@
.DW (13)
) u_mio_pad_attr_41 (
.re (mio_pad_attr_41_re),
- // qualified with register enable
.we (mio_pad_attr_41_we & mio_pad_attr_regwen_41_qs),
.wd (mio_pad_attr_41_wd),
.d (hw2reg.mio_pad_attr[41].d),
.qre (),
.qe (reg2hw.mio_pad_attr[41].qe),
- .q (reg2hw.mio_pad_attr[41].q ),
+ .q (reg2hw.mio_pad_attr[41].q),
.qs (mio_pad_attr_41_qs)
);
@@ -9776,13 +9734,12 @@
.DW (13)
) u_mio_pad_attr_42 (
.re (mio_pad_attr_42_re),
- // qualified with register enable
.we (mio_pad_attr_42_we & mio_pad_attr_regwen_42_qs),
.wd (mio_pad_attr_42_wd),
.d (hw2reg.mio_pad_attr[42].d),
.qre (),
.qe (reg2hw.mio_pad_attr[42].qe),
- .q (reg2hw.mio_pad_attr[42].q ),
+ .q (reg2hw.mio_pad_attr[42].q),
.qs (mio_pad_attr_42_qs)
);
@@ -9793,13 +9750,12 @@
.DW (13)
) u_mio_pad_attr_43 (
.re (mio_pad_attr_43_re),
- // qualified with register enable
.we (mio_pad_attr_43_we & mio_pad_attr_regwen_43_qs),
.wd (mio_pad_attr_43_wd),
.d (hw2reg.mio_pad_attr[43].d),
.qre (),
.qe (reg2hw.mio_pad_attr[43].qe),
- .q (reg2hw.mio_pad_attr[43].q ),
+ .q (reg2hw.mio_pad_attr[43].q),
.qs (mio_pad_attr_43_qs)
);
@@ -9810,13 +9766,12 @@
.DW (13)
) u_mio_pad_attr_44 (
.re (mio_pad_attr_44_re),
- // qualified with register enable
.we (mio_pad_attr_44_we & mio_pad_attr_regwen_44_qs),
.wd (mio_pad_attr_44_wd),
.d (hw2reg.mio_pad_attr[44].d),
.qre (),
.qe (reg2hw.mio_pad_attr[44].qe),
- .q (reg2hw.mio_pad_attr[44].q ),
+ .q (reg2hw.mio_pad_attr[44].q),
.qs (mio_pad_attr_44_qs)
);
@@ -9827,13 +9782,12 @@
.DW (13)
) u_mio_pad_attr_45 (
.re (mio_pad_attr_45_re),
- // qualified with register enable
.we (mio_pad_attr_45_we & mio_pad_attr_regwen_45_qs),
.wd (mio_pad_attr_45_wd),
.d (hw2reg.mio_pad_attr[45].d),
.qre (),
.qe (reg2hw.mio_pad_attr[45].qe),
- .q (reg2hw.mio_pad_attr[45].q ),
+ .q (reg2hw.mio_pad_attr[45].q),
.qs (mio_pad_attr_45_qs)
);
@@ -9844,13 +9798,12 @@
.DW (13)
) u_mio_pad_attr_46 (
.re (mio_pad_attr_46_re),
- // qualified with register enable
.we (mio_pad_attr_46_we & mio_pad_attr_regwen_46_qs),
.wd (mio_pad_attr_46_wd),
.d (hw2reg.mio_pad_attr[46].d),
.qre (),
.qe (reg2hw.mio_pad_attr[46].qe),
- .q (reg2hw.mio_pad_attr[46].q ),
+ .q (reg2hw.mio_pad_attr[46].q),
.qs (mio_pad_attr_46_qs)
);
@@ -9864,8 +9817,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_0_we),
@@ -9873,7 +9826,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9891,8 +9844,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_1_we),
@@ -9900,7 +9853,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9918,8 +9871,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_2_we),
@@ -9927,7 +9880,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9945,8 +9898,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_3_we),
@@ -9954,7 +9907,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9972,8 +9925,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_4_we),
@@ -9981,7 +9934,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -9999,8 +9952,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_5_we),
@@ -10008,7 +9961,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10026,8 +9979,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_6_we),
@@ -10035,7 +9988,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10053,8 +10006,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_7_we),
@@ -10062,7 +10015,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10080,8 +10033,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_8_we),
@@ -10089,7 +10042,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10107,8 +10060,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_9_we),
@@ -10116,7 +10069,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10134,8 +10087,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_10_we),
@@ -10143,7 +10096,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10161,8 +10114,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_11_we),
@@ -10170,7 +10123,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10188,8 +10141,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_12_we),
@@ -10197,7 +10150,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10215,8 +10168,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_13_we),
@@ -10224,7 +10177,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10242,8 +10195,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_14_we),
@@ -10251,7 +10204,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10269,8 +10222,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_15_we),
@@ -10278,7 +10231,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10296,8 +10249,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_16_we),
@@ -10305,7 +10258,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10323,8 +10276,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_17_we),
@@ -10332,7 +10285,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10350,8 +10303,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_18_we),
@@ -10359,7 +10312,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10377,8 +10330,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_19_we),
@@ -10386,7 +10339,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10404,8 +10357,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_20_we),
@@ -10413,7 +10366,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10431,8 +10384,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_21_we),
@@ -10440,7 +10393,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10458,8 +10411,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_22_we),
@@ -10467,7 +10420,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10485,8 +10438,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_attr_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_attr_regwen_23_we),
@@ -10494,7 +10447,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -10513,13 +10466,12 @@
.DW (13)
) u_dio_pad_attr_0 (
.re (dio_pad_attr_0_re),
- // qualified with register enable
.we (dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs),
.wd (dio_pad_attr_0_wd),
.d (hw2reg.dio_pad_attr[0].d),
.qre (),
.qe (reg2hw.dio_pad_attr[0].qe),
- .q (reg2hw.dio_pad_attr[0].q ),
+ .q (reg2hw.dio_pad_attr[0].q),
.qs (dio_pad_attr_0_qs)
);
@@ -10530,13 +10482,12 @@
.DW (13)
) u_dio_pad_attr_1 (
.re (dio_pad_attr_1_re),
- // qualified with register enable
.we (dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs),
.wd (dio_pad_attr_1_wd),
.d (hw2reg.dio_pad_attr[1].d),
.qre (),
.qe (reg2hw.dio_pad_attr[1].qe),
- .q (reg2hw.dio_pad_attr[1].q ),
+ .q (reg2hw.dio_pad_attr[1].q),
.qs (dio_pad_attr_1_qs)
);
@@ -10547,13 +10498,12 @@
.DW (13)
) u_dio_pad_attr_2 (
.re (dio_pad_attr_2_re),
- // qualified with register enable
.we (dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs),
.wd (dio_pad_attr_2_wd),
.d (hw2reg.dio_pad_attr[2].d),
.qre (),
.qe (reg2hw.dio_pad_attr[2].qe),
- .q (reg2hw.dio_pad_attr[2].q ),
+ .q (reg2hw.dio_pad_attr[2].q),
.qs (dio_pad_attr_2_qs)
);
@@ -10564,13 +10514,12 @@
.DW (13)
) u_dio_pad_attr_3 (
.re (dio_pad_attr_3_re),
- // qualified with register enable
.we (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs),
.wd (dio_pad_attr_3_wd),
.d (hw2reg.dio_pad_attr[3].d),
.qre (),
.qe (reg2hw.dio_pad_attr[3].qe),
- .q (reg2hw.dio_pad_attr[3].q ),
+ .q (reg2hw.dio_pad_attr[3].q),
.qs (dio_pad_attr_3_qs)
);
@@ -10581,13 +10530,12 @@
.DW (13)
) u_dio_pad_attr_4 (
.re (dio_pad_attr_4_re),
- // qualified with register enable
.we (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs),
.wd (dio_pad_attr_4_wd),
.d (hw2reg.dio_pad_attr[4].d),
.qre (),
.qe (reg2hw.dio_pad_attr[4].qe),
- .q (reg2hw.dio_pad_attr[4].q ),
+ .q (reg2hw.dio_pad_attr[4].q),
.qs (dio_pad_attr_4_qs)
);
@@ -10598,13 +10546,12 @@
.DW (13)
) u_dio_pad_attr_5 (
.re (dio_pad_attr_5_re),
- // qualified with register enable
.we (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs),
.wd (dio_pad_attr_5_wd),
.d (hw2reg.dio_pad_attr[5].d),
.qre (),
.qe (reg2hw.dio_pad_attr[5].qe),
- .q (reg2hw.dio_pad_attr[5].q ),
+ .q (reg2hw.dio_pad_attr[5].q),
.qs (dio_pad_attr_5_qs)
);
@@ -10615,13 +10562,12 @@
.DW (13)
) u_dio_pad_attr_6 (
.re (dio_pad_attr_6_re),
- // qualified with register enable
.we (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs),
.wd (dio_pad_attr_6_wd),
.d (hw2reg.dio_pad_attr[6].d),
.qre (),
.qe (reg2hw.dio_pad_attr[6].qe),
- .q (reg2hw.dio_pad_attr[6].q ),
+ .q (reg2hw.dio_pad_attr[6].q),
.qs (dio_pad_attr_6_qs)
);
@@ -10632,13 +10578,12 @@
.DW (13)
) u_dio_pad_attr_7 (
.re (dio_pad_attr_7_re),
- // qualified with register enable
.we (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs),
.wd (dio_pad_attr_7_wd),
.d (hw2reg.dio_pad_attr[7].d),
.qre (),
.qe (reg2hw.dio_pad_attr[7].qe),
- .q (reg2hw.dio_pad_attr[7].q ),
+ .q (reg2hw.dio_pad_attr[7].q),
.qs (dio_pad_attr_7_qs)
);
@@ -10649,13 +10594,12 @@
.DW (13)
) u_dio_pad_attr_8 (
.re (dio_pad_attr_8_re),
- // qualified with register enable
.we (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs),
.wd (dio_pad_attr_8_wd),
.d (hw2reg.dio_pad_attr[8].d),
.qre (),
.qe (reg2hw.dio_pad_attr[8].qe),
- .q (reg2hw.dio_pad_attr[8].q ),
+ .q (reg2hw.dio_pad_attr[8].q),
.qs (dio_pad_attr_8_qs)
);
@@ -10666,13 +10610,12 @@
.DW (13)
) u_dio_pad_attr_9 (
.re (dio_pad_attr_9_re),
- // qualified with register enable
.we (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs),
.wd (dio_pad_attr_9_wd),
.d (hw2reg.dio_pad_attr[9].d),
.qre (),
.qe (reg2hw.dio_pad_attr[9].qe),
- .q (reg2hw.dio_pad_attr[9].q ),
+ .q (reg2hw.dio_pad_attr[9].q),
.qs (dio_pad_attr_9_qs)
);
@@ -10683,13 +10626,12 @@
.DW (13)
) u_dio_pad_attr_10 (
.re (dio_pad_attr_10_re),
- // qualified with register enable
.we (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs),
.wd (dio_pad_attr_10_wd),
.d (hw2reg.dio_pad_attr[10].d),
.qre (),
.qe (reg2hw.dio_pad_attr[10].qe),
- .q (reg2hw.dio_pad_attr[10].q ),
+ .q (reg2hw.dio_pad_attr[10].q),
.qs (dio_pad_attr_10_qs)
);
@@ -10700,13 +10642,12 @@
.DW (13)
) u_dio_pad_attr_11 (
.re (dio_pad_attr_11_re),
- // qualified with register enable
.we (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs),
.wd (dio_pad_attr_11_wd),
.d (hw2reg.dio_pad_attr[11].d),
.qre (),
.qe (reg2hw.dio_pad_attr[11].qe),
- .q (reg2hw.dio_pad_attr[11].q ),
+ .q (reg2hw.dio_pad_attr[11].q),
.qs (dio_pad_attr_11_qs)
);
@@ -10717,13 +10658,12 @@
.DW (13)
) u_dio_pad_attr_12 (
.re (dio_pad_attr_12_re),
- // qualified with register enable
.we (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs),
.wd (dio_pad_attr_12_wd),
.d (hw2reg.dio_pad_attr[12].d),
.qre (),
.qe (reg2hw.dio_pad_attr[12].qe),
- .q (reg2hw.dio_pad_attr[12].q ),
+ .q (reg2hw.dio_pad_attr[12].q),
.qs (dio_pad_attr_12_qs)
);
@@ -10734,13 +10674,12 @@
.DW (13)
) u_dio_pad_attr_13 (
.re (dio_pad_attr_13_re),
- // qualified with register enable
.we (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs),
.wd (dio_pad_attr_13_wd),
.d (hw2reg.dio_pad_attr[13].d),
.qre (),
.qe (reg2hw.dio_pad_attr[13].qe),
- .q (reg2hw.dio_pad_attr[13].q ),
+ .q (reg2hw.dio_pad_attr[13].q),
.qs (dio_pad_attr_13_qs)
);
@@ -10751,13 +10690,12 @@
.DW (13)
) u_dio_pad_attr_14 (
.re (dio_pad_attr_14_re),
- // qualified with register enable
.we (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs),
.wd (dio_pad_attr_14_wd),
.d (hw2reg.dio_pad_attr[14].d),
.qre (),
.qe (reg2hw.dio_pad_attr[14].qe),
- .q (reg2hw.dio_pad_attr[14].q ),
+ .q (reg2hw.dio_pad_attr[14].q),
.qs (dio_pad_attr_14_qs)
);
@@ -10768,13 +10706,12 @@
.DW (13)
) u_dio_pad_attr_15 (
.re (dio_pad_attr_15_re),
- // qualified with register enable
.we (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs),
.wd (dio_pad_attr_15_wd),
.d (hw2reg.dio_pad_attr[15].d),
.qre (),
.qe (reg2hw.dio_pad_attr[15].qe),
- .q (reg2hw.dio_pad_attr[15].q ),
+ .q (reg2hw.dio_pad_attr[15].q),
.qs (dio_pad_attr_15_qs)
);
@@ -10785,13 +10722,12 @@
.DW (13)
) u_dio_pad_attr_16 (
.re (dio_pad_attr_16_re),
- // qualified with register enable
.we (dio_pad_attr_16_we & dio_pad_attr_regwen_16_qs),
.wd (dio_pad_attr_16_wd),
.d (hw2reg.dio_pad_attr[16].d),
.qre (),
.qe (reg2hw.dio_pad_attr[16].qe),
- .q (reg2hw.dio_pad_attr[16].q ),
+ .q (reg2hw.dio_pad_attr[16].q),
.qs (dio_pad_attr_16_qs)
);
@@ -10802,13 +10738,12 @@
.DW (13)
) u_dio_pad_attr_17 (
.re (dio_pad_attr_17_re),
- // qualified with register enable
.we (dio_pad_attr_17_we & dio_pad_attr_regwen_17_qs),
.wd (dio_pad_attr_17_wd),
.d (hw2reg.dio_pad_attr[17].d),
.qre (),
.qe (reg2hw.dio_pad_attr[17].qe),
- .q (reg2hw.dio_pad_attr[17].q ),
+ .q (reg2hw.dio_pad_attr[17].q),
.qs (dio_pad_attr_17_qs)
);
@@ -10819,13 +10754,12 @@
.DW (13)
) u_dio_pad_attr_18 (
.re (dio_pad_attr_18_re),
- // qualified with register enable
.we (dio_pad_attr_18_we & dio_pad_attr_regwen_18_qs),
.wd (dio_pad_attr_18_wd),
.d (hw2reg.dio_pad_attr[18].d),
.qre (),
.qe (reg2hw.dio_pad_attr[18].qe),
- .q (reg2hw.dio_pad_attr[18].q ),
+ .q (reg2hw.dio_pad_attr[18].q),
.qs (dio_pad_attr_18_qs)
);
@@ -10836,13 +10770,12 @@
.DW (13)
) u_dio_pad_attr_19 (
.re (dio_pad_attr_19_re),
- // qualified with register enable
.we (dio_pad_attr_19_we & dio_pad_attr_regwen_19_qs),
.wd (dio_pad_attr_19_wd),
.d (hw2reg.dio_pad_attr[19].d),
.qre (),
.qe (reg2hw.dio_pad_attr[19].qe),
- .q (reg2hw.dio_pad_attr[19].q ),
+ .q (reg2hw.dio_pad_attr[19].q),
.qs (dio_pad_attr_19_qs)
);
@@ -10853,13 +10786,12 @@
.DW (13)
) u_dio_pad_attr_20 (
.re (dio_pad_attr_20_re),
- // qualified with register enable
.we (dio_pad_attr_20_we & dio_pad_attr_regwen_20_qs),
.wd (dio_pad_attr_20_wd),
.d (hw2reg.dio_pad_attr[20].d),
.qre (),
.qe (reg2hw.dio_pad_attr[20].qe),
- .q (reg2hw.dio_pad_attr[20].q ),
+ .q (reg2hw.dio_pad_attr[20].q),
.qs (dio_pad_attr_20_qs)
);
@@ -10870,13 +10802,12 @@
.DW (13)
) u_dio_pad_attr_21 (
.re (dio_pad_attr_21_re),
- // qualified with register enable
.we (dio_pad_attr_21_we & dio_pad_attr_regwen_21_qs),
.wd (dio_pad_attr_21_wd),
.d (hw2reg.dio_pad_attr[21].d),
.qre (),
.qe (reg2hw.dio_pad_attr[21].qe),
- .q (reg2hw.dio_pad_attr[21].q ),
+ .q (reg2hw.dio_pad_attr[21].q),
.qs (dio_pad_attr_21_qs)
);
@@ -10887,13 +10818,12 @@
.DW (13)
) u_dio_pad_attr_22 (
.re (dio_pad_attr_22_re),
- // qualified with register enable
.we (dio_pad_attr_22_we & dio_pad_attr_regwen_22_qs),
.wd (dio_pad_attr_22_wd),
.d (hw2reg.dio_pad_attr[22].d),
.qre (),
.qe (reg2hw.dio_pad_attr[22].qe),
- .q (reg2hw.dio_pad_attr[22].q ),
+ .q (reg2hw.dio_pad_attr[22].q),
.qs (dio_pad_attr_22_qs)
);
@@ -10904,13 +10834,12 @@
.DW (13)
) u_dio_pad_attr_23 (
.re (dio_pad_attr_23_re),
- // qualified with register enable
.we (dio_pad_attr_23_we & dio_pad_attr_regwen_23_qs),
.wd (dio_pad_attr_23_wd),
.d (hw2reg.dio_pad_attr[23].d),
.qre (),
.qe (reg2hw.dio_pad_attr[23].qe),
- .q (reg2hw.dio_pad_attr[23].q ),
+ .q (reg2hw.dio_pad_attr[23].q),
.qs (dio_pad_attr_23_qs)
);
@@ -10925,8 +10854,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_0_we),
@@ -10934,11 +10863,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[0].de),
- .d (hw2reg.mio_pad_sleep_status[0].d ),
+ .d (hw2reg.mio_pad_sleep_status[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[0].q ),
+ .q (reg2hw.mio_pad_sleep_status[0].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_0_qs)
@@ -10951,8 +10880,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_1_we),
@@ -10960,11 +10889,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[1].de),
- .d (hw2reg.mio_pad_sleep_status[1].d ),
+ .d (hw2reg.mio_pad_sleep_status[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[1].q ),
+ .q (reg2hw.mio_pad_sleep_status[1].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_1_qs)
@@ -10977,8 +10906,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_2_we),
@@ -10986,11 +10915,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[2].de),
- .d (hw2reg.mio_pad_sleep_status[2].d ),
+ .d (hw2reg.mio_pad_sleep_status[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[2].q ),
+ .q (reg2hw.mio_pad_sleep_status[2].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_2_qs)
@@ -11003,8 +10932,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_3_we),
@@ -11012,11 +10941,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[3].de),
- .d (hw2reg.mio_pad_sleep_status[3].d ),
+ .d (hw2reg.mio_pad_sleep_status[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[3].q ),
+ .q (reg2hw.mio_pad_sleep_status[3].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_3_qs)
@@ -11029,8 +10958,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_4_we),
@@ -11038,11 +10967,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[4].de),
- .d (hw2reg.mio_pad_sleep_status[4].d ),
+ .d (hw2reg.mio_pad_sleep_status[4].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[4].q ),
+ .q (reg2hw.mio_pad_sleep_status[4].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_4_qs)
@@ -11055,8 +10984,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_5_we),
@@ -11064,11 +10993,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[5].de),
- .d (hw2reg.mio_pad_sleep_status[5].d ),
+ .d (hw2reg.mio_pad_sleep_status[5].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[5].q ),
+ .q (reg2hw.mio_pad_sleep_status[5].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_5_qs)
@@ -11081,8 +11010,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_6_we),
@@ -11090,11 +11019,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[6].de),
- .d (hw2reg.mio_pad_sleep_status[6].d ),
+ .d (hw2reg.mio_pad_sleep_status[6].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[6].q ),
+ .q (reg2hw.mio_pad_sleep_status[6].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_6_qs)
@@ -11107,8 +11036,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_7_we),
@@ -11116,11 +11045,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[7].de),
- .d (hw2reg.mio_pad_sleep_status[7].d ),
+ .d (hw2reg.mio_pad_sleep_status[7].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[7].q ),
+ .q (reg2hw.mio_pad_sleep_status[7].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_7_qs)
@@ -11133,8 +11062,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_8_we),
@@ -11142,11 +11071,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[8].de),
- .d (hw2reg.mio_pad_sleep_status[8].d ),
+ .d (hw2reg.mio_pad_sleep_status[8].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[8].q ),
+ .q (reg2hw.mio_pad_sleep_status[8].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_8_qs)
@@ -11159,8 +11088,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_9_we),
@@ -11168,11 +11097,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[9].de),
- .d (hw2reg.mio_pad_sleep_status[9].d ),
+ .d (hw2reg.mio_pad_sleep_status[9].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[9].q ),
+ .q (reg2hw.mio_pad_sleep_status[9].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_9_qs)
@@ -11185,8 +11114,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_10_we),
@@ -11194,11 +11123,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[10].de),
- .d (hw2reg.mio_pad_sleep_status[10].d ),
+ .d (hw2reg.mio_pad_sleep_status[10].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[10].q ),
+ .q (reg2hw.mio_pad_sleep_status[10].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_10_qs)
@@ -11211,8 +11140,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_11_we),
@@ -11220,11 +11149,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[11].de),
- .d (hw2reg.mio_pad_sleep_status[11].d ),
+ .d (hw2reg.mio_pad_sleep_status[11].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[11].q ),
+ .q (reg2hw.mio_pad_sleep_status[11].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_11_qs)
@@ -11237,8 +11166,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_12_we),
@@ -11246,11 +11175,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[12].de),
- .d (hw2reg.mio_pad_sleep_status[12].d ),
+ .d (hw2reg.mio_pad_sleep_status[12].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[12].q ),
+ .q (reg2hw.mio_pad_sleep_status[12].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_12_qs)
@@ -11263,8 +11192,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_13_we),
@@ -11272,11 +11201,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[13].de),
- .d (hw2reg.mio_pad_sleep_status[13].d ),
+ .d (hw2reg.mio_pad_sleep_status[13].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[13].q ),
+ .q (reg2hw.mio_pad_sleep_status[13].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_13_qs)
@@ -11289,8 +11218,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_14_we),
@@ -11298,11 +11227,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[14].de),
- .d (hw2reg.mio_pad_sleep_status[14].d ),
+ .d (hw2reg.mio_pad_sleep_status[14].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[14].q ),
+ .q (reg2hw.mio_pad_sleep_status[14].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_14_qs)
@@ -11315,8 +11244,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_15_we),
@@ -11324,11 +11253,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[15].de),
- .d (hw2reg.mio_pad_sleep_status[15].d ),
+ .d (hw2reg.mio_pad_sleep_status[15].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[15].q ),
+ .q (reg2hw.mio_pad_sleep_status[15].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_15_qs)
@@ -11341,8 +11270,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_16_we),
@@ -11350,11 +11279,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[16].de),
- .d (hw2reg.mio_pad_sleep_status[16].d ),
+ .d (hw2reg.mio_pad_sleep_status[16].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[16].q ),
+ .q (reg2hw.mio_pad_sleep_status[16].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_16_qs)
@@ -11367,8 +11296,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_17_we),
@@ -11376,11 +11305,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[17].de),
- .d (hw2reg.mio_pad_sleep_status[17].d ),
+ .d (hw2reg.mio_pad_sleep_status[17].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[17].q ),
+ .q (reg2hw.mio_pad_sleep_status[17].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_17_qs)
@@ -11393,8 +11322,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_18_we),
@@ -11402,11 +11331,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[18].de),
- .d (hw2reg.mio_pad_sleep_status[18].d ),
+ .d (hw2reg.mio_pad_sleep_status[18].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[18].q ),
+ .q (reg2hw.mio_pad_sleep_status[18].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_18_qs)
@@ -11419,8 +11348,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_19_we),
@@ -11428,11 +11357,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[19].de),
- .d (hw2reg.mio_pad_sleep_status[19].d ),
+ .d (hw2reg.mio_pad_sleep_status[19].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[19].q ),
+ .q (reg2hw.mio_pad_sleep_status[19].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_19_qs)
@@ -11445,8 +11374,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_20_we),
@@ -11454,11 +11383,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[20].de),
- .d (hw2reg.mio_pad_sleep_status[20].d ),
+ .d (hw2reg.mio_pad_sleep_status[20].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[20].q ),
+ .q (reg2hw.mio_pad_sleep_status[20].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_20_qs)
@@ -11471,8 +11400,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_21_we),
@@ -11480,11 +11409,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[21].de),
- .d (hw2reg.mio_pad_sleep_status[21].d ),
+ .d (hw2reg.mio_pad_sleep_status[21].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[21].q ),
+ .q (reg2hw.mio_pad_sleep_status[21].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_21_qs)
@@ -11497,8 +11426,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_22_we),
@@ -11506,11 +11435,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[22].de),
- .d (hw2reg.mio_pad_sleep_status[22].d ),
+ .d (hw2reg.mio_pad_sleep_status[22].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[22].q ),
+ .q (reg2hw.mio_pad_sleep_status[22].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_22_qs)
@@ -11523,8 +11452,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_23_we),
@@ -11532,11 +11461,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[23].de),
- .d (hw2reg.mio_pad_sleep_status[23].d ),
+ .d (hw2reg.mio_pad_sleep_status[23].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[23].q ),
+ .q (reg2hw.mio_pad_sleep_status[23].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_23_qs)
@@ -11549,8 +11478,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_24_we),
@@ -11558,11 +11487,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[24].de),
- .d (hw2reg.mio_pad_sleep_status[24].d ),
+ .d (hw2reg.mio_pad_sleep_status[24].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[24].q ),
+ .q (reg2hw.mio_pad_sleep_status[24].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_24_qs)
@@ -11575,8 +11504,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_25_we),
@@ -11584,11 +11513,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[25].de),
- .d (hw2reg.mio_pad_sleep_status[25].d ),
+ .d (hw2reg.mio_pad_sleep_status[25].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[25].q ),
+ .q (reg2hw.mio_pad_sleep_status[25].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_25_qs)
@@ -11601,8 +11530,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_26_we),
@@ -11610,11 +11539,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[26].de),
- .d (hw2reg.mio_pad_sleep_status[26].d ),
+ .d (hw2reg.mio_pad_sleep_status[26].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[26].q ),
+ .q (reg2hw.mio_pad_sleep_status[26].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_26_qs)
@@ -11627,8 +11556,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_27_we),
@@ -11636,11 +11565,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[27].de),
- .d (hw2reg.mio_pad_sleep_status[27].d ),
+ .d (hw2reg.mio_pad_sleep_status[27].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[27].q ),
+ .q (reg2hw.mio_pad_sleep_status[27].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_27_qs)
@@ -11653,8 +11582,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_28_we),
@@ -11662,11 +11591,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[28].de),
- .d (hw2reg.mio_pad_sleep_status[28].d ),
+ .d (hw2reg.mio_pad_sleep_status[28].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[28].q ),
+ .q (reg2hw.mio_pad_sleep_status[28].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_28_qs)
@@ -11679,8 +11608,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_29_we),
@@ -11688,11 +11617,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[29].de),
- .d (hw2reg.mio_pad_sleep_status[29].d ),
+ .d (hw2reg.mio_pad_sleep_status[29].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[29].q ),
+ .q (reg2hw.mio_pad_sleep_status[29].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_29_qs)
@@ -11705,8 +11634,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_30_we),
@@ -11714,11 +11643,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[30].de),
- .d (hw2reg.mio_pad_sleep_status[30].d ),
+ .d (hw2reg.mio_pad_sleep_status[30].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[30].q ),
+ .q (reg2hw.mio_pad_sleep_status[30].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_30_qs)
@@ -11731,8 +11660,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_0_en_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_0_en_31_we),
@@ -11740,11 +11669,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[31].de),
- .d (hw2reg.mio_pad_sleep_status[31].d ),
+ .d (hw2reg.mio_pad_sleep_status[31].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[31].q ),
+ .q (reg2hw.mio_pad_sleep_status[31].q),
// to register interface (read)
.qs (mio_pad_sleep_status_0_en_31_qs)
@@ -11760,8 +11689,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_32_we),
@@ -11769,11 +11698,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[32].de),
- .d (hw2reg.mio_pad_sleep_status[32].d ),
+ .d (hw2reg.mio_pad_sleep_status[32].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[32].q ),
+ .q (reg2hw.mio_pad_sleep_status[32].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_32_qs)
@@ -11786,8 +11715,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_33_we),
@@ -11795,11 +11724,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[33].de),
- .d (hw2reg.mio_pad_sleep_status[33].d ),
+ .d (hw2reg.mio_pad_sleep_status[33].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[33].q ),
+ .q (reg2hw.mio_pad_sleep_status[33].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_33_qs)
@@ -11812,8 +11741,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_34_we),
@@ -11821,11 +11750,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[34].de),
- .d (hw2reg.mio_pad_sleep_status[34].d ),
+ .d (hw2reg.mio_pad_sleep_status[34].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[34].q ),
+ .q (reg2hw.mio_pad_sleep_status[34].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_34_qs)
@@ -11838,8 +11767,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_35_we),
@@ -11847,11 +11776,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[35].de),
- .d (hw2reg.mio_pad_sleep_status[35].d ),
+ .d (hw2reg.mio_pad_sleep_status[35].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[35].q ),
+ .q (reg2hw.mio_pad_sleep_status[35].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_35_qs)
@@ -11864,8 +11793,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_36_we),
@@ -11873,11 +11802,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[36].de),
- .d (hw2reg.mio_pad_sleep_status[36].d ),
+ .d (hw2reg.mio_pad_sleep_status[36].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[36].q ),
+ .q (reg2hw.mio_pad_sleep_status[36].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_36_qs)
@@ -11890,8 +11819,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_37_we),
@@ -11899,11 +11828,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[37].de),
- .d (hw2reg.mio_pad_sleep_status[37].d ),
+ .d (hw2reg.mio_pad_sleep_status[37].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[37].q ),
+ .q (reg2hw.mio_pad_sleep_status[37].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_37_qs)
@@ -11916,8 +11845,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_38_we),
@@ -11925,11 +11854,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[38].de),
- .d (hw2reg.mio_pad_sleep_status[38].d ),
+ .d (hw2reg.mio_pad_sleep_status[38].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[38].q ),
+ .q (reg2hw.mio_pad_sleep_status[38].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_38_qs)
@@ -11942,8 +11871,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_39_we),
@@ -11951,11 +11880,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[39].de),
- .d (hw2reg.mio_pad_sleep_status[39].d ),
+ .d (hw2reg.mio_pad_sleep_status[39].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[39].q ),
+ .q (reg2hw.mio_pad_sleep_status[39].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_39_qs)
@@ -11968,8 +11897,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_40_we),
@@ -11977,11 +11906,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[40].de),
- .d (hw2reg.mio_pad_sleep_status[40].d ),
+ .d (hw2reg.mio_pad_sleep_status[40].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[40].q ),
+ .q (reg2hw.mio_pad_sleep_status[40].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_40_qs)
@@ -11994,8 +11923,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_41_we),
@@ -12003,11 +11932,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[41].de),
- .d (hw2reg.mio_pad_sleep_status[41].d ),
+ .d (hw2reg.mio_pad_sleep_status[41].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[41].q ),
+ .q (reg2hw.mio_pad_sleep_status[41].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_41_qs)
@@ -12020,8 +11949,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_42_we),
@@ -12029,11 +11958,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[42].de),
- .d (hw2reg.mio_pad_sleep_status[42].d ),
+ .d (hw2reg.mio_pad_sleep_status[42].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[42].q ),
+ .q (reg2hw.mio_pad_sleep_status[42].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_42_qs)
@@ -12046,8 +11975,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_43_we),
@@ -12055,11 +11984,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[43].de),
- .d (hw2reg.mio_pad_sleep_status[43].d ),
+ .d (hw2reg.mio_pad_sleep_status[43].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[43].q ),
+ .q (reg2hw.mio_pad_sleep_status[43].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_43_qs)
@@ -12072,8 +12001,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_44_we),
@@ -12081,11 +12010,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[44].de),
- .d (hw2reg.mio_pad_sleep_status[44].d ),
+ .d (hw2reg.mio_pad_sleep_status[44].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[44].q ),
+ .q (reg2hw.mio_pad_sleep_status[44].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_44_qs)
@@ -12098,8 +12027,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_45_we),
@@ -12107,11 +12036,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[45].de),
- .d (hw2reg.mio_pad_sleep_status[45].d ),
+ .d (hw2reg.mio_pad_sleep_status[45].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[45].q ),
+ .q (reg2hw.mio_pad_sleep_status[45].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_45_qs)
@@ -12124,8 +12053,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_mio_pad_sleep_status_1_en_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_status_1_en_46_we),
@@ -12133,11 +12062,11 @@
// from internal hardware
.de (hw2reg.mio_pad_sleep_status[46].de),
- .d (hw2reg.mio_pad_sleep_status[46].d ),
+ .d (hw2reg.mio_pad_sleep_status[46].d),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_status[46].q ),
+ .q (reg2hw.mio_pad_sleep_status[46].q),
// to register interface (read)
.qs (mio_pad_sleep_status_1_en_46_qs)
@@ -12154,8 +12083,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_0_we),
@@ -12163,7 +12092,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12181,8 +12110,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_1_we),
@@ -12190,7 +12119,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12208,8 +12137,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_2_we),
@@ -12217,7 +12146,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12235,8 +12164,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_3_we),
@@ -12244,7 +12173,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12262,8 +12191,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_4_we),
@@ -12271,7 +12200,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12289,8 +12218,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_5_we),
@@ -12298,7 +12227,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12316,8 +12245,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_6_we),
@@ -12325,7 +12254,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12343,8 +12272,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_7_we),
@@ -12352,7 +12281,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12370,8 +12299,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_8_we),
@@ -12379,7 +12308,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12397,8 +12326,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_9_we),
@@ -12406,7 +12335,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12424,8 +12353,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_10_we),
@@ -12433,7 +12362,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12451,8 +12380,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_11_we),
@@ -12460,7 +12389,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12478,8 +12407,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_12_we),
@@ -12487,7 +12416,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12505,8 +12434,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_13_we),
@@ -12514,7 +12443,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12532,8 +12461,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_14_we),
@@ -12541,7 +12470,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12559,8 +12488,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_15_we),
@@ -12568,7 +12497,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12586,8 +12515,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_16_we),
@@ -12595,7 +12524,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12613,8 +12542,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_17_we),
@@ -12622,7 +12551,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12640,8 +12569,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_18_we),
@@ -12649,7 +12578,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12667,8 +12596,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_19_we),
@@ -12676,7 +12605,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12694,8 +12623,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_20_we),
@@ -12703,7 +12632,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12721,8 +12650,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_21_we),
@@ -12730,7 +12659,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12748,8 +12677,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_22_we),
@@ -12757,7 +12686,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12775,8 +12704,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_23_we),
@@ -12784,7 +12713,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12802,8 +12731,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_24_we),
@@ -12811,7 +12740,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12829,8 +12758,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_25_we),
@@ -12838,7 +12767,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12856,8 +12785,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_26_we),
@@ -12865,7 +12794,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12883,8 +12812,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_27_we),
@@ -12892,7 +12821,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12910,8 +12839,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_28_we),
@@ -12919,7 +12848,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12937,8 +12866,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_29_we),
@@ -12946,7 +12875,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12964,8 +12893,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_30_we),
@@ -12973,7 +12902,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -12991,8 +12920,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_31_we),
@@ -13000,7 +12929,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13018,8 +12947,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_32_we),
@@ -13027,7 +12956,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13045,8 +12974,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_33_we),
@@ -13054,7 +12983,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13072,8 +13001,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_34_we),
@@ -13081,7 +13010,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13099,8 +13028,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_35_we),
@@ -13108,7 +13037,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13126,8 +13055,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_36_we),
@@ -13135,7 +13064,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13153,8 +13082,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_37_we),
@@ -13162,7 +13091,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13180,8 +13109,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_38_we),
@@ -13189,7 +13118,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13207,8 +13136,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_39_we),
@@ -13216,7 +13145,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13234,8 +13163,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_40_we),
@@ -13243,7 +13172,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13261,8 +13190,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_41_we),
@@ -13270,7 +13199,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13288,8 +13217,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_42_we),
@@ -13297,7 +13226,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13315,8 +13244,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_43_we),
@@ -13324,7 +13253,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13342,8 +13271,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_44_we),
@@ -13351,7 +13280,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13369,8 +13298,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_45_we),
@@ -13378,7 +13307,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13396,8 +13325,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_mio_pad_sleep_regwen_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (mio_pad_sleep_regwen_46_we),
@@ -13405,7 +13334,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -13425,20 +13354,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs),
.wd (mio_pad_sleep_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[0].q ),
+ .q (reg2hw.mio_pad_sleep_en[0].q),
// to register interface (read)
.qs (mio_pad_sleep_en_0_qs)
@@ -13452,20 +13381,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs),
.wd (mio_pad_sleep_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[1].q ),
+ .q (reg2hw.mio_pad_sleep_en[1].q),
// to register interface (read)
.qs (mio_pad_sleep_en_1_qs)
@@ -13479,20 +13408,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs),
.wd (mio_pad_sleep_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[2].q ),
+ .q (reg2hw.mio_pad_sleep_en[2].q),
// to register interface (read)
.qs (mio_pad_sleep_en_2_qs)
@@ -13506,20 +13435,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs),
.wd (mio_pad_sleep_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[3].q ),
+ .q (reg2hw.mio_pad_sleep_en[3].q),
// to register interface (read)
.qs (mio_pad_sleep_en_3_qs)
@@ -13533,20 +13462,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs),
.wd (mio_pad_sleep_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[4].q ),
+ .q (reg2hw.mio_pad_sleep_en[4].q),
// to register interface (read)
.qs (mio_pad_sleep_en_4_qs)
@@ -13560,20 +13489,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs),
.wd (mio_pad_sleep_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[5].q ),
+ .q (reg2hw.mio_pad_sleep_en[5].q),
// to register interface (read)
.qs (mio_pad_sleep_en_5_qs)
@@ -13587,20 +13516,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs),
.wd (mio_pad_sleep_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[6].q ),
+ .q (reg2hw.mio_pad_sleep_en[6].q),
// to register interface (read)
.qs (mio_pad_sleep_en_6_qs)
@@ -13614,20 +13543,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs),
.wd (mio_pad_sleep_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[7].q ),
+ .q (reg2hw.mio_pad_sleep_en[7].q),
// to register interface (read)
.qs (mio_pad_sleep_en_7_qs)
@@ -13641,20 +13570,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs),
.wd (mio_pad_sleep_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[8].q ),
+ .q (reg2hw.mio_pad_sleep_en[8].q),
// to register interface (read)
.qs (mio_pad_sleep_en_8_qs)
@@ -13668,20 +13597,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs),
.wd (mio_pad_sleep_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[9].q ),
+ .q (reg2hw.mio_pad_sleep_en[9].q),
// to register interface (read)
.qs (mio_pad_sleep_en_9_qs)
@@ -13695,20 +13624,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs),
.wd (mio_pad_sleep_en_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[10].q ),
+ .q (reg2hw.mio_pad_sleep_en[10].q),
// to register interface (read)
.qs (mio_pad_sleep_en_10_qs)
@@ -13722,20 +13651,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs),
.wd (mio_pad_sleep_en_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[11].q ),
+ .q (reg2hw.mio_pad_sleep_en[11].q),
// to register interface (read)
.qs (mio_pad_sleep_en_11_qs)
@@ -13749,20 +13678,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs),
.wd (mio_pad_sleep_en_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[12].q ),
+ .q (reg2hw.mio_pad_sleep_en[12].q),
// to register interface (read)
.qs (mio_pad_sleep_en_12_qs)
@@ -13776,20 +13705,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs),
.wd (mio_pad_sleep_en_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[13].q ),
+ .q (reg2hw.mio_pad_sleep_en[13].q),
// to register interface (read)
.qs (mio_pad_sleep_en_13_qs)
@@ -13803,20 +13732,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs),
.wd (mio_pad_sleep_en_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[14].q ),
+ .q (reg2hw.mio_pad_sleep_en[14].q),
// to register interface (read)
.qs (mio_pad_sleep_en_14_qs)
@@ -13830,20 +13759,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs),
.wd (mio_pad_sleep_en_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[15].q ),
+ .q (reg2hw.mio_pad_sleep_en[15].q),
// to register interface (read)
.qs (mio_pad_sleep_en_15_qs)
@@ -13857,20 +13786,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs),
.wd (mio_pad_sleep_en_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[16].q ),
+ .q (reg2hw.mio_pad_sleep_en[16].q),
// to register interface (read)
.qs (mio_pad_sleep_en_16_qs)
@@ -13884,20 +13813,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs),
.wd (mio_pad_sleep_en_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[17].q ),
+ .q (reg2hw.mio_pad_sleep_en[17].q),
// to register interface (read)
.qs (mio_pad_sleep_en_17_qs)
@@ -13911,20 +13840,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs),
.wd (mio_pad_sleep_en_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[18].q ),
+ .q (reg2hw.mio_pad_sleep_en[18].q),
// to register interface (read)
.qs (mio_pad_sleep_en_18_qs)
@@ -13938,20 +13867,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs),
.wd (mio_pad_sleep_en_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[19].q ),
+ .q (reg2hw.mio_pad_sleep_en[19].q),
// to register interface (read)
.qs (mio_pad_sleep_en_19_qs)
@@ -13965,20 +13894,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs),
.wd (mio_pad_sleep_en_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[20].q ),
+ .q (reg2hw.mio_pad_sleep_en[20].q),
// to register interface (read)
.qs (mio_pad_sleep_en_20_qs)
@@ -13992,20 +13921,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs),
.wd (mio_pad_sleep_en_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[21].q ),
+ .q (reg2hw.mio_pad_sleep_en[21].q),
// to register interface (read)
.qs (mio_pad_sleep_en_21_qs)
@@ -14019,20 +13948,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs),
.wd (mio_pad_sleep_en_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[22].q ),
+ .q (reg2hw.mio_pad_sleep_en[22].q),
// to register interface (read)
.qs (mio_pad_sleep_en_22_qs)
@@ -14046,20 +13975,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs),
.wd (mio_pad_sleep_en_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[23].q ),
+ .q (reg2hw.mio_pad_sleep_en[23].q),
// to register interface (read)
.qs (mio_pad_sleep_en_23_qs)
@@ -14073,20 +14002,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs),
.wd (mio_pad_sleep_en_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[24].q ),
+ .q (reg2hw.mio_pad_sleep_en[24].q),
// to register interface (read)
.qs (mio_pad_sleep_en_24_qs)
@@ -14100,20 +14029,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs),
.wd (mio_pad_sleep_en_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[25].q ),
+ .q (reg2hw.mio_pad_sleep_en[25].q),
// to register interface (read)
.qs (mio_pad_sleep_en_25_qs)
@@ -14127,20 +14056,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs),
.wd (mio_pad_sleep_en_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[26].q ),
+ .q (reg2hw.mio_pad_sleep_en[26].q),
// to register interface (read)
.qs (mio_pad_sleep_en_26_qs)
@@ -14154,20 +14083,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs),
.wd (mio_pad_sleep_en_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[27].q ),
+ .q (reg2hw.mio_pad_sleep_en[27].q),
// to register interface (read)
.qs (mio_pad_sleep_en_27_qs)
@@ -14181,20 +14110,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs),
.wd (mio_pad_sleep_en_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[28].q ),
+ .q (reg2hw.mio_pad_sleep_en[28].q),
// to register interface (read)
.qs (mio_pad_sleep_en_28_qs)
@@ -14208,20 +14137,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs),
.wd (mio_pad_sleep_en_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[29].q ),
+ .q (reg2hw.mio_pad_sleep_en[29].q),
// to register interface (read)
.qs (mio_pad_sleep_en_29_qs)
@@ -14235,20 +14164,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs),
.wd (mio_pad_sleep_en_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[30].q ),
+ .q (reg2hw.mio_pad_sleep_en[30].q),
// to register interface (read)
.qs (mio_pad_sleep_en_30_qs)
@@ -14262,20 +14191,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs),
.wd (mio_pad_sleep_en_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[31].q ),
+ .q (reg2hw.mio_pad_sleep_en[31].q),
// to register interface (read)
.qs (mio_pad_sleep_en_31_qs)
@@ -14289,20 +14218,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_32_we & mio_pad_sleep_regwen_32_qs),
.wd (mio_pad_sleep_en_32_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[32].q ),
+ .q (reg2hw.mio_pad_sleep_en[32].q),
// to register interface (read)
.qs (mio_pad_sleep_en_32_qs)
@@ -14316,20 +14245,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_33_we & mio_pad_sleep_regwen_33_qs),
.wd (mio_pad_sleep_en_33_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[33].q ),
+ .q (reg2hw.mio_pad_sleep_en[33].q),
// to register interface (read)
.qs (mio_pad_sleep_en_33_qs)
@@ -14343,20 +14272,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_34_we & mio_pad_sleep_regwen_34_qs),
.wd (mio_pad_sleep_en_34_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[34].q ),
+ .q (reg2hw.mio_pad_sleep_en[34].q),
// to register interface (read)
.qs (mio_pad_sleep_en_34_qs)
@@ -14370,20 +14299,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_35_we & mio_pad_sleep_regwen_35_qs),
.wd (mio_pad_sleep_en_35_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[35].q ),
+ .q (reg2hw.mio_pad_sleep_en[35].q),
// to register interface (read)
.qs (mio_pad_sleep_en_35_qs)
@@ -14397,20 +14326,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_36_we & mio_pad_sleep_regwen_36_qs),
.wd (mio_pad_sleep_en_36_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[36].q ),
+ .q (reg2hw.mio_pad_sleep_en[36].q),
// to register interface (read)
.qs (mio_pad_sleep_en_36_qs)
@@ -14424,20 +14353,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_37_we & mio_pad_sleep_regwen_37_qs),
.wd (mio_pad_sleep_en_37_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[37].q ),
+ .q (reg2hw.mio_pad_sleep_en[37].q),
// to register interface (read)
.qs (mio_pad_sleep_en_37_qs)
@@ -14451,20 +14380,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_38_we & mio_pad_sleep_regwen_38_qs),
.wd (mio_pad_sleep_en_38_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[38].q ),
+ .q (reg2hw.mio_pad_sleep_en[38].q),
// to register interface (read)
.qs (mio_pad_sleep_en_38_qs)
@@ -14478,20 +14407,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_39_we & mio_pad_sleep_regwen_39_qs),
.wd (mio_pad_sleep_en_39_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[39].q ),
+ .q (reg2hw.mio_pad_sleep_en[39].q),
// to register interface (read)
.qs (mio_pad_sleep_en_39_qs)
@@ -14505,20 +14434,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_40_we & mio_pad_sleep_regwen_40_qs),
.wd (mio_pad_sleep_en_40_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[40].q ),
+ .q (reg2hw.mio_pad_sleep_en[40].q),
// to register interface (read)
.qs (mio_pad_sleep_en_40_qs)
@@ -14532,20 +14461,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_41_we & mio_pad_sleep_regwen_41_qs),
.wd (mio_pad_sleep_en_41_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[41].q ),
+ .q (reg2hw.mio_pad_sleep_en[41].q),
// to register interface (read)
.qs (mio_pad_sleep_en_41_qs)
@@ -14559,20 +14488,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_42_we & mio_pad_sleep_regwen_42_qs),
.wd (mio_pad_sleep_en_42_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[42].q ),
+ .q (reg2hw.mio_pad_sleep_en[42].q),
// to register interface (read)
.qs (mio_pad_sleep_en_42_qs)
@@ -14586,20 +14515,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs),
.wd (mio_pad_sleep_en_43_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[43].q ),
+ .q (reg2hw.mio_pad_sleep_en[43].q),
// to register interface (read)
.qs (mio_pad_sleep_en_43_qs)
@@ -14613,20 +14542,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs),
.wd (mio_pad_sleep_en_44_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[44].q ),
+ .q (reg2hw.mio_pad_sleep_en[44].q),
// to register interface (read)
.qs (mio_pad_sleep_en_44_qs)
@@ -14640,20 +14569,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs),
.wd (mio_pad_sleep_en_45_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[45].q ),
+ .q (reg2hw.mio_pad_sleep_en[45].q),
// to register interface (read)
.qs (mio_pad_sleep_en_45_qs)
@@ -14667,20 +14596,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_mio_pad_sleep_en_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs),
.wd (mio_pad_sleep_en_46_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_en[46].q ),
+ .q (reg2hw.mio_pad_sleep_en[46].q),
// to register interface (read)
.qs (mio_pad_sleep_en_46_qs)
@@ -14696,20 +14625,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs),
.wd (mio_pad_sleep_mode_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[0].q ),
+ .q (reg2hw.mio_pad_sleep_mode[0].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_0_qs)
@@ -14723,20 +14652,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs),
.wd (mio_pad_sleep_mode_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[1].q ),
+ .q (reg2hw.mio_pad_sleep_mode[1].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_1_qs)
@@ -14750,20 +14679,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs),
.wd (mio_pad_sleep_mode_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[2].q ),
+ .q (reg2hw.mio_pad_sleep_mode[2].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_2_qs)
@@ -14777,20 +14706,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs),
.wd (mio_pad_sleep_mode_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[3].q ),
+ .q (reg2hw.mio_pad_sleep_mode[3].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_3_qs)
@@ -14804,20 +14733,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs),
.wd (mio_pad_sleep_mode_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[4].q ),
+ .q (reg2hw.mio_pad_sleep_mode[4].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_4_qs)
@@ -14831,20 +14760,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs),
.wd (mio_pad_sleep_mode_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[5].q ),
+ .q (reg2hw.mio_pad_sleep_mode[5].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_5_qs)
@@ -14858,20 +14787,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs),
.wd (mio_pad_sleep_mode_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[6].q ),
+ .q (reg2hw.mio_pad_sleep_mode[6].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_6_qs)
@@ -14885,20 +14814,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs),
.wd (mio_pad_sleep_mode_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[7].q ),
+ .q (reg2hw.mio_pad_sleep_mode[7].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_7_qs)
@@ -14912,20 +14841,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs),
.wd (mio_pad_sleep_mode_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[8].q ),
+ .q (reg2hw.mio_pad_sleep_mode[8].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_8_qs)
@@ -14939,20 +14868,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs),
.wd (mio_pad_sleep_mode_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[9].q ),
+ .q (reg2hw.mio_pad_sleep_mode[9].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_9_qs)
@@ -14966,20 +14895,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs),
.wd (mio_pad_sleep_mode_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[10].q ),
+ .q (reg2hw.mio_pad_sleep_mode[10].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_10_qs)
@@ -14993,20 +14922,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs),
.wd (mio_pad_sleep_mode_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[11].q ),
+ .q (reg2hw.mio_pad_sleep_mode[11].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_11_qs)
@@ -15020,20 +14949,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_12_we & mio_pad_sleep_regwen_12_qs),
.wd (mio_pad_sleep_mode_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[12].q ),
+ .q (reg2hw.mio_pad_sleep_mode[12].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_12_qs)
@@ -15047,20 +14976,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_13_we & mio_pad_sleep_regwen_13_qs),
.wd (mio_pad_sleep_mode_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[13].q ),
+ .q (reg2hw.mio_pad_sleep_mode[13].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_13_qs)
@@ -15074,20 +15003,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_14_we & mio_pad_sleep_regwen_14_qs),
.wd (mio_pad_sleep_mode_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[14].q ),
+ .q (reg2hw.mio_pad_sleep_mode[14].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_14_qs)
@@ -15101,20 +15030,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_15_we & mio_pad_sleep_regwen_15_qs),
.wd (mio_pad_sleep_mode_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[15].q ),
+ .q (reg2hw.mio_pad_sleep_mode[15].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_15_qs)
@@ -15128,20 +15057,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_16_we & mio_pad_sleep_regwen_16_qs),
.wd (mio_pad_sleep_mode_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[16].q ),
+ .q (reg2hw.mio_pad_sleep_mode[16].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_16_qs)
@@ -15155,20 +15084,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_17_we & mio_pad_sleep_regwen_17_qs),
.wd (mio_pad_sleep_mode_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[17].q ),
+ .q (reg2hw.mio_pad_sleep_mode[17].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_17_qs)
@@ -15182,20 +15111,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_18_we & mio_pad_sleep_regwen_18_qs),
.wd (mio_pad_sleep_mode_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[18].q ),
+ .q (reg2hw.mio_pad_sleep_mode[18].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_18_qs)
@@ -15209,20 +15138,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_19_we & mio_pad_sleep_regwen_19_qs),
.wd (mio_pad_sleep_mode_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[19].q ),
+ .q (reg2hw.mio_pad_sleep_mode[19].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_19_qs)
@@ -15236,20 +15165,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_20_we & mio_pad_sleep_regwen_20_qs),
.wd (mio_pad_sleep_mode_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[20].q ),
+ .q (reg2hw.mio_pad_sleep_mode[20].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_20_qs)
@@ -15263,20 +15192,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_21_we & mio_pad_sleep_regwen_21_qs),
.wd (mio_pad_sleep_mode_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[21].q ),
+ .q (reg2hw.mio_pad_sleep_mode[21].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_21_qs)
@@ -15290,20 +15219,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_22_we & mio_pad_sleep_regwen_22_qs),
.wd (mio_pad_sleep_mode_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[22].q ),
+ .q (reg2hw.mio_pad_sleep_mode[22].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_22_qs)
@@ -15317,20 +15246,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_23_we & mio_pad_sleep_regwen_23_qs),
.wd (mio_pad_sleep_mode_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[23].q ),
+ .q (reg2hw.mio_pad_sleep_mode[23].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_23_qs)
@@ -15344,20 +15273,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_24_we & mio_pad_sleep_regwen_24_qs),
.wd (mio_pad_sleep_mode_24_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[24].q ),
+ .q (reg2hw.mio_pad_sleep_mode[24].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_24_qs)
@@ -15371,20 +15300,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_25_we & mio_pad_sleep_regwen_25_qs),
.wd (mio_pad_sleep_mode_25_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[25].q ),
+ .q (reg2hw.mio_pad_sleep_mode[25].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_25_qs)
@@ -15398,20 +15327,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_26_we & mio_pad_sleep_regwen_26_qs),
.wd (mio_pad_sleep_mode_26_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[26].q ),
+ .q (reg2hw.mio_pad_sleep_mode[26].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_26_qs)
@@ -15425,20 +15354,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_27_we & mio_pad_sleep_regwen_27_qs),
.wd (mio_pad_sleep_mode_27_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[27].q ),
+ .q (reg2hw.mio_pad_sleep_mode[27].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_27_qs)
@@ -15452,20 +15381,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_28_we & mio_pad_sleep_regwen_28_qs),
.wd (mio_pad_sleep_mode_28_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[28].q ),
+ .q (reg2hw.mio_pad_sleep_mode[28].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_28_qs)
@@ -15479,20 +15408,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_29_we & mio_pad_sleep_regwen_29_qs),
.wd (mio_pad_sleep_mode_29_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[29].q ),
+ .q (reg2hw.mio_pad_sleep_mode[29].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_29_qs)
@@ -15506,20 +15435,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_30_we & mio_pad_sleep_regwen_30_qs),
.wd (mio_pad_sleep_mode_30_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[30].q ),
+ .q (reg2hw.mio_pad_sleep_mode[30].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_30_qs)
@@ -15533,20 +15462,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_31_we & mio_pad_sleep_regwen_31_qs),
.wd (mio_pad_sleep_mode_31_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[31].q ),
+ .q (reg2hw.mio_pad_sleep_mode[31].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_31_qs)
@@ -15560,20 +15489,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_32_we & mio_pad_sleep_regwen_32_qs),
.wd (mio_pad_sleep_mode_32_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[32].q ),
+ .q (reg2hw.mio_pad_sleep_mode[32].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_32_qs)
@@ -15587,20 +15516,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_33_we & mio_pad_sleep_regwen_33_qs),
.wd (mio_pad_sleep_mode_33_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[33].q ),
+ .q (reg2hw.mio_pad_sleep_mode[33].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_33_qs)
@@ -15614,20 +15543,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_34_we & mio_pad_sleep_regwen_34_qs),
.wd (mio_pad_sleep_mode_34_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[34].q ),
+ .q (reg2hw.mio_pad_sleep_mode[34].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_34_qs)
@@ -15641,20 +15570,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_35_we & mio_pad_sleep_regwen_35_qs),
.wd (mio_pad_sleep_mode_35_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[35].q ),
+ .q (reg2hw.mio_pad_sleep_mode[35].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_35_qs)
@@ -15668,20 +15597,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_36_we & mio_pad_sleep_regwen_36_qs),
.wd (mio_pad_sleep_mode_36_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[36].q ),
+ .q (reg2hw.mio_pad_sleep_mode[36].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_36_qs)
@@ -15695,20 +15624,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_37_we & mio_pad_sleep_regwen_37_qs),
.wd (mio_pad_sleep_mode_37_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[37].q ),
+ .q (reg2hw.mio_pad_sleep_mode[37].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_37_qs)
@@ -15722,20 +15651,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_38_we & mio_pad_sleep_regwen_38_qs),
.wd (mio_pad_sleep_mode_38_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[38].q ),
+ .q (reg2hw.mio_pad_sleep_mode[38].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_38_qs)
@@ -15749,20 +15678,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_39_we & mio_pad_sleep_regwen_39_qs),
.wd (mio_pad_sleep_mode_39_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[39].q ),
+ .q (reg2hw.mio_pad_sleep_mode[39].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_39_qs)
@@ -15776,20 +15705,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_40_we & mio_pad_sleep_regwen_40_qs),
.wd (mio_pad_sleep_mode_40_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[40].q ),
+ .q (reg2hw.mio_pad_sleep_mode[40].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_40_qs)
@@ -15803,20 +15732,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_41_we & mio_pad_sleep_regwen_41_qs),
.wd (mio_pad_sleep_mode_41_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[41].q ),
+ .q (reg2hw.mio_pad_sleep_mode[41].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_41_qs)
@@ -15830,20 +15759,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_42_we & mio_pad_sleep_regwen_42_qs),
.wd (mio_pad_sleep_mode_42_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[42].q ),
+ .q (reg2hw.mio_pad_sleep_mode[42].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_42_qs)
@@ -15857,20 +15786,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_43_we & mio_pad_sleep_regwen_43_qs),
.wd (mio_pad_sleep_mode_43_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[43].q ),
+ .q (reg2hw.mio_pad_sleep_mode[43].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_43_qs)
@@ -15884,20 +15813,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_44_we & mio_pad_sleep_regwen_44_qs),
.wd (mio_pad_sleep_mode_44_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[44].q ),
+ .q (reg2hw.mio_pad_sleep_mode[44].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_44_qs)
@@ -15911,20 +15840,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_45_we & mio_pad_sleep_regwen_45_qs),
.wd (mio_pad_sleep_mode_45_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[45].q ),
+ .q (reg2hw.mio_pad_sleep_mode[45].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_45_qs)
@@ -15938,20 +15867,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_mio_pad_sleep_mode_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (mio_pad_sleep_mode_46_we & mio_pad_sleep_regwen_46_qs),
.wd (mio_pad_sleep_mode_46_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.mio_pad_sleep_mode[46].q ),
+ .q (reg2hw.mio_pad_sleep_mode[46].q),
// to register interface (read)
.qs (mio_pad_sleep_mode_46_qs)
@@ -15968,8 +15897,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_0_we),
@@ -15977,11 +15906,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[0].de),
- .d (hw2reg.dio_pad_sleep_status[0].d ),
+ .d (hw2reg.dio_pad_sleep_status[0].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[0].q ),
+ .q (reg2hw.dio_pad_sleep_status[0].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_0_qs)
@@ -15994,8 +15923,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_1_we),
@@ -16003,11 +15932,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[1].de),
- .d (hw2reg.dio_pad_sleep_status[1].d ),
+ .d (hw2reg.dio_pad_sleep_status[1].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[1].q ),
+ .q (reg2hw.dio_pad_sleep_status[1].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_1_qs)
@@ -16020,8 +15949,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_2_we),
@@ -16029,11 +15958,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[2].de),
- .d (hw2reg.dio_pad_sleep_status[2].d ),
+ .d (hw2reg.dio_pad_sleep_status[2].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[2].q ),
+ .q (reg2hw.dio_pad_sleep_status[2].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_2_qs)
@@ -16046,8 +15975,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_3_we),
@@ -16055,11 +15984,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[3].de),
- .d (hw2reg.dio_pad_sleep_status[3].d ),
+ .d (hw2reg.dio_pad_sleep_status[3].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[3].q ),
+ .q (reg2hw.dio_pad_sleep_status[3].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_3_qs)
@@ -16072,8 +16001,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_4_we),
@@ -16081,11 +16010,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[4].de),
- .d (hw2reg.dio_pad_sleep_status[4].d ),
+ .d (hw2reg.dio_pad_sleep_status[4].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[4].q ),
+ .q (reg2hw.dio_pad_sleep_status[4].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_4_qs)
@@ -16098,8 +16027,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_5_we),
@@ -16107,11 +16036,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[5].de),
- .d (hw2reg.dio_pad_sleep_status[5].d ),
+ .d (hw2reg.dio_pad_sleep_status[5].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[5].q ),
+ .q (reg2hw.dio_pad_sleep_status[5].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_5_qs)
@@ -16124,8 +16053,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_6_we),
@@ -16133,11 +16062,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[6].de),
- .d (hw2reg.dio_pad_sleep_status[6].d ),
+ .d (hw2reg.dio_pad_sleep_status[6].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[6].q ),
+ .q (reg2hw.dio_pad_sleep_status[6].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_6_qs)
@@ -16150,8 +16079,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_7_we),
@@ -16159,11 +16088,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[7].de),
- .d (hw2reg.dio_pad_sleep_status[7].d ),
+ .d (hw2reg.dio_pad_sleep_status[7].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[7].q ),
+ .q (reg2hw.dio_pad_sleep_status[7].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_7_qs)
@@ -16176,8 +16105,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_8_we),
@@ -16185,11 +16114,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[8].de),
- .d (hw2reg.dio_pad_sleep_status[8].d ),
+ .d (hw2reg.dio_pad_sleep_status[8].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[8].q ),
+ .q (reg2hw.dio_pad_sleep_status[8].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_8_qs)
@@ -16202,8 +16131,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_9_we),
@@ -16211,11 +16140,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[9].de),
- .d (hw2reg.dio_pad_sleep_status[9].d ),
+ .d (hw2reg.dio_pad_sleep_status[9].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[9].q ),
+ .q (reg2hw.dio_pad_sleep_status[9].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_9_qs)
@@ -16228,8 +16157,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_10_we),
@@ -16237,11 +16166,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[10].de),
- .d (hw2reg.dio_pad_sleep_status[10].d ),
+ .d (hw2reg.dio_pad_sleep_status[10].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[10].q ),
+ .q (reg2hw.dio_pad_sleep_status[10].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_10_qs)
@@ -16254,8 +16183,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_11_we),
@@ -16263,11 +16192,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[11].de),
- .d (hw2reg.dio_pad_sleep_status[11].d ),
+ .d (hw2reg.dio_pad_sleep_status[11].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[11].q ),
+ .q (reg2hw.dio_pad_sleep_status[11].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_11_qs)
@@ -16280,8 +16209,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_12_we),
@@ -16289,11 +16218,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[12].de),
- .d (hw2reg.dio_pad_sleep_status[12].d ),
+ .d (hw2reg.dio_pad_sleep_status[12].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[12].q ),
+ .q (reg2hw.dio_pad_sleep_status[12].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_12_qs)
@@ -16306,8 +16235,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_13_we),
@@ -16315,11 +16244,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[13].de),
- .d (hw2reg.dio_pad_sleep_status[13].d ),
+ .d (hw2reg.dio_pad_sleep_status[13].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[13].q ),
+ .q (reg2hw.dio_pad_sleep_status[13].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_13_qs)
@@ -16332,8 +16261,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_14_we),
@@ -16341,11 +16270,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[14].de),
- .d (hw2reg.dio_pad_sleep_status[14].d ),
+ .d (hw2reg.dio_pad_sleep_status[14].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[14].q ),
+ .q (reg2hw.dio_pad_sleep_status[14].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_14_qs)
@@ -16358,8 +16287,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_15_we),
@@ -16367,11 +16296,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[15].de),
- .d (hw2reg.dio_pad_sleep_status[15].d ),
+ .d (hw2reg.dio_pad_sleep_status[15].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[15].q ),
+ .q (reg2hw.dio_pad_sleep_status[15].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_15_qs)
@@ -16384,8 +16313,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_16_we),
@@ -16393,11 +16322,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[16].de),
- .d (hw2reg.dio_pad_sleep_status[16].d ),
+ .d (hw2reg.dio_pad_sleep_status[16].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[16].q ),
+ .q (reg2hw.dio_pad_sleep_status[16].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_16_qs)
@@ -16410,8 +16339,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_17_we),
@@ -16419,11 +16348,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[17].de),
- .d (hw2reg.dio_pad_sleep_status[17].d ),
+ .d (hw2reg.dio_pad_sleep_status[17].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[17].q ),
+ .q (reg2hw.dio_pad_sleep_status[17].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_17_qs)
@@ -16436,8 +16365,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_18_we),
@@ -16445,11 +16374,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[18].de),
- .d (hw2reg.dio_pad_sleep_status[18].d ),
+ .d (hw2reg.dio_pad_sleep_status[18].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[18].q ),
+ .q (reg2hw.dio_pad_sleep_status[18].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_18_qs)
@@ -16462,8 +16391,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_19_we),
@@ -16471,11 +16400,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[19].de),
- .d (hw2reg.dio_pad_sleep_status[19].d ),
+ .d (hw2reg.dio_pad_sleep_status[19].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[19].q ),
+ .q (reg2hw.dio_pad_sleep_status[19].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_19_qs)
@@ -16488,8 +16417,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_20_we),
@@ -16497,11 +16426,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[20].de),
- .d (hw2reg.dio_pad_sleep_status[20].d ),
+ .d (hw2reg.dio_pad_sleep_status[20].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[20].q ),
+ .q (reg2hw.dio_pad_sleep_status[20].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_20_qs)
@@ -16514,8 +16443,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_21_we),
@@ -16523,11 +16452,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[21].de),
- .d (hw2reg.dio_pad_sleep_status[21].d ),
+ .d (hw2reg.dio_pad_sleep_status[21].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[21].q ),
+ .q (reg2hw.dio_pad_sleep_status[21].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_21_qs)
@@ -16540,8 +16469,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_22_we),
@@ -16549,11 +16478,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[22].de),
- .d (hw2reg.dio_pad_sleep_status[22].d ),
+ .d (hw2reg.dio_pad_sleep_status[22].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[22].q ),
+ .q (reg2hw.dio_pad_sleep_status[22].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_22_qs)
@@ -16566,8 +16495,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h0)
) u_dio_pad_sleep_status_en_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_status_en_23_we),
@@ -16575,11 +16504,11 @@
// from internal hardware
.de (hw2reg.dio_pad_sleep_status[23].de),
- .d (hw2reg.dio_pad_sleep_status[23].d ),
+ .d (hw2reg.dio_pad_sleep_status[23].d),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_status[23].q ),
+ .q (reg2hw.dio_pad_sleep_status[23].q),
// to register interface (read)
.qs (dio_pad_sleep_status_en_23_qs)
@@ -16596,8 +16525,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_0_we),
@@ -16605,7 +16534,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16623,8 +16552,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_1_we),
@@ -16632,7 +16561,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16650,8 +16579,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_2_we),
@@ -16659,7 +16588,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16677,8 +16606,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_3_we),
@@ -16686,7 +16615,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16704,8 +16633,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_4_we),
@@ -16713,7 +16642,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16731,8 +16660,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_5_we),
@@ -16740,7 +16669,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16758,8 +16687,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_6_we),
@@ -16767,7 +16696,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16785,8 +16714,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_7_we),
@@ -16794,7 +16723,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16812,8 +16741,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_8_we),
@@ -16821,7 +16750,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16839,8 +16768,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_9_we),
@@ -16848,7 +16777,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16866,8 +16795,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_10_we),
@@ -16875,7 +16804,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16893,8 +16822,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_11_we),
@@ -16902,7 +16831,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16920,8 +16849,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_12_we),
@@ -16929,7 +16858,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16947,8 +16876,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_13_we),
@@ -16956,7 +16885,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -16974,8 +16903,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_14_we),
@@ -16983,7 +16912,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17001,8 +16930,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_15_we),
@@ -17010,7 +16939,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17028,8 +16957,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_16_we),
@@ -17037,7 +16966,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17055,8 +16984,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_17_we),
@@ -17064,7 +16993,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17082,8 +17011,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_18_we),
@@ -17091,7 +17020,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17109,8 +17038,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_19_we),
@@ -17118,7 +17047,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17136,8 +17065,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_20_we),
@@ -17145,7 +17074,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17163,8 +17092,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_21_we),
@@ -17172,7 +17101,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17190,8 +17119,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_22_we),
@@ -17199,7 +17128,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17217,8 +17146,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_dio_pad_sleep_regwen_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (dio_pad_sleep_regwen_23_we),
@@ -17226,7 +17155,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -17246,20 +17175,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs),
.wd (dio_pad_sleep_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[0].q ),
+ .q (reg2hw.dio_pad_sleep_en[0].q),
// to register interface (read)
.qs (dio_pad_sleep_en_0_qs)
@@ -17273,20 +17202,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs),
.wd (dio_pad_sleep_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[1].q ),
+ .q (reg2hw.dio_pad_sleep_en[1].q),
// to register interface (read)
.qs (dio_pad_sleep_en_1_qs)
@@ -17300,20 +17229,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs),
.wd (dio_pad_sleep_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[2].q ),
+ .q (reg2hw.dio_pad_sleep_en[2].q),
// to register interface (read)
.qs (dio_pad_sleep_en_2_qs)
@@ -17327,20 +17256,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs),
.wd (dio_pad_sleep_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[3].q ),
+ .q (reg2hw.dio_pad_sleep_en[3].q),
// to register interface (read)
.qs (dio_pad_sleep_en_3_qs)
@@ -17354,20 +17283,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs),
.wd (dio_pad_sleep_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[4].q ),
+ .q (reg2hw.dio_pad_sleep_en[4].q),
// to register interface (read)
.qs (dio_pad_sleep_en_4_qs)
@@ -17381,20 +17310,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs),
.wd (dio_pad_sleep_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[5].q ),
+ .q (reg2hw.dio_pad_sleep_en[5].q),
// to register interface (read)
.qs (dio_pad_sleep_en_5_qs)
@@ -17408,20 +17337,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs),
.wd (dio_pad_sleep_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[6].q ),
+ .q (reg2hw.dio_pad_sleep_en[6].q),
// to register interface (read)
.qs (dio_pad_sleep_en_6_qs)
@@ -17435,20 +17364,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs),
.wd (dio_pad_sleep_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[7].q ),
+ .q (reg2hw.dio_pad_sleep_en[7].q),
// to register interface (read)
.qs (dio_pad_sleep_en_7_qs)
@@ -17462,20 +17391,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs),
.wd (dio_pad_sleep_en_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[8].q ),
+ .q (reg2hw.dio_pad_sleep_en[8].q),
// to register interface (read)
.qs (dio_pad_sleep_en_8_qs)
@@ -17489,20 +17418,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs),
.wd (dio_pad_sleep_en_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[9].q ),
+ .q (reg2hw.dio_pad_sleep_en[9].q),
// to register interface (read)
.qs (dio_pad_sleep_en_9_qs)
@@ -17516,20 +17445,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs),
.wd (dio_pad_sleep_en_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[10].q ),
+ .q (reg2hw.dio_pad_sleep_en[10].q),
// to register interface (read)
.qs (dio_pad_sleep_en_10_qs)
@@ -17543,20 +17472,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs),
.wd (dio_pad_sleep_en_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[11].q ),
+ .q (reg2hw.dio_pad_sleep_en[11].q),
// to register interface (read)
.qs (dio_pad_sleep_en_11_qs)
@@ -17570,20 +17499,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs),
.wd (dio_pad_sleep_en_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[12].q ),
+ .q (reg2hw.dio_pad_sleep_en[12].q),
// to register interface (read)
.qs (dio_pad_sleep_en_12_qs)
@@ -17597,20 +17526,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs),
.wd (dio_pad_sleep_en_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[13].q ),
+ .q (reg2hw.dio_pad_sleep_en[13].q),
// to register interface (read)
.qs (dio_pad_sleep_en_13_qs)
@@ -17624,20 +17553,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs),
.wd (dio_pad_sleep_en_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[14].q ),
+ .q (reg2hw.dio_pad_sleep_en[14].q),
// to register interface (read)
.qs (dio_pad_sleep_en_14_qs)
@@ -17651,20 +17580,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs),
.wd (dio_pad_sleep_en_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[15].q ),
+ .q (reg2hw.dio_pad_sleep_en[15].q),
// to register interface (read)
.qs (dio_pad_sleep_en_15_qs)
@@ -17678,20 +17607,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_16_we & dio_pad_sleep_regwen_16_qs),
.wd (dio_pad_sleep_en_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[16].q ),
+ .q (reg2hw.dio_pad_sleep_en[16].q),
// to register interface (read)
.qs (dio_pad_sleep_en_16_qs)
@@ -17705,20 +17634,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_17_we & dio_pad_sleep_regwen_17_qs),
.wd (dio_pad_sleep_en_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[17].q ),
+ .q (reg2hw.dio_pad_sleep_en[17].q),
// to register interface (read)
.qs (dio_pad_sleep_en_17_qs)
@@ -17732,20 +17661,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_18_we & dio_pad_sleep_regwen_18_qs),
.wd (dio_pad_sleep_en_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[18].q ),
+ .q (reg2hw.dio_pad_sleep_en[18].q),
// to register interface (read)
.qs (dio_pad_sleep_en_18_qs)
@@ -17759,20 +17688,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_19_we & dio_pad_sleep_regwen_19_qs),
.wd (dio_pad_sleep_en_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[19].q ),
+ .q (reg2hw.dio_pad_sleep_en[19].q),
// to register interface (read)
.qs (dio_pad_sleep_en_19_qs)
@@ -17786,20 +17715,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_20_we & dio_pad_sleep_regwen_20_qs),
.wd (dio_pad_sleep_en_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[20].q ),
+ .q (reg2hw.dio_pad_sleep_en[20].q),
// to register interface (read)
.qs (dio_pad_sleep_en_20_qs)
@@ -17813,20 +17742,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_21_we & dio_pad_sleep_regwen_21_qs),
.wd (dio_pad_sleep_en_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[21].q ),
+ .q (reg2hw.dio_pad_sleep_en[21].q),
// to register interface (read)
.qs (dio_pad_sleep_en_21_qs)
@@ -17840,20 +17769,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_22_we & dio_pad_sleep_regwen_22_qs),
.wd (dio_pad_sleep_en_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[22].q ),
+ .q (reg2hw.dio_pad_sleep_en[22].q),
// to register interface (read)
.qs (dio_pad_sleep_en_22_qs)
@@ -17867,20 +17796,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_dio_pad_sleep_en_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_en_23_we & dio_pad_sleep_regwen_23_qs),
.wd (dio_pad_sleep_en_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_en[23].q ),
+ .q (reg2hw.dio_pad_sleep_en[23].q),
// to register interface (read)
.qs (dio_pad_sleep_en_23_qs)
@@ -17896,20 +17825,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs),
.wd (dio_pad_sleep_mode_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[0].q ),
+ .q (reg2hw.dio_pad_sleep_mode[0].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_0_qs)
@@ -17923,20 +17852,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs),
.wd (dio_pad_sleep_mode_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[1].q ),
+ .q (reg2hw.dio_pad_sleep_mode[1].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_1_qs)
@@ -17950,20 +17879,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs),
.wd (dio_pad_sleep_mode_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[2].q ),
+ .q (reg2hw.dio_pad_sleep_mode[2].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_2_qs)
@@ -17977,20 +17906,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs),
.wd (dio_pad_sleep_mode_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[3].q ),
+ .q (reg2hw.dio_pad_sleep_mode[3].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_3_qs)
@@ -18004,20 +17933,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs),
.wd (dio_pad_sleep_mode_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[4].q ),
+ .q (reg2hw.dio_pad_sleep_mode[4].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_4_qs)
@@ -18031,20 +17960,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs),
.wd (dio_pad_sleep_mode_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[5].q ),
+ .q (reg2hw.dio_pad_sleep_mode[5].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_5_qs)
@@ -18058,20 +17987,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs),
.wd (dio_pad_sleep_mode_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[6].q ),
+ .q (reg2hw.dio_pad_sleep_mode[6].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_6_qs)
@@ -18085,20 +18014,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs),
.wd (dio_pad_sleep_mode_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[7].q ),
+ .q (reg2hw.dio_pad_sleep_mode[7].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_7_qs)
@@ -18112,20 +18041,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs),
.wd (dio_pad_sleep_mode_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[8].q ),
+ .q (reg2hw.dio_pad_sleep_mode[8].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_8_qs)
@@ -18139,20 +18068,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs),
.wd (dio_pad_sleep_mode_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[9].q ),
+ .q (reg2hw.dio_pad_sleep_mode[9].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_9_qs)
@@ -18166,20 +18095,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs),
.wd (dio_pad_sleep_mode_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[10].q ),
+ .q (reg2hw.dio_pad_sleep_mode[10].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_10_qs)
@@ -18193,20 +18122,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs),
.wd (dio_pad_sleep_mode_11_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[11].q ),
+ .q (reg2hw.dio_pad_sleep_mode[11].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_11_qs)
@@ -18220,20 +18149,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs),
.wd (dio_pad_sleep_mode_12_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[12].q ),
+ .q (reg2hw.dio_pad_sleep_mode[12].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_12_qs)
@@ -18247,20 +18176,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs),
.wd (dio_pad_sleep_mode_13_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[13].q ),
+ .q (reg2hw.dio_pad_sleep_mode[13].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_13_qs)
@@ -18274,20 +18203,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs),
.wd (dio_pad_sleep_mode_14_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[14].q ),
+ .q (reg2hw.dio_pad_sleep_mode[14].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_14_qs)
@@ -18301,20 +18230,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs),
.wd (dio_pad_sleep_mode_15_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[15].q ),
+ .q (reg2hw.dio_pad_sleep_mode[15].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_15_qs)
@@ -18328,20 +18257,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_16_we & dio_pad_sleep_regwen_16_qs),
.wd (dio_pad_sleep_mode_16_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[16].q ),
+ .q (reg2hw.dio_pad_sleep_mode[16].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_16_qs)
@@ -18355,20 +18284,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_17_we & dio_pad_sleep_regwen_17_qs),
.wd (dio_pad_sleep_mode_17_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[17].q ),
+ .q (reg2hw.dio_pad_sleep_mode[17].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_17_qs)
@@ -18382,20 +18311,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_18_we & dio_pad_sleep_regwen_18_qs),
.wd (dio_pad_sleep_mode_18_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[18].q ),
+ .q (reg2hw.dio_pad_sleep_mode[18].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_18_qs)
@@ -18409,20 +18338,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_19_we & dio_pad_sleep_regwen_19_qs),
.wd (dio_pad_sleep_mode_19_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[19].q ),
+ .q (reg2hw.dio_pad_sleep_mode[19].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_19_qs)
@@ -18436,20 +18365,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_20_we & dio_pad_sleep_regwen_20_qs),
.wd (dio_pad_sleep_mode_20_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[20].q ),
+ .q (reg2hw.dio_pad_sleep_mode[20].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_20_qs)
@@ -18463,20 +18392,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_21_we & dio_pad_sleep_regwen_21_qs),
.wd (dio_pad_sleep_mode_21_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[21].q ),
+ .q (reg2hw.dio_pad_sleep_mode[21].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_21_qs)
@@ -18490,20 +18419,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_22_we & dio_pad_sleep_regwen_22_qs),
.wd (dio_pad_sleep_mode_22_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[22].q ),
+ .q (reg2hw.dio_pad_sleep_mode[22].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_22_qs)
@@ -18517,20 +18446,20 @@
.SWACCESS("RW"),
.RESVAL (2'h2)
) u_dio_pad_sleep_mode_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (dio_pad_sleep_mode_23_we & dio_pad_sleep_regwen_23_qs),
.wd (dio_pad_sleep_mode_23_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.dio_pad_sleep_mode[23].q ),
+ .q (reg2hw.dio_pad_sleep_mode[23].q),
// to register interface (read)
.qs (dio_pad_sleep_mode_23_qs)
@@ -18546,8 +18475,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_0_we),
@@ -18555,7 +18484,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -18573,8 +18502,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_1_we),
@@ -18582,7 +18511,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -18600,8 +18529,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_2_we),
@@ -18609,7 +18538,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -18627,8 +18556,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_3_we),
@@ -18636,7 +18565,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -18654,8 +18583,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_4_we),
@@ -18663,7 +18592,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -18681,8 +18610,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_5_we),
@@ -18690,7 +18619,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -18708,8 +18637,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_6_we),
@@ -18717,7 +18646,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -18735,8 +18664,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wkup_detector_regwen_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wkup_detector_regwen_7_we),
@@ -18744,7 +18673,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -18764,20 +18693,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[0].q ),
+ .q (reg2hw.wkup_detector_en[0].q),
// to register interface (read)
.qs (wkup_detector_en_0_qs)
@@ -18791,20 +18720,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[1].q ),
+ .q (reg2hw.wkup_detector_en[1].q),
// to register interface (read)
.qs (wkup_detector_en_1_qs)
@@ -18818,20 +18747,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[2].q ),
+ .q (reg2hw.wkup_detector_en[2].q),
// to register interface (read)
.qs (wkup_detector_en_2_qs)
@@ -18845,20 +18774,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[3].q ),
+ .q (reg2hw.wkup_detector_en[3].q),
// to register interface (read)
.qs (wkup_detector_en_3_qs)
@@ -18872,20 +18801,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[4].q ),
+ .q (reg2hw.wkup_detector_en[4].q),
// to register interface (read)
.qs (wkup_detector_en_4_qs)
@@ -18899,20 +18828,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_en_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[5].q ),
+ .q (reg2hw.wkup_detector_en[5].q),
// to register interface (read)
.qs (wkup_detector_en_5_qs)
@@ -18926,20 +18855,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_en_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[6].q ),
+ .q (reg2hw.wkup_detector_en[6].q),
// to register interface (read)
.qs (wkup_detector_en_6_qs)
@@ -18953,20 +18882,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_en_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_en_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_en_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_en[7].q ),
+ .q (reg2hw.wkup_detector_en[7].q),
// to register interface (read)
.qs (wkup_detector_en_7_qs)
@@ -18983,20 +18912,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_0_mode_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_0_mode_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_0_mode_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[0].mode.q ),
+ .q (reg2hw.wkup_detector[0].mode.q),
// to register interface (read)
.qs (wkup_detector_0_mode_0_qs)
@@ -19009,20 +18938,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_0_filter_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_0_filter_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_0_filter_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[0].filter.q ),
+ .q (reg2hw.wkup_detector[0].filter.q),
// to register interface (read)
.qs (wkup_detector_0_filter_0_qs)
@@ -19035,20 +18964,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_0_miodio_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_0_miodio_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_0_miodio_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[0].miodio.q ),
+ .q (reg2hw.wkup_detector[0].miodio.q),
// to register interface (read)
.qs (wkup_detector_0_miodio_0_qs)
@@ -19064,20 +18993,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_1_mode_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_1_mode_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_1_mode_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[1].mode.q ),
+ .q (reg2hw.wkup_detector[1].mode.q),
// to register interface (read)
.qs (wkup_detector_1_mode_1_qs)
@@ -19090,20 +19019,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_1_filter_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_1_filter_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_1_filter_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[1].filter.q ),
+ .q (reg2hw.wkup_detector[1].filter.q),
// to register interface (read)
.qs (wkup_detector_1_filter_1_qs)
@@ -19116,20 +19045,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_1_miodio_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_1_miodio_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_1_miodio_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[1].miodio.q ),
+ .q (reg2hw.wkup_detector[1].miodio.q),
// to register interface (read)
.qs (wkup_detector_1_miodio_1_qs)
@@ -19145,20 +19074,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_2_mode_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_2_mode_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_2_mode_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[2].mode.q ),
+ .q (reg2hw.wkup_detector[2].mode.q),
// to register interface (read)
.qs (wkup_detector_2_mode_2_qs)
@@ -19171,20 +19100,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_2_filter_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_2_filter_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_2_filter_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[2].filter.q ),
+ .q (reg2hw.wkup_detector[2].filter.q),
// to register interface (read)
.qs (wkup_detector_2_filter_2_qs)
@@ -19197,20 +19126,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_2_miodio_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_2_miodio_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_2_miodio_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[2].miodio.q ),
+ .q (reg2hw.wkup_detector[2].miodio.q),
// to register interface (read)
.qs (wkup_detector_2_miodio_2_qs)
@@ -19226,20 +19155,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_3_mode_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_3_mode_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_3_mode_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[3].mode.q ),
+ .q (reg2hw.wkup_detector[3].mode.q),
// to register interface (read)
.qs (wkup_detector_3_mode_3_qs)
@@ -19252,20 +19181,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_3_filter_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_3_filter_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_3_filter_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[3].filter.q ),
+ .q (reg2hw.wkup_detector[3].filter.q),
// to register interface (read)
.qs (wkup_detector_3_filter_3_qs)
@@ -19278,20 +19207,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_3_miodio_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_3_miodio_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_3_miodio_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[3].miodio.q ),
+ .q (reg2hw.wkup_detector[3].miodio.q),
// to register interface (read)
.qs (wkup_detector_3_miodio_3_qs)
@@ -19307,20 +19236,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_4_mode_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_4_mode_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_4_mode_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[4].mode.q ),
+ .q (reg2hw.wkup_detector[4].mode.q),
// to register interface (read)
.qs (wkup_detector_4_mode_4_qs)
@@ -19333,20 +19262,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_4_filter_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_4_filter_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_4_filter_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[4].filter.q ),
+ .q (reg2hw.wkup_detector[4].filter.q),
// to register interface (read)
.qs (wkup_detector_4_filter_4_qs)
@@ -19359,20 +19288,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_4_miodio_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_4_miodio_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_4_miodio_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[4].miodio.q ),
+ .q (reg2hw.wkup_detector[4].miodio.q),
// to register interface (read)
.qs (wkup_detector_4_miodio_4_qs)
@@ -19388,20 +19317,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_5_mode_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_5_mode_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_5_mode_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[5].mode.q ),
+ .q (reg2hw.wkup_detector[5].mode.q),
// to register interface (read)
.qs (wkup_detector_5_mode_5_qs)
@@ -19414,20 +19343,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_5_filter_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_5_filter_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_5_filter_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[5].filter.q ),
+ .q (reg2hw.wkup_detector[5].filter.q),
// to register interface (read)
.qs (wkup_detector_5_filter_5_qs)
@@ -19440,20 +19369,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_5_miodio_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_5_miodio_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_5_miodio_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[5].miodio.q ),
+ .q (reg2hw.wkup_detector[5].miodio.q),
// to register interface (read)
.qs (wkup_detector_5_miodio_5_qs)
@@ -19469,20 +19398,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_6_mode_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_6_mode_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_6_mode_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[6].mode.q ),
+ .q (reg2hw.wkup_detector[6].mode.q),
// to register interface (read)
.qs (wkup_detector_6_mode_6_qs)
@@ -19495,20 +19424,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_6_filter_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_6_filter_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_6_filter_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[6].filter.q ),
+ .q (reg2hw.wkup_detector[6].filter.q),
// to register interface (read)
.qs (wkup_detector_6_filter_6_qs)
@@ -19521,20 +19450,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_6_miodio_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_6_miodio_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_6_miodio_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[6].miodio.q ),
+ .q (reg2hw.wkup_detector[6].miodio.q),
// to register interface (read)
.qs (wkup_detector_6_miodio_6_qs)
@@ -19550,20 +19479,20 @@
.SWACCESS("RW"),
.RESVAL (3'h0)
) u_wkup_detector_7_mode_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_7_mode_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_7_mode_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[7].mode.q ),
+ .q (reg2hw.wkup_detector[7].mode.q),
// to register interface (read)
.qs (wkup_detector_7_mode_7_qs)
@@ -19576,20 +19505,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_7_filter_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_7_filter_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_7_filter_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[7].filter.q ),
+ .q (reg2hw.wkup_detector[7].filter.q),
// to register interface (read)
.qs (wkup_detector_7_filter_7_qs)
@@ -19602,20 +19531,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wkup_detector_7_miodio_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_7_miodio_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_7_miodio_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector[7].miodio.q ),
+ .q (reg2hw.wkup_detector[7].miodio.q),
// to register interface (read)
.qs (wkup_detector_7_miodio_7_qs)
@@ -19632,20 +19561,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_cnt_th_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[0].q ),
+ .q (reg2hw.wkup_detector_cnt_th[0].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_0_qs)
@@ -19659,20 +19588,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_cnt_th_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[1].q ),
+ .q (reg2hw.wkup_detector_cnt_th[1].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_1_qs)
@@ -19686,20 +19615,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_cnt_th_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[2].q ),
+ .q (reg2hw.wkup_detector_cnt_th[2].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_2_qs)
@@ -19713,20 +19642,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_cnt_th_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[3].q ),
+ .q (reg2hw.wkup_detector_cnt_th[3].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_3_qs)
@@ -19740,20 +19669,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_cnt_th_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[4].q ),
+ .q (reg2hw.wkup_detector_cnt_th[4].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_4_qs)
@@ -19767,20 +19696,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_cnt_th_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[5].q ),
+ .q (reg2hw.wkup_detector_cnt_th[5].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_5_qs)
@@ -19794,20 +19723,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_cnt_th_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[6].q ),
+ .q (reg2hw.wkup_detector_cnt_th[6].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_6_qs)
@@ -19821,20 +19750,20 @@
.SWACCESS("RW"),
.RESVAL (8'h0)
) u_wkup_detector_cnt_th_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_cnt_th_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_cnt_th_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_cnt_th[7].q ),
+ .q (reg2hw.wkup_detector_cnt_th[7].q),
// to register interface (read)
.qs (wkup_detector_cnt_th_7_qs)
@@ -19850,20 +19779,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_0_we & wkup_detector_regwen_0_qs),
.wd (wkup_detector_padsel_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[0].q ),
+ .q (reg2hw.wkup_detector_padsel[0].q),
// to register interface (read)
.qs (wkup_detector_padsel_0_qs)
@@ -19877,20 +19806,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_1_we & wkup_detector_regwen_1_qs),
.wd (wkup_detector_padsel_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[1].q ),
+ .q (reg2hw.wkup_detector_padsel[1].q),
// to register interface (read)
.qs (wkup_detector_padsel_1_qs)
@@ -19904,20 +19833,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_2_we & wkup_detector_regwen_2_qs),
.wd (wkup_detector_padsel_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[2].q ),
+ .q (reg2hw.wkup_detector_padsel[2].q),
// to register interface (read)
.qs (wkup_detector_padsel_2_qs)
@@ -19931,20 +19860,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_3_we & wkup_detector_regwen_3_qs),
.wd (wkup_detector_padsel_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[3].q ),
+ .q (reg2hw.wkup_detector_padsel[3].q),
// to register interface (read)
.qs (wkup_detector_padsel_3_qs)
@@ -19958,20 +19887,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_4_we & wkup_detector_regwen_4_qs),
.wd (wkup_detector_padsel_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[4].q ),
+ .q (reg2hw.wkup_detector_padsel[4].q),
// to register interface (read)
.qs (wkup_detector_padsel_4_qs)
@@ -19985,20 +19914,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_5_we & wkup_detector_regwen_5_qs),
.wd (wkup_detector_padsel_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[5].q ),
+ .q (reg2hw.wkup_detector_padsel[5].q),
// to register interface (read)
.qs (wkup_detector_padsel_5_qs)
@@ -20012,20 +19941,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_6_we & wkup_detector_regwen_6_qs),
.wd (wkup_detector_padsel_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[6].q ),
+ .q (reg2hw.wkup_detector_padsel[6].q),
// to register interface (read)
.qs (wkup_detector_padsel_6_qs)
@@ -20039,20 +19968,20 @@
.SWACCESS("RW"),
.RESVAL (6'h0)
) u_wkup_detector_padsel_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wkup_detector_padsel_7_we & wkup_detector_regwen_7_qs),
.wd (wkup_detector_padsel_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wkup_detector_padsel[7].q ),
+ .q (reg2hw.wkup_detector_padsel[7].q),
// to register interface (read)
.qs (wkup_detector_padsel_7_qs)
@@ -20073,7 +20002,7 @@
.d (hw2reg.wkup_cause[0].d),
.qre (),
.qe (reg2hw.wkup_cause[0].qe),
- .q (reg2hw.wkup_cause[0].q ),
+ .q (reg2hw.wkup_cause[0].q),
.qs (wkup_cause_cause_0_qs)
);
@@ -20088,7 +20017,7 @@
.d (hw2reg.wkup_cause[1].d),
.qre (),
.qe (reg2hw.wkup_cause[1].qe),
- .q (reg2hw.wkup_cause[1].q ),
+ .q (reg2hw.wkup_cause[1].q),
.qs (wkup_cause_cause_1_qs)
);
@@ -20103,7 +20032,7 @@
.d (hw2reg.wkup_cause[2].d),
.qre (),
.qe (reg2hw.wkup_cause[2].qe),
- .q (reg2hw.wkup_cause[2].q ),
+ .q (reg2hw.wkup_cause[2].q),
.qs (wkup_cause_cause_2_qs)
);
@@ -20118,7 +20047,7 @@
.d (hw2reg.wkup_cause[3].d),
.qre (),
.qe (reg2hw.wkup_cause[3].qe),
- .q (reg2hw.wkup_cause[3].q ),
+ .q (reg2hw.wkup_cause[3].q),
.qs (wkup_cause_cause_3_qs)
);
@@ -20133,7 +20062,7 @@
.d (hw2reg.wkup_cause[4].d),
.qre (),
.qe (reg2hw.wkup_cause[4].qe),
- .q (reg2hw.wkup_cause[4].q ),
+ .q (reg2hw.wkup_cause[4].q),
.qs (wkup_cause_cause_4_qs)
);
@@ -20148,7 +20077,7 @@
.d (hw2reg.wkup_cause[5].d),
.qre (),
.qe (reg2hw.wkup_cause[5].qe),
- .q (reg2hw.wkup_cause[5].q ),
+ .q (reg2hw.wkup_cause[5].q),
.qs (wkup_cause_cause_5_qs)
);
@@ -20163,7 +20092,7 @@
.d (hw2reg.wkup_cause[6].d),
.qre (),
.qe (reg2hw.wkup_cause[6].qe),
- .q (reg2hw.wkup_cause[6].q ),
+ .q (reg2hw.wkup_cause[6].q),
.qs (wkup_cause_cause_6_qs)
);
@@ -20178,7 +20107,7 @@
.d (hw2reg.wkup_cause[7].d),
.qre (),
.qe (reg2hw.wkup_cause[7].qe),
- .q (reg2hw.wkup_cause[7].q ),
+ .q (reg2hw.wkup_cause[7].q),
.qs (wkup_cause_cause_7_qs)
);
diff --git a/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv
index b2f89fa..b2f20e3 100644
--- a/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv
+++ b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv
@@ -194,8 +194,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_intr_state (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_state_we),
@@ -203,11 +203,11 @@
// from internal hardware
.de (hw2reg.intr_state.de),
- .d (hw2reg.intr_state.d ),
+ .d (hw2reg.intr_state.d),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.q ),
+ .q (reg2hw.intr_state.q),
// to register interface (read)
.qs (intr_state_qs)
@@ -221,8 +221,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_intr_enable (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (intr_enable_we),
@@ -230,11 +230,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.q ),
+ .q (reg2hw.intr_enable.q),
// to register interface (read)
.qs (intr_enable_qs)
@@ -252,7 +252,7 @@
.d ('0),
.qre (),
.qe (reg2hw.intr_test.qe),
- .q (reg2hw.intr_test.q ),
+ .q (reg2hw.intr_test.q),
.qs ()
);
@@ -281,20 +281,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_low_power_hint (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_low_power_hint_we & ctrl_cfg_regwen_qs),
.wd (control_low_power_hint_wd),
// from internal hardware
.de (hw2reg.control.low_power_hint.de),
- .d (hw2reg.control.low_power_hint.d ),
+ .d (hw2reg.control.low_power_hint.d),
// to internal hardware
.qe (),
- .q (reg2hw.control.low_power_hint.q ),
+ .q (reg2hw.control.low_power_hint.q),
// to register interface (read)
.qs (control_low_power_hint_qs)
@@ -307,20 +307,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_core_clk_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_core_clk_en_we & ctrl_cfg_regwen_qs),
.wd (control_core_clk_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.core_clk_en.q ),
+ .q (reg2hw.control.core_clk_en.q),
// to register interface (read)
.qs (control_core_clk_en_qs)
@@ -333,20 +333,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_io_clk_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_io_clk_en_we & ctrl_cfg_regwen_qs),
.wd (control_io_clk_en_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.io_clk_en.q ),
+ .q (reg2hw.control.io_clk_en.q),
// to register interface (read)
.qs (control_io_clk_en_qs)
@@ -359,20 +359,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_control_usb_clk_en_lp (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_usb_clk_en_lp_we & ctrl_cfg_regwen_qs),
.wd (control_usb_clk_en_lp_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.usb_clk_en_lp.q ),
+ .q (reg2hw.control.usb_clk_en_lp.q),
// to register interface (read)
.qs (control_usb_clk_en_lp_qs)
@@ -385,20 +385,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_control_usb_clk_en_active (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_usb_clk_en_active_we & ctrl_cfg_regwen_qs),
.wd (control_usb_clk_en_active_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.usb_clk_en_active.q ),
+ .q (reg2hw.control.usb_clk_en_active.q),
// to register interface (read)
.qs (control_usb_clk_en_active_qs)
@@ -411,20 +411,20 @@
.SWACCESS("RW"),
.RESVAL (1'h1)
) u_control_main_pd_n (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (control_main_pd_n_we & ctrl_cfg_regwen_qs),
.wd (control_main_pd_n_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.control.main_pd_n.q ),
+ .q (reg2hw.control.main_pd_n.q),
// to register interface (read)
.qs (control_main_pd_n_qs)
@@ -438,8 +438,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cfg_cdc_sync (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg_cdc_sync_we),
@@ -447,11 +447,11 @@
// from internal hardware
.de (hw2reg.cfg_cdc_sync.de),
- .d (hw2reg.cfg_cdc_sync.d ),
+ .d (hw2reg.cfg_cdc_sync.d),
// to internal hardware
.qe (reg2hw.cfg_cdc_sync.qe),
- .q (reg2hw.cfg_cdc_sync.q ),
+ .q (reg2hw.cfg_cdc_sync.q),
// to register interface (read)
.qs (cfg_cdc_sync_qs)
@@ -465,8 +465,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_wakeup_en_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wakeup_en_regwen_we),
@@ -474,7 +474,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -495,20 +495,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wakeup_en_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wakeup_en_en_0_we & wakeup_en_regwen_qs),
.wd (wakeup_en_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wakeup_en[0].q ),
+ .q (reg2hw.wakeup_en[0].q),
// to register interface (read)
.qs (wakeup_en_en_0_qs)
@@ -521,20 +521,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wakeup_en_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wakeup_en_en_1_we & wakeup_en_regwen_qs),
.wd (wakeup_en_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wakeup_en[1].q ),
+ .q (reg2hw.wakeup_en[1].q),
// to register interface (read)
.qs (wakeup_en_en_1_qs)
@@ -547,20 +547,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wakeup_en_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wakeup_en_en_2_we & wakeup_en_regwen_qs),
.wd (wakeup_en_en_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wakeup_en[2].q ),
+ .q (reg2hw.wakeup_en[2].q),
// to register interface (read)
.qs (wakeup_en_en_2_qs)
@@ -573,20 +573,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wakeup_en_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wakeup_en_en_3_we & wakeup_en_regwen_qs),
.wd (wakeup_en_en_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wakeup_en[3].q ),
+ .q (reg2hw.wakeup_en[3].q),
// to register interface (read)
.qs (wakeup_en_en_3_qs)
@@ -599,20 +599,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wakeup_en_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (wakeup_en_en_4_we & wakeup_en_regwen_qs),
.wd (wakeup_en_en_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wakeup_en[4].q ),
+ .q (reg2hw.wakeup_en[4].q),
// to register interface (read)
.qs (wakeup_en_en_4_qs)
@@ -630,15 +630,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_wake_status_val_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.wake_status[0].de),
- .d (hw2reg.wake_status[0].d ),
+ .d (hw2reg.wake_status[0].d),
// to internal hardware
.qe (),
@@ -655,15 +656,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_wake_status_val_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.wake_status[1].de),
- .d (hw2reg.wake_status[1].d ),
+ .d (hw2reg.wake_status[1].d),
// to internal hardware
.qe (),
@@ -680,15 +682,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_wake_status_val_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.wake_status[2].de),
- .d (hw2reg.wake_status[2].d ),
+ .d (hw2reg.wake_status[2].d),
// to internal hardware
.qe (),
@@ -705,15 +708,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_wake_status_val_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.wake_status[3].de),
- .d (hw2reg.wake_status[3].d ),
+ .d (hw2reg.wake_status[3].d),
// to internal hardware
.qe (),
@@ -730,15 +734,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_wake_status_val_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.wake_status[4].de),
- .d (hw2reg.wake_status[4].d ),
+ .d (hw2reg.wake_status[4].d),
// to internal hardware
.qe (),
@@ -757,8 +762,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_reset_en_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_en_regwen_we),
@@ -766,7 +771,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -787,20 +792,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_reset_en_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (reset_en_en_0_we & reset_en_regwen_qs),
.wd (reset_en_en_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.reset_en[0].q ),
+ .q (reg2hw.reset_en[0].q),
// to register interface (read)
.qs (reset_en_en_0_qs)
@@ -813,20 +818,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_reset_en_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (reset_en_en_1_we & reset_en_regwen_qs),
.wd (reset_en_en_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.reset_en[1].q ),
+ .q (reg2hw.reset_en[1].q),
// to register interface (read)
.qs (reset_en_en_1_qs)
@@ -844,15 +849,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_reset_status_val_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.reset_status[0].de),
- .d (hw2reg.reset_status[0].d ),
+ .d (hw2reg.reset_status[0].d),
// to internal hardware
.qe (),
@@ -869,15 +875,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_reset_status_val_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.reset_status[1].de),
- .d (hw2reg.reset_status[1].d ),
+ .d (hw2reg.reset_status[1].d),
// to internal hardware
.qe (),
@@ -896,15 +903,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_escalate_reset_status (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.escalate_reset_status.de),
- .d (hw2reg.escalate_reset_status.d ),
+ .d (hw2reg.escalate_reset_status.d),
// to internal hardware
.qe (),
@@ -922,8 +930,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_wake_info_capture_dis (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (wake_info_capture_dis_we),
@@ -931,11 +939,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.wake_info_capture_dis.q ),
+ .q (reg2hw.wake_info_capture_dis.q),
// to register interface (read)
.qs (wake_info_capture_dis_qs)
@@ -954,7 +962,7 @@
.d (hw2reg.wake_info.reasons.d),
.qre (),
.qe (reg2hw.wake_info.reasons.qe),
- .q (reg2hw.wake_info.reasons.q ),
+ .q (reg2hw.wake_info.reasons.q),
.qs (wake_info_reasons_qs)
);
@@ -969,7 +977,7 @@
.d (hw2reg.wake_info.fall_through.d),
.qre (),
.qe (reg2hw.wake_info.fall_through.qe),
- .q (reg2hw.wake_info.fall_through.q ),
+ .q (reg2hw.wake_info.fall_through.q),
.qs (wake_info_fall_through_qs)
);
@@ -984,7 +992,7 @@
.d (hw2reg.wake_info.abort.d),
.qre (),
.qe (reg2hw.wake_info.abort.qe),
- .q (reg2hw.wake_info.abort.q ),
+ .q (reg2hw.wake_info.abort.q),
.qs (wake_info_abort_qs)
);
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
index b9ad0ef..d691154 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
@@ -201,8 +201,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h1)
) u_reset_info_por (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_info_por_we),
@@ -210,7 +210,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -227,8 +227,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_reset_info_low_power_exit (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_info_low_power_exit_we),
@@ -236,7 +236,7 @@
// from internal hardware
.de (hw2reg.reset_info.low_power_exit.de),
- .d (hw2reg.reset_info.low_power_exit.d ),
+ .d (hw2reg.reset_info.low_power_exit.d),
// to internal hardware
.qe (),
@@ -253,8 +253,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_reset_info_ndm_reset (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_info_ndm_reset_we),
@@ -262,7 +262,7 @@
// from internal hardware
.de (hw2reg.reset_info.ndm_reset.de),
- .d (hw2reg.reset_info.ndm_reset.d ),
+ .d (hw2reg.reset_info.ndm_reset.d),
// to internal hardware
.qe (),
@@ -279,8 +279,8 @@
.SWACCESS("W1C"),
.RESVAL (3'h0)
) u_reset_info_hw_req (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (reset_info_hw_req_we),
@@ -288,11 +288,11 @@
// from internal hardware
.de (hw2reg.reset_info.hw_req.de),
- .d (hw2reg.reset_info.hw_req.d ),
+ .d (hw2reg.reset_info.hw_req.d),
// to internal hardware
.qe (),
- .q (reg2hw.reset_info.hw_req.q ),
+ .q (reg2hw.reset_info.hw_req.q),
// to register interface (read)
.qs (reset_info_hw_req_qs)
@@ -306,8 +306,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_alert_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_regwen_we),
@@ -315,7 +315,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -334,20 +334,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_info_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_info_ctrl_en_we & alert_regwen_qs),
.wd (alert_info_ctrl_en_wd),
// from internal hardware
.de (hw2reg.alert_info_ctrl.en.de),
- .d (hw2reg.alert_info_ctrl.en.d ),
+ .d (hw2reg.alert_info_ctrl.en.d),
// to internal hardware
.qe (),
- .q (reg2hw.alert_info_ctrl.en.q ),
+ .q (reg2hw.alert_info_ctrl.en.q),
// to register interface (read)
.qs (alert_info_ctrl_en_qs)
@@ -360,20 +360,20 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_alert_info_ctrl_index (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (alert_info_ctrl_index_we & alert_regwen_qs),
.wd (alert_info_ctrl_index_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_info_ctrl.index.q ),
+ .q (reg2hw.alert_info_ctrl.index.q),
// to register interface (read)
.qs (alert_info_ctrl_index_qs)
@@ -419,8 +419,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_cpu_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cpu_regwen_we),
@@ -428,7 +428,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -447,20 +447,20 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_cpu_info_ctrl_en (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cpu_info_ctrl_en_we & cpu_regwen_qs),
.wd (cpu_info_ctrl_en_wd),
// from internal hardware
.de (hw2reg.cpu_info_ctrl.en.de),
- .d (hw2reg.cpu_info_ctrl.en.d ),
+ .d (hw2reg.cpu_info_ctrl.en.d),
// to internal hardware
.qe (),
- .q (reg2hw.cpu_info_ctrl.en.q ),
+ .q (reg2hw.cpu_info_ctrl.en.q),
// to register interface (read)
.qs (cpu_info_ctrl_en_qs)
@@ -473,20 +473,20 @@
.SWACCESS("RW"),
.RESVAL (4'h0)
) u_cpu_info_ctrl_index (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (cpu_info_ctrl_index_we & cpu_regwen_qs),
.wd (cpu_info_ctrl_index_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.cpu_info_ctrl.index.q ),
+ .q (reg2hw.cpu_info_ctrl.index.q),
// to register interface (read)
.qs (cpu_info_ctrl_index_qs)
@@ -535,8 +535,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_sw_rst_regen_en_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_rst_regen_en_0_we),
@@ -544,11 +544,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[0].q ),
+ .q (reg2hw.sw_rst_regen[0].q),
// to register interface (read)
.qs (sw_rst_regen_en_0_qs)
@@ -561,8 +561,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_sw_rst_regen_en_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_rst_regen_en_1_we),
@@ -570,11 +570,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[1].q ),
+ .q (reg2hw.sw_rst_regen[1].q),
// to register interface (read)
.qs (sw_rst_regen_en_1_qs)
@@ -587,8 +587,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_sw_rst_regen_en_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_rst_regen_en_2_we),
@@ -596,11 +596,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[2].q ),
+ .q (reg2hw.sw_rst_regen[2].q),
// to register interface (read)
.qs (sw_rst_regen_en_2_qs)
@@ -613,8 +613,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_sw_rst_regen_en_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_rst_regen_en_3_we),
@@ -622,11 +622,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[3].q ),
+ .q (reg2hw.sw_rst_regen[3].q),
// to register interface (read)
.qs (sw_rst_regen_en_3_qs)
@@ -639,8 +639,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_sw_rst_regen_en_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_rst_regen_en_4_we),
@@ -648,11 +648,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[4].q ),
+ .q (reg2hw.sw_rst_regen[4].q),
// to register interface (read)
.qs (sw_rst_regen_en_4_qs)
@@ -665,8 +665,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_sw_rst_regen_en_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_rst_regen_en_5_we),
@@ -674,11 +674,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[5].q ),
+ .q (reg2hw.sw_rst_regen[5].q),
// to register interface (read)
.qs (sw_rst_regen_en_5_qs)
@@ -691,8 +691,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_sw_rst_regen_en_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (sw_rst_regen_en_6_we),
@@ -700,11 +700,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.sw_rst_regen[6].q ),
+ .q (reg2hw.sw_rst_regen[6].q),
// to register interface (read)
.qs (sw_rst_regen_en_6_qs)
@@ -726,7 +726,7 @@
.d (hw2reg.sw_rst_ctrl_n[0].d),
.qre (),
.qe (reg2hw.sw_rst_ctrl_n[0].qe),
- .q (reg2hw.sw_rst_ctrl_n[0].q ),
+ .q (reg2hw.sw_rst_ctrl_n[0].q),
.qs (sw_rst_ctrl_n_val_0_qs)
);
@@ -741,7 +741,7 @@
.d (hw2reg.sw_rst_ctrl_n[1].d),
.qre (),
.qe (reg2hw.sw_rst_ctrl_n[1].qe),
- .q (reg2hw.sw_rst_ctrl_n[1].q ),
+ .q (reg2hw.sw_rst_ctrl_n[1].q),
.qs (sw_rst_ctrl_n_val_1_qs)
);
@@ -756,7 +756,7 @@
.d (hw2reg.sw_rst_ctrl_n[2].d),
.qre (),
.qe (reg2hw.sw_rst_ctrl_n[2].qe),
- .q (reg2hw.sw_rst_ctrl_n[2].q ),
+ .q (reg2hw.sw_rst_ctrl_n[2].q),
.qs (sw_rst_ctrl_n_val_2_qs)
);
@@ -771,7 +771,7 @@
.d (hw2reg.sw_rst_ctrl_n[3].d),
.qre (),
.qe (reg2hw.sw_rst_ctrl_n[3].qe),
- .q (reg2hw.sw_rst_ctrl_n[3].q ),
+ .q (reg2hw.sw_rst_ctrl_n[3].q),
.qs (sw_rst_ctrl_n_val_3_qs)
);
@@ -786,7 +786,7 @@
.d (hw2reg.sw_rst_ctrl_n[4].d),
.qre (),
.qe (reg2hw.sw_rst_ctrl_n[4].qe),
- .q (reg2hw.sw_rst_ctrl_n[4].q ),
+ .q (reg2hw.sw_rst_ctrl_n[4].q),
.qs (sw_rst_ctrl_n_val_4_qs)
);
@@ -801,7 +801,7 @@
.d (hw2reg.sw_rst_ctrl_n[5].d),
.qre (),
.qe (reg2hw.sw_rst_ctrl_n[5].qe),
- .q (reg2hw.sw_rst_ctrl_n[5].q ),
+ .q (reg2hw.sw_rst_ctrl_n[5].q),
.qs (sw_rst_ctrl_n_val_5_qs)
);
@@ -816,7 +816,7 @@
.d (hw2reg.sw_rst_ctrl_n[6].d),
.qre (),
.qe (reg2hw.sw_rst_ctrl_n[6].qe),
- .q (reg2hw.sw_rst_ctrl_n[6].q ),
+ .q (reg2hw.sw_rst_ctrl_n[6].q),
.qs (sw_rst_ctrl_n_val_6_qs)
);
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
index 55275ca..423374e 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
@@ -1926,15 +1926,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[0].de),
- .d (hw2reg.ip[0].d ),
+ .d (hw2reg.ip[0].d),
// to internal hardware
.qe (),
@@ -1951,15 +1952,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[1].de),
- .d (hw2reg.ip[1].d ),
+ .d (hw2reg.ip[1].d),
// to internal hardware
.qe (),
@@ -1976,15 +1978,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[2].de),
- .d (hw2reg.ip[2].d ),
+ .d (hw2reg.ip[2].d),
// to internal hardware
.qe (),
@@ -2001,15 +2004,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[3].de),
- .d (hw2reg.ip[3].d ),
+ .d (hw2reg.ip[3].d),
// to internal hardware
.qe (),
@@ -2026,15 +2030,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[4].de),
- .d (hw2reg.ip[4].d ),
+ .d (hw2reg.ip[4].d),
// to internal hardware
.qe (),
@@ -2051,15 +2056,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[5].de),
- .d (hw2reg.ip[5].d ),
+ .d (hw2reg.ip[5].d),
// to internal hardware
.qe (),
@@ -2076,15 +2082,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[6].de),
- .d (hw2reg.ip[6].d ),
+ .d (hw2reg.ip[6].d),
// to internal hardware
.qe (),
@@ -2101,15 +2108,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[7].de),
- .d (hw2reg.ip[7].d ),
+ .d (hw2reg.ip[7].d),
// to internal hardware
.qe (),
@@ -2126,15 +2134,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[8].de),
- .d (hw2reg.ip[8].d ),
+ .d (hw2reg.ip[8].d),
// to internal hardware
.qe (),
@@ -2151,15 +2160,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[9].de),
- .d (hw2reg.ip[9].d ),
+ .d (hw2reg.ip[9].d),
// to internal hardware
.qe (),
@@ -2176,15 +2186,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[10].de),
- .d (hw2reg.ip[10].d ),
+ .d (hw2reg.ip[10].d),
// to internal hardware
.qe (),
@@ -2201,15 +2212,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[11].de),
- .d (hw2reg.ip[11].d ),
+ .d (hw2reg.ip[11].d),
// to internal hardware
.qe (),
@@ -2226,15 +2238,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[12].de),
- .d (hw2reg.ip[12].d ),
+ .d (hw2reg.ip[12].d),
// to internal hardware
.qe (),
@@ -2251,15 +2264,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[13].de),
- .d (hw2reg.ip[13].d ),
+ .d (hw2reg.ip[13].d),
// to internal hardware
.qe (),
@@ -2276,15 +2290,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[14].de),
- .d (hw2reg.ip[14].d ),
+ .d (hw2reg.ip[14].d),
// to internal hardware
.qe (),
@@ -2301,15 +2316,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[15].de),
- .d (hw2reg.ip[15].d ),
+ .d (hw2reg.ip[15].d),
// to internal hardware
.qe (),
@@ -2326,15 +2342,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[16].de),
- .d (hw2reg.ip[16].d ),
+ .d (hw2reg.ip[16].d),
// to internal hardware
.qe (),
@@ -2351,15 +2368,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[17].de),
- .d (hw2reg.ip[17].d ),
+ .d (hw2reg.ip[17].d),
// to internal hardware
.qe (),
@@ -2376,15 +2394,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[18].de),
- .d (hw2reg.ip[18].d ),
+ .d (hw2reg.ip[18].d),
// to internal hardware
.qe (),
@@ -2401,15 +2420,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[19].de),
- .d (hw2reg.ip[19].d ),
+ .d (hw2reg.ip[19].d),
// to internal hardware
.qe (),
@@ -2426,15 +2446,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[20].de),
- .d (hw2reg.ip[20].d ),
+ .d (hw2reg.ip[20].d),
// to internal hardware
.qe (),
@@ -2451,15 +2472,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[21].de),
- .d (hw2reg.ip[21].d ),
+ .d (hw2reg.ip[21].d),
// to internal hardware
.qe (),
@@ -2476,15 +2498,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[22].de),
- .d (hw2reg.ip[22].d ),
+ .d (hw2reg.ip[22].d),
// to internal hardware
.qe (),
@@ -2501,15 +2524,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[23].de),
- .d (hw2reg.ip[23].d ),
+ .d (hw2reg.ip[23].d),
// to internal hardware
.qe (),
@@ -2526,15 +2550,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[24].de),
- .d (hw2reg.ip[24].d ),
+ .d (hw2reg.ip[24].d),
// to internal hardware
.qe (),
@@ -2551,15 +2576,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[25].de),
- .d (hw2reg.ip[25].d ),
+ .d (hw2reg.ip[25].d),
// to internal hardware
.qe (),
@@ -2576,15 +2602,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[26].de),
- .d (hw2reg.ip[26].d ),
+ .d (hw2reg.ip[26].d),
// to internal hardware
.qe (),
@@ -2601,15 +2628,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[27].de),
- .d (hw2reg.ip[27].d ),
+ .d (hw2reg.ip[27].d),
// to internal hardware
.qe (),
@@ -2626,15 +2654,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[28].de),
- .d (hw2reg.ip[28].d ),
+ .d (hw2reg.ip[28].d),
// to internal hardware
.qe (),
@@ -2651,15 +2680,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[29].de),
- .d (hw2reg.ip[29].d ),
+ .d (hw2reg.ip[29].d),
// to internal hardware
.qe (),
@@ -2676,15 +2706,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[30].de),
- .d (hw2reg.ip[30].d ),
+ .d (hw2reg.ip[30].d),
// to internal hardware
.qe (),
@@ -2701,15 +2732,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_0_p_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[31].de),
- .d (hw2reg.ip[31].d ),
+ .d (hw2reg.ip[31].d),
// to internal hardware
.qe (),
@@ -2729,15 +2761,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[32].de),
- .d (hw2reg.ip[32].d ),
+ .d (hw2reg.ip[32].d),
// to internal hardware
.qe (),
@@ -2754,15 +2787,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[33].de),
- .d (hw2reg.ip[33].d ),
+ .d (hw2reg.ip[33].d),
// to internal hardware
.qe (),
@@ -2779,15 +2813,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[34].de),
- .d (hw2reg.ip[34].d ),
+ .d (hw2reg.ip[34].d),
// to internal hardware
.qe (),
@@ -2804,15 +2839,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[35].de),
- .d (hw2reg.ip[35].d ),
+ .d (hw2reg.ip[35].d),
// to internal hardware
.qe (),
@@ -2829,15 +2865,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[36].de),
- .d (hw2reg.ip[36].d ),
+ .d (hw2reg.ip[36].d),
// to internal hardware
.qe (),
@@ -2854,15 +2891,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[37].de),
- .d (hw2reg.ip[37].d ),
+ .d (hw2reg.ip[37].d),
// to internal hardware
.qe (),
@@ -2879,15 +2917,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[38].de),
- .d (hw2reg.ip[38].d ),
+ .d (hw2reg.ip[38].d),
// to internal hardware
.qe (),
@@ -2904,15 +2943,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[39].de),
- .d (hw2reg.ip[39].d ),
+ .d (hw2reg.ip[39].d),
// to internal hardware
.qe (),
@@ -2929,15 +2969,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[40].de),
- .d (hw2reg.ip[40].d ),
+ .d (hw2reg.ip[40].d),
// to internal hardware
.qe (),
@@ -2954,15 +2995,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[41].de),
- .d (hw2reg.ip[41].d ),
+ .d (hw2reg.ip[41].d),
// to internal hardware
.qe (),
@@ -2979,15 +3021,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[42].de),
- .d (hw2reg.ip[42].d ),
+ .d (hw2reg.ip[42].d),
// to internal hardware
.qe (),
@@ -3004,15 +3047,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[43].de),
- .d (hw2reg.ip[43].d ),
+ .d (hw2reg.ip[43].d),
// to internal hardware
.qe (),
@@ -3029,15 +3073,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[44].de),
- .d (hw2reg.ip[44].d ),
+ .d (hw2reg.ip[44].d),
// to internal hardware
.qe (),
@@ -3054,15 +3099,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[45].de),
- .d (hw2reg.ip[45].d ),
+ .d (hw2reg.ip[45].d),
// to internal hardware
.qe (),
@@ -3079,15 +3125,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[46].de),
- .d (hw2reg.ip[46].d ),
+ .d (hw2reg.ip[46].d),
// to internal hardware
.qe (),
@@ -3104,15 +3151,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_47 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[47].de),
- .d (hw2reg.ip[47].d ),
+ .d (hw2reg.ip[47].d),
// to internal hardware
.qe (),
@@ -3129,15 +3177,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_48 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[48].de),
- .d (hw2reg.ip[48].d ),
+ .d (hw2reg.ip[48].d),
// to internal hardware
.qe (),
@@ -3154,15 +3203,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_49 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[49].de),
- .d (hw2reg.ip[49].d ),
+ .d (hw2reg.ip[49].d),
// to internal hardware
.qe (),
@@ -3179,15 +3229,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_50 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[50].de),
- .d (hw2reg.ip[50].d ),
+ .d (hw2reg.ip[50].d),
// to internal hardware
.qe (),
@@ -3204,15 +3255,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_51 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[51].de),
- .d (hw2reg.ip[51].d ),
+ .d (hw2reg.ip[51].d),
// to internal hardware
.qe (),
@@ -3229,15 +3281,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[52].de),
- .d (hw2reg.ip[52].d ),
+ .d (hw2reg.ip[52].d),
// to internal hardware
.qe (),
@@ -3254,15 +3307,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[53].de),
- .d (hw2reg.ip[53].d ),
+ .d (hw2reg.ip[53].d),
// to internal hardware
.qe (),
@@ -3279,15 +3333,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_54 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[54].de),
- .d (hw2reg.ip[54].d ),
+ .d (hw2reg.ip[54].d),
// to internal hardware
.qe (),
@@ -3304,15 +3359,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_55 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[55].de),
- .d (hw2reg.ip[55].d ),
+ .d (hw2reg.ip[55].d),
// to internal hardware
.qe (),
@@ -3329,15 +3385,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_56 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[56].de),
- .d (hw2reg.ip[56].d ),
+ .d (hw2reg.ip[56].d),
// to internal hardware
.qe (),
@@ -3354,15 +3411,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_57 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[57].de),
- .d (hw2reg.ip[57].d ),
+ .d (hw2reg.ip[57].d),
// to internal hardware
.qe (),
@@ -3379,15 +3437,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_58 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[58].de),
- .d (hw2reg.ip[58].d ),
+ .d (hw2reg.ip[58].d),
// to internal hardware
.qe (),
@@ -3404,15 +3463,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_59 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[59].de),
- .d (hw2reg.ip[59].d ),
+ .d (hw2reg.ip[59].d),
// to internal hardware
.qe (),
@@ -3429,15 +3489,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_60 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[60].de),
- .d (hw2reg.ip[60].d ),
+ .d (hw2reg.ip[60].d),
// to internal hardware
.qe (),
@@ -3454,15 +3515,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_61 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[61].de),
- .d (hw2reg.ip[61].d ),
+ .d (hw2reg.ip[61].d),
// to internal hardware
.qe (),
@@ -3479,15 +3541,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_62 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[62].de),
- .d (hw2reg.ip[62].d ),
+ .d (hw2reg.ip[62].d),
// to internal hardware
.qe (),
@@ -3504,15 +3567,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_1_p_63 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[63].de),
- .d (hw2reg.ip[63].d ),
+ .d (hw2reg.ip[63].d),
// to internal hardware
.qe (),
@@ -3532,15 +3596,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_64 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[64].de),
- .d (hw2reg.ip[64].d ),
+ .d (hw2reg.ip[64].d),
// to internal hardware
.qe (),
@@ -3557,15 +3622,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_65 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[65].de),
- .d (hw2reg.ip[65].d ),
+ .d (hw2reg.ip[65].d),
// to internal hardware
.qe (),
@@ -3582,15 +3648,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_66 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[66].de),
- .d (hw2reg.ip[66].d ),
+ .d (hw2reg.ip[66].d),
// to internal hardware
.qe (),
@@ -3607,15 +3674,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_67 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[67].de),
- .d (hw2reg.ip[67].d ),
+ .d (hw2reg.ip[67].d),
// to internal hardware
.qe (),
@@ -3632,15 +3700,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_68 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[68].de),
- .d (hw2reg.ip[68].d ),
+ .d (hw2reg.ip[68].d),
// to internal hardware
.qe (),
@@ -3657,15 +3726,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_69 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[69].de),
- .d (hw2reg.ip[69].d ),
+ .d (hw2reg.ip[69].d),
// to internal hardware
.qe (),
@@ -3682,15 +3752,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_70 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[70].de),
- .d (hw2reg.ip[70].d ),
+ .d (hw2reg.ip[70].d),
// to internal hardware
.qe (),
@@ -3707,15 +3778,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_71 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[71].de),
- .d (hw2reg.ip[71].d ),
+ .d (hw2reg.ip[71].d),
// to internal hardware
.qe (),
@@ -3732,15 +3804,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_72 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[72].de),
- .d (hw2reg.ip[72].d ),
+ .d (hw2reg.ip[72].d),
// to internal hardware
.qe (),
@@ -3757,15 +3830,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_73 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[73].de),
- .d (hw2reg.ip[73].d ),
+ .d (hw2reg.ip[73].d),
// to internal hardware
.qe (),
@@ -3782,15 +3856,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_74 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[74].de),
- .d (hw2reg.ip[74].d ),
+ .d (hw2reg.ip[74].d),
// to internal hardware
.qe (),
@@ -3807,15 +3882,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_75 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[75].de),
- .d (hw2reg.ip[75].d ),
+ .d (hw2reg.ip[75].d),
// to internal hardware
.qe (),
@@ -3832,15 +3908,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_76 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[76].de),
- .d (hw2reg.ip[76].d ),
+ .d (hw2reg.ip[76].d),
// to internal hardware
.qe (),
@@ -3857,15 +3934,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_77 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[77].de),
- .d (hw2reg.ip[77].d ),
+ .d (hw2reg.ip[77].d),
// to internal hardware
.qe (),
@@ -3882,15 +3960,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_78 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[78].de),
- .d (hw2reg.ip[78].d ),
+ .d (hw2reg.ip[78].d),
// to internal hardware
.qe (),
@@ -3907,15 +3986,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_79 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[79].de),
- .d (hw2reg.ip[79].d ),
+ .d (hw2reg.ip[79].d),
// to internal hardware
.qe (),
@@ -3932,15 +4012,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_80 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[80].de),
- .d (hw2reg.ip[80].d ),
+ .d (hw2reg.ip[80].d),
// to internal hardware
.qe (),
@@ -3957,15 +4038,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_81 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[81].de),
- .d (hw2reg.ip[81].d ),
+ .d (hw2reg.ip[81].d),
// to internal hardware
.qe (),
@@ -3982,15 +4064,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_82 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[82].de),
- .d (hw2reg.ip[82].d ),
+ .d (hw2reg.ip[82].d),
// to internal hardware
.qe (),
@@ -4007,15 +4090,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_83 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[83].de),
- .d (hw2reg.ip[83].d ),
+ .d (hw2reg.ip[83].d),
// to internal hardware
.qe (),
@@ -4032,15 +4116,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_84 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[84].de),
- .d (hw2reg.ip[84].d ),
+ .d (hw2reg.ip[84].d),
// to internal hardware
.qe (),
@@ -4057,15 +4142,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_85 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[85].de),
- .d (hw2reg.ip[85].d ),
+ .d (hw2reg.ip[85].d),
// to internal hardware
.qe (),
@@ -4082,15 +4168,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_86 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[86].de),
- .d (hw2reg.ip[86].d ),
+ .d (hw2reg.ip[86].d),
// to internal hardware
.qe (),
@@ -4107,15 +4194,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_87 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[87].de),
- .d (hw2reg.ip[87].d ),
+ .d (hw2reg.ip[87].d),
// to internal hardware
.qe (),
@@ -4132,15 +4220,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_88 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[88].de),
- .d (hw2reg.ip[88].d ),
+ .d (hw2reg.ip[88].d),
// to internal hardware
.qe (),
@@ -4157,15 +4246,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_89 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[89].de),
- .d (hw2reg.ip[89].d ),
+ .d (hw2reg.ip[89].d),
// to internal hardware
.qe (),
@@ -4182,15 +4272,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_90 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[90].de),
- .d (hw2reg.ip[90].d ),
+ .d (hw2reg.ip[90].d),
// to internal hardware
.qe (),
@@ -4207,15 +4298,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_91 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[91].de),
- .d (hw2reg.ip[91].d ),
+ .d (hw2reg.ip[91].d),
// to internal hardware
.qe (),
@@ -4232,15 +4324,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_92 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[92].de),
- .d (hw2reg.ip[92].d ),
+ .d (hw2reg.ip[92].d),
// to internal hardware
.qe (),
@@ -4257,15 +4350,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_93 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[93].de),
- .d (hw2reg.ip[93].d ),
+ .d (hw2reg.ip[93].d),
// to internal hardware
.qe (),
@@ -4282,15 +4376,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_94 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[94].de),
- .d (hw2reg.ip[94].d ),
+ .d (hw2reg.ip[94].d),
// to internal hardware
.qe (),
@@ -4307,15 +4402,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_2_p_95 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[95].de),
- .d (hw2reg.ip[95].d ),
+ .d (hw2reg.ip[95].d),
// to internal hardware
.qe (),
@@ -4335,15 +4431,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_96 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[96].de),
- .d (hw2reg.ip[96].d ),
+ .d (hw2reg.ip[96].d),
// to internal hardware
.qe (),
@@ -4360,15 +4457,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_97 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[97].de),
- .d (hw2reg.ip[97].d ),
+ .d (hw2reg.ip[97].d),
// to internal hardware
.qe (),
@@ -4385,15 +4483,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_98 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[98].de),
- .d (hw2reg.ip[98].d ),
+ .d (hw2reg.ip[98].d),
// to internal hardware
.qe (),
@@ -4410,15 +4509,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_99 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[99].de),
- .d (hw2reg.ip[99].d ),
+ .d (hw2reg.ip[99].d),
// to internal hardware
.qe (),
@@ -4435,15 +4535,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_100 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[100].de),
- .d (hw2reg.ip[100].d ),
+ .d (hw2reg.ip[100].d),
// to internal hardware
.qe (),
@@ -4460,15 +4561,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_101 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[101].de),
- .d (hw2reg.ip[101].d ),
+ .d (hw2reg.ip[101].d),
// to internal hardware
.qe (),
@@ -4485,15 +4587,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_102 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[102].de),
- .d (hw2reg.ip[102].d ),
+ .d (hw2reg.ip[102].d),
// to internal hardware
.qe (),
@@ -4510,15 +4613,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_103 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[103].de),
- .d (hw2reg.ip[103].d ),
+ .d (hw2reg.ip[103].d),
// to internal hardware
.qe (),
@@ -4535,15 +4639,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_104 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[104].de),
- .d (hw2reg.ip[104].d ),
+ .d (hw2reg.ip[104].d),
// to internal hardware
.qe (),
@@ -4560,15 +4665,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_105 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[105].de),
- .d (hw2reg.ip[105].d ),
+ .d (hw2reg.ip[105].d),
// to internal hardware
.qe (),
@@ -4585,15 +4691,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_106 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[106].de),
- .d (hw2reg.ip[106].d ),
+ .d (hw2reg.ip[106].d),
// to internal hardware
.qe (),
@@ -4610,15 +4717,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_107 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[107].de),
- .d (hw2reg.ip[107].d ),
+ .d (hw2reg.ip[107].d),
// to internal hardware
.qe (),
@@ -4635,15 +4743,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_108 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[108].de),
- .d (hw2reg.ip[108].d ),
+ .d (hw2reg.ip[108].d),
// to internal hardware
.qe (),
@@ -4660,15 +4769,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_109 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[109].de),
- .d (hw2reg.ip[109].d ),
+ .d (hw2reg.ip[109].d),
// to internal hardware
.qe (),
@@ -4685,15 +4795,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_110 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[110].de),
- .d (hw2reg.ip[110].d ),
+ .d (hw2reg.ip[110].d),
// to internal hardware
.qe (),
@@ -4710,15 +4821,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_111 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[111].de),
- .d (hw2reg.ip[111].d ),
+ .d (hw2reg.ip[111].d),
// to internal hardware
.qe (),
@@ -4735,15 +4847,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_112 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[112].de),
- .d (hw2reg.ip[112].d ),
+ .d (hw2reg.ip[112].d),
// to internal hardware
.qe (),
@@ -4760,15 +4873,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_113 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[113].de),
- .d (hw2reg.ip[113].d ),
+ .d (hw2reg.ip[113].d),
// to internal hardware
.qe (),
@@ -4785,15 +4899,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_114 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[114].de),
- .d (hw2reg.ip[114].d ),
+ .d (hw2reg.ip[114].d),
// to internal hardware
.qe (),
@@ -4810,15 +4925,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_115 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[115].de),
- .d (hw2reg.ip[115].d ),
+ .d (hw2reg.ip[115].d),
// to internal hardware
.qe (),
@@ -4835,15 +4951,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_116 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[116].de),
- .d (hw2reg.ip[116].d ),
+ .d (hw2reg.ip[116].d),
// to internal hardware
.qe (),
@@ -4860,15 +4977,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_117 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[117].de),
- .d (hw2reg.ip[117].d ),
+ .d (hw2reg.ip[117].d),
// to internal hardware
.qe (),
@@ -4885,15 +5003,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_118 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[118].de),
- .d (hw2reg.ip[118].d ),
+ .d (hw2reg.ip[118].d),
// to internal hardware
.qe (),
@@ -4910,15 +5029,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_119 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[119].de),
- .d (hw2reg.ip[119].d ),
+ .d (hw2reg.ip[119].d),
// to internal hardware
.qe (),
@@ -4935,15 +5055,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_120 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[120].de),
- .d (hw2reg.ip[120].d ),
+ .d (hw2reg.ip[120].d),
// to internal hardware
.qe (),
@@ -4960,15 +5081,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_121 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[121].de),
- .d (hw2reg.ip[121].d ),
+ .d (hw2reg.ip[121].d),
// to internal hardware
.qe (),
@@ -4985,15 +5107,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_122 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[122].de),
- .d (hw2reg.ip[122].d ),
+ .d (hw2reg.ip[122].d),
// to internal hardware
.qe (),
@@ -5010,15 +5133,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_123 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[123].de),
- .d (hw2reg.ip[123].d ),
+ .d (hw2reg.ip[123].d),
// to internal hardware
.qe (),
@@ -5035,15 +5159,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_124 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[124].de),
- .d (hw2reg.ip[124].d ),
+ .d (hw2reg.ip[124].d),
// to internal hardware
.qe (),
@@ -5060,15 +5185,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_125 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[125].de),
- .d (hw2reg.ip[125].d ),
+ .d (hw2reg.ip[125].d),
// to internal hardware
.qe (),
@@ -5085,15 +5211,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_126 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[126].de),
- .d (hw2reg.ip[126].d ),
+ .d (hw2reg.ip[126].d),
// to internal hardware
.qe (),
@@ -5110,15 +5237,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_3_p_127 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[127].de),
- .d (hw2reg.ip[127].d ),
+ .d (hw2reg.ip[127].d),
// to internal hardware
.qe (),
@@ -5138,15 +5266,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_128 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[128].de),
- .d (hw2reg.ip[128].d ),
+ .d (hw2reg.ip[128].d),
// to internal hardware
.qe (),
@@ -5163,15 +5292,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_129 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[129].de),
- .d (hw2reg.ip[129].d ),
+ .d (hw2reg.ip[129].d),
// to internal hardware
.qe (),
@@ -5188,15 +5318,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_130 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[130].de),
- .d (hw2reg.ip[130].d ),
+ .d (hw2reg.ip[130].d),
// to internal hardware
.qe (),
@@ -5213,15 +5344,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_131 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[131].de),
- .d (hw2reg.ip[131].d ),
+ .d (hw2reg.ip[131].d),
// to internal hardware
.qe (),
@@ -5238,15 +5370,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_132 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[132].de),
- .d (hw2reg.ip[132].d ),
+ .d (hw2reg.ip[132].d),
// to internal hardware
.qe (),
@@ -5263,15 +5396,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_133 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[133].de),
- .d (hw2reg.ip[133].d ),
+ .d (hw2reg.ip[133].d),
// to internal hardware
.qe (),
@@ -5288,15 +5422,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_134 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[134].de),
- .d (hw2reg.ip[134].d ),
+ .d (hw2reg.ip[134].d),
// to internal hardware
.qe (),
@@ -5313,15 +5448,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_135 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[135].de),
- .d (hw2reg.ip[135].d ),
+ .d (hw2reg.ip[135].d),
// to internal hardware
.qe (),
@@ -5338,15 +5474,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_136 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[136].de),
- .d (hw2reg.ip[136].d ),
+ .d (hw2reg.ip[136].d),
// to internal hardware
.qe (),
@@ -5363,15 +5500,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_137 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[137].de),
- .d (hw2reg.ip[137].d ),
+ .d (hw2reg.ip[137].d),
// to internal hardware
.qe (),
@@ -5388,15 +5526,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_138 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[138].de),
- .d (hw2reg.ip[138].d ),
+ .d (hw2reg.ip[138].d),
// to internal hardware
.qe (),
@@ -5413,15 +5552,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_139 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[139].de),
- .d (hw2reg.ip[139].d ),
+ .d (hw2reg.ip[139].d),
// to internal hardware
.qe (),
@@ -5438,15 +5578,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_140 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[140].de),
- .d (hw2reg.ip[140].d ),
+ .d (hw2reg.ip[140].d),
// to internal hardware
.qe (),
@@ -5463,15 +5604,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_141 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[141].de),
- .d (hw2reg.ip[141].d ),
+ .d (hw2reg.ip[141].d),
// to internal hardware
.qe (),
@@ -5488,15 +5630,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_142 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[142].de),
- .d (hw2reg.ip[142].d ),
+ .d (hw2reg.ip[142].d),
// to internal hardware
.qe (),
@@ -5513,15 +5656,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_143 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[143].de),
- .d (hw2reg.ip[143].d ),
+ .d (hw2reg.ip[143].d),
// to internal hardware
.qe (),
@@ -5538,15 +5682,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_144 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[144].de),
- .d (hw2reg.ip[144].d ),
+ .d (hw2reg.ip[144].d),
// to internal hardware
.qe (),
@@ -5563,15 +5708,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_145 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[145].de),
- .d (hw2reg.ip[145].d ),
+ .d (hw2reg.ip[145].d),
// to internal hardware
.qe (),
@@ -5588,15 +5734,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_146 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[146].de),
- .d (hw2reg.ip[146].d ),
+ .d (hw2reg.ip[146].d),
// to internal hardware
.qe (),
@@ -5613,15 +5760,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_147 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[147].de),
- .d (hw2reg.ip[147].d ),
+ .d (hw2reg.ip[147].d),
// to internal hardware
.qe (),
@@ -5638,15 +5786,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_148 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[148].de),
- .d (hw2reg.ip[148].d ),
+ .d (hw2reg.ip[148].d),
// to internal hardware
.qe (),
@@ -5663,15 +5812,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_149 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[149].de),
- .d (hw2reg.ip[149].d ),
+ .d (hw2reg.ip[149].d),
// to internal hardware
.qe (),
@@ -5688,15 +5838,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_150 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[150].de),
- .d (hw2reg.ip[150].d ),
+ .d (hw2reg.ip[150].d),
// to internal hardware
.qe (),
@@ -5713,15 +5864,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_151 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[151].de),
- .d (hw2reg.ip[151].d ),
+ .d (hw2reg.ip[151].d),
// to internal hardware
.qe (),
@@ -5738,15 +5890,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_152 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[152].de),
- .d (hw2reg.ip[152].d ),
+ .d (hw2reg.ip[152].d),
// to internal hardware
.qe (),
@@ -5763,15 +5916,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_153 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[153].de),
- .d (hw2reg.ip[153].d ),
+ .d (hw2reg.ip[153].d),
// to internal hardware
.qe (),
@@ -5788,15 +5942,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_154 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[154].de),
- .d (hw2reg.ip[154].d ),
+ .d (hw2reg.ip[154].d),
// to internal hardware
.qe (),
@@ -5813,15 +5968,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_155 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[155].de),
- .d (hw2reg.ip[155].d ),
+ .d (hw2reg.ip[155].d),
// to internal hardware
.qe (),
@@ -5838,15 +5994,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_156 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[156].de),
- .d (hw2reg.ip[156].d ),
+ .d (hw2reg.ip[156].d),
// to internal hardware
.qe (),
@@ -5863,15 +6020,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_157 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[157].de),
- .d (hw2reg.ip[157].d ),
+ .d (hw2reg.ip[157].d),
// to internal hardware
.qe (),
@@ -5888,15 +6046,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_158 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[158].de),
- .d (hw2reg.ip[158].d ),
+ .d (hw2reg.ip[158].d),
// to internal hardware
.qe (),
@@ -5913,15 +6072,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_4_p_159 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[159].de),
- .d (hw2reg.ip[159].d ),
+ .d (hw2reg.ip[159].d),
// to internal hardware
.qe (),
@@ -5941,15 +6101,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_160 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[160].de),
- .d (hw2reg.ip[160].d ),
+ .d (hw2reg.ip[160].d),
// to internal hardware
.qe (),
@@ -5966,15 +6127,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_161 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[161].de),
- .d (hw2reg.ip[161].d ),
+ .d (hw2reg.ip[161].d),
// to internal hardware
.qe (),
@@ -5991,15 +6153,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_162 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[162].de),
- .d (hw2reg.ip[162].d ),
+ .d (hw2reg.ip[162].d),
// to internal hardware
.qe (),
@@ -6016,15 +6179,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_163 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[163].de),
- .d (hw2reg.ip[163].d ),
+ .d (hw2reg.ip[163].d),
// to internal hardware
.qe (),
@@ -6041,15 +6205,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_164 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[164].de),
- .d (hw2reg.ip[164].d ),
+ .d (hw2reg.ip[164].d),
// to internal hardware
.qe (),
@@ -6066,15 +6231,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_165 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[165].de),
- .d (hw2reg.ip[165].d ),
+ .d (hw2reg.ip[165].d),
// to internal hardware
.qe (),
@@ -6091,15 +6257,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_166 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[166].de),
- .d (hw2reg.ip[166].d ),
+ .d (hw2reg.ip[166].d),
// to internal hardware
.qe (),
@@ -6116,15 +6283,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_167 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[167].de),
- .d (hw2reg.ip[167].d ),
+ .d (hw2reg.ip[167].d),
// to internal hardware
.qe (),
@@ -6141,15 +6309,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_168 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[168].de),
- .d (hw2reg.ip[168].d ),
+ .d (hw2reg.ip[168].d),
// to internal hardware
.qe (),
@@ -6166,15 +6335,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_169 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[169].de),
- .d (hw2reg.ip[169].d ),
+ .d (hw2reg.ip[169].d),
// to internal hardware
.qe (),
@@ -6191,15 +6361,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_170 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[170].de),
- .d (hw2reg.ip[170].d ),
+ .d (hw2reg.ip[170].d),
// to internal hardware
.qe (),
@@ -6216,15 +6387,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_171 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[171].de),
- .d (hw2reg.ip[171].d ),
+ .d (hw2reg.ip[171].d),
// to internal hardware
.qe (),
@@ -6241,15 +6413,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_172 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[172].de),
- .d (hw2reg.ip[172].d ),
+ .d (hw2reg.ip[172].d),
// to internal hardware
.qe (),
@@ -6266,15 +6439,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_173 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[173].de),
- .d (hw2reg.ip[173].d ),
+ .d (hw2reg.ip[173].d),
// to internal hardware
.qe (),
@@ -6291,15 +6465,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_174 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[174].de),
- .d (hw2reg.ip[174].d ),
+ .d (hw2reg.ip[174].d),
// to internal hardware
.qe (),
@@ -6316,15 +6491,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_175 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[175].de),
- .d (hw2reg.ip[175].d ),
+ .d (hw2reg.ip[175].d),
// to internal hardware
.qe (),
@@ -6341,15 +6517,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_176 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[176].de),
- .d (hw2reg.ip[176].d ),
+ .d (hw2reg.ip[176].d),
// to internal hardware
.qe (),
@@ -6366,15 +6543,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_177 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[177].de),
- .d (hw2reg.ip[177].d ),
+ .d (hw2reg.ip[177].d),
// to internal hardware
.qe (),
@@ -6391,15 +6569,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_178 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[178].de),
- .d (hw2reg.ip[178].d ),
+ .d (hw2reg.ip[178].d),
// to internal hardware
.qe (),
@@ -6416,15 +6595,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_ip_5_p_179 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.ip[179].de),
- .d (hw2reg.ip[179].d ),
+ .d (hw2reg.ip[179].d),
// to internal hardware
.qe (),
@@ -6446,8 +6626,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_0_we),
@@ -6455,11 +6635,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[0].q ),
+ .q (reg2hw.le[0].q),
// to register interface (read)
.qs (le_0_le_0_qs)
@@ -6472,8 +6652,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_1_we),
@@ -6481,11 +6661,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[1].q ),
+ .q (reg2hw.le[1].q),
// to register interface (read)
.qs (le_0_le_1_qs)
@@ -6498,8 +6678,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_2_we),
@@ -6507,11 +6687,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[2].q ),
+ .q (reg2hw.le[2].q),
// to register interface (read)
.qs (le_0_le_2_qs)
@@ -6524,8 +6704,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_3_we),
@@ -6533,11 +6713,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[3].q ),
+ .q (reg2hw.le[3].q),
// to register interface (read)
.qs (le_0_le_3_qs)
@@ -6550,8 +6730,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_4_we),
@@ -6559,11 +6739,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[4].q ),
+ .q (reg2hw.le[4].q),
// to register interface (read)
.qs (le_0_le_4_qs)
@@ -6576,8 +6756,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_5_we),
@@ -6585,11 +6765,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[5].q ),
+ .q (reg2hw.le[5].q),
// to register interface (read)
.qs (le_0_le_5_qs)
@@ -6602,8 +6782,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_6_we),
@@ -6611,11 +6791,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[6].q ),
+ .q (reg2hw.le[6].q),
// to register interface (read)
.qs (le_0_le_6_qs)
@@ -6628,8 +6808,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_7_we),
@@ -6637,11 +6817,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[7].q ),
+ .q (reg2hw.le[7].q),
// to register interface (read)
.qs (le_0_le_7_qs)
@@ -6654,8 +6834,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_8_we),
@@ -6663,11 +6843,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[8].q ),
+ .q (reg2hw.le[8].q),
// to register interface (read)
.qs (le_0_le_8_qs)
@@ -6680,8 +6860,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_9_we),
@@ -6689,11 +6869,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[9].q ),
+ .q (reg2hw.le[9].q),
// to register interface (read)
.qs (le_0_le_9_qs)
@@ -6706,8 +6886,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_10_we),
@@ -6715,11 +6895,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[10].q ),
+ .q (reg2hw.le[10].q),
// to register interface (read)
.qs (le_0_le_10_qs)
@@ -6732,8 +6912,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_11_we),
@@ -6741,11 +6921,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[11].q ),
+ .q (reg2hw.le[11].q),
// to register interface (read)
.qs (le_0_le_11_qs)
@@ -6758,8 +6938,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_12_we),
@@ -6767,11 +6947,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[12].q ),
+ .q (reg2hw.le[12].q),
// to register interface (read)
.qs (le_0_le_12_qs)
@@ -6784,8 +6964,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_13_we),
@@ -6793,11 +6973,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[13].q ),
+ .q (reg2hw.le[13].q),
// to register interface (read)
.qs (le_0_le_13_qs)
@@ -6810,8 +6990,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_14_we),
@@ -6819,11 +6999,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[14].q ),
+ .q (reg2hw.le[14].q),
// to register interface (read)
.qs (le_0_le_14_qs)
@@ -6836,8 +7016,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_15_we),
@@ -6845,11 +7025,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[15].q ),
+ .q (reg2hw.le[15].q),
// to register interface (read)
.qs (le_0_le_15_qs)
@@ -6862,8 +7042,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_16_we),
@@ -6871,11 +7051,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[16].q ),
+ .q (reg2hw.le[16].q),
// to register interface (read)
.qs (le_0_le_16_qs)
@@ -6888,8 +7068,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_17_we),
@@ -6897,11 +7077,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[17].q ),
+ .q (reg2hw.le[17].q),
// to register interface (read)
.qs (le_0_le_17_qs)
@@ -6914,8 +7094,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_18_we),
@@ -6923,11 +7103,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[18].q ),
+ .q (reg2hw.le[18].q),
// to register interface (read)
.qs (le_0_le_18_qs)
@@ -6940,8 +7120,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_19_we),
@@ -6949,11 +7129,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[19].q ),
+ .q (reg2hw.le[19].q),
// to register interface (read)
.qs (le_0_le_19_qs)
@@ -6966,8 +7146,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_20_we),
@@ -6975,11 +7155,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[20].q ),
+ .q (reg2hw.le[20].q),
// to register interface (read)
.qs (le_0_le_20_qs)
@@ -6992,8 +7172,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_21_we),
@@ -7001,11 +7181,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[21].q ),
+ .q (reg2hw.le[21].q),
// to register interface (read)
.qs (le_0_le_21_qs)
@@ -7018,8 +7198,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_22_we),
@@ -7027,11 +7207,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[22].q ),
+ .q (reg2hw.le[22].q),
// to register interface (read)
.qs (le_0_le_22_qs)
@@ -7044,8 +7224,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_23_we),
@@ -7053,11 +7233,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[23].q ),
+ .q (reg2hw.le[23].q),
// to register interface (read)
.qs (le_0_le_23_qs)
@@ -7070,8 +7250,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_24_we),
@@ -7079,11 +7259,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[24].q ),
+ .q (reg2hw.le[24].q),
// to register interface (read)
.qs (le_0_le_24_qs)
@@ -7096,8 +7276,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_25_we),
@@ -7105,11 +7285,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[25].q ),
+ .q (reg2hw.le[25].q),
// to register interface (read)
.qs (le_0_le_25_qs)
@@ -7122,8 +7302,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_26_we),
@@ -7131,11 +7311,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[26].q ),
+ .q (reg2hw.le[26].q),
// to register interface (read)
.qs (le_0_le_26_qs)
@@ -7148,8 +7328,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_27_we),
@@ -7157,11 +7337,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[27].q ),
+ .q (reg2hw.le[27].q),
// to register interface (read)
.qs (le_0_le_27_qs)
@@ -7174,8 +7354,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_28_we),
@@ -7183,11 +7363,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[28].q ),
+ .q (reg2hw.le[28].q),
// to register interface (read)
.qs (le_0_le_28_qs)
@@ -7200,8 +7380,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_29_we),
@@ -7209,11 +7389,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[29].q ),
+ .q (reg2hw.le[29].q),
// to register interface (read)
.qs (le_0_le_29_qs)
@@ -7226,8 +7406,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_30_we),
@@ -7235,11 +7415,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[30].q ),
+ .q (reg2hw.le[30].q),
// to register interface (read)
.qs (le_0_le_30_qs)
@@ -7252,8 +7432,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_0_le_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_0_le_31_we),
@@ -7261,11 +7441,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[31].q ),
+ .q (reg2hw.le[31].q),
// to register interface (read)
.qs (le_0_le_31_qs)
@@ -7281,8 +7461,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_32_we),
@@ -7290,11 +7470,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[32].q ),
+ .q (reg2hw.le[32].q),
// to register interface (read)
.qs (le_1_le_32_qs)
@@ -7307,8 +7487,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_33_we),
@@ -7316,11 +7496,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[33].q ),
+ .q (reg2hw.le[33].q),
// to register interface (read)
.qs (le_1_le_33_qs)
@@ -7333,8 +7513,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_34_we),
@@ -7342,11 +7522,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[34].q ),
+ .q (reg2hw.le[34].q),
// to register interface (read)
.qs (le_1_le_34_qs)
@@ -7359,8 +7539,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_35_we),
@@ -7368,11 +7548,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[35].q ),
+ .q (reg2hw.le[35].q),
// to register interface (read)
.qs (le_1_le_35_qs)
@@ -7385,8 +7565,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_36_we),
@@ -7394,11 +7574,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[36].q ),
+ .q (reg2hw.le[36].q),
// to register interface (read)
.qs (le_1_le_36_qs)
@@ -7411,8 +7591,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_37_we),
@@ -7420,11 +7600,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[37].q ),
+ .q (reg2hw.le[37].q),
// to register interface (read)
.qs (le_1_le_37_qs)
@@ -7437,8 +7617,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_38_we),
@@ -7446,11 +7626,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[38].q ),
+ .q (reg2hw.le[38].q),
// to register interface (read)
.qs (le_1_le_38_qs)
@@ -7463,8 +7643,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_39_we),
@@ -7472,11 +7652,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[39].q ),
+ .q (reg2hw.le[39].q),
// to register interface (read)
.qs (le_1_le_39_qs)
@@ -7489,8 +7669,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_40_we),
@@ -7498,11 +7678,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[40].q ),
+ .q (reg2hw.le[40].q),
// to register interface (read)
.qs (le_1_le_40_qs)
@@ -7515,8 +7695,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_41_we),
@@ -7524,11 +7704,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[41].q ),
+ .q (reg2hw.le[41].q),
// to register interface (read)
.qs (le_1_le_41_qs)
@@ -7541,8 +7721,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_42_we),
@@ -7550,11 +7730,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[42].q ),
+ .q (reg2hw.le[42].q),
// to register interface (read)
.qs (le_1_le_42_qs)
@@ -7567,8 +7747,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_43_we),
@@ -7576,11 +7756,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[43].q ),
+ .q (reg2hw.le[43].q),
// to register interface (read)
.qs (le_1_le_43_qs)
@@ -7593,8 +7773,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_44_we),
@@ -7602,11 +7782,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[44].q ),
+ .q (reg2hw.le[44].q),
// to register interface (read)
.qs (le_1_le_44_qs)
@@ -7619,8 +7799,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_45_we),
@@ -7628,11 +7808,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[45].q ),
+ .q (reg2hw.le[45].q),
// to register interface (read)
.qs (le_1_le_45_qs)
@@ -7645,8 +7825,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_46_we),
@@ -7654,11 +7834,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[46].q ),
+ .q (reg2hw.le[46].q),
// to register interface (read)
.qs (le_1_le_46_qs)
@@ -7671,8 +7851,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_47 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_47_we),
@@ -7680,11 +7860,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[47].q ),
+ .q (reg2hw.le[47].q),
// to register interface (read)
.qs (le_1_le_47_qs)
@@ -7697,8 +7877,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_48 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_48_we),
@@ -7706,11 +7886,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[48].q ),
+ .q (reg2hw.le[48].q),
// to register interface (read)
.qs (le_1_le_48_qs)
@@ -7723,8 +7903,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_49 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_49_we),
@@ -7732,11 +7912,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[49].q ),
+ .q (reg2hw.le[49].q),
// to register interface (read)
.qs (le_1_le_49_qs)
@@ -7749,8 +7929,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_50 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_50_we),
@@ -7758,11 +7938,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[50].q ),
+ .q (reg2hw.le[50].q),
// to register interface (read)
.qs (le_1_le_50_qs)
@@ -7775,8 +7955,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_51 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_51_we),
@@ -7784,11 +7964,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[51].q ),
+ .q (reg2hw.le[51].q),
// to register interface (read)
.qs (le_1_le_51_qs)
@@ -7801,8 +7981,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_52_we),
@@ -7810,11 +7990,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[52].q ),
+ .q (reg2hw.le[52].q),
// to register interface (read)
.qs (le_1_le_52_qs)
@@ -7827,8 +8007,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_53_we),
@@ -7836,11 +8016,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[53].q ),
+ .q (reg2hw.le[53].q),
// to register interface (read)
.qs (le_1_le_53_qs)
@@ -7853,8 +8033,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_54 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_54_we),
@@ -7862,11 +8042,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[54].q ),
+ .q (reg2hw.le[54].q),
// to register interface (read)
.qs (le_1_le_54_qs)
@@ -7879,8 +8059,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_55 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_55_we),
@@ -7888,11 +8068,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[55].q ),
+ .q (reg2hw.le[55].q),
// to register interface (read)
.qs (le_1_le_55_qs)
@@ -7905,8 +8085,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_56 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_56_we),
@@ -7914,11 +8094,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[56].q ),
+ .q (reg2hw.le[56].q),
// to register interface (read)
.qs (le_1_le_56_qs)
@@ -7931,8 +8111,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_57 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_57_we),
@@ -7940,11 +8120,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[57].q ),
+ .q (reg2hw.le[57].q),
// to register interface (read)
.qs (le_1_le_57_qs)
@@ -7957,8 +8137,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_58 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_58_we),
@@ -7966,11 +8146,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[58].q ),
+ .q (reg2hw.le[58].q),
// to register interface (read)
.qs (le_1_le_58_qs)
@@ -7983,8 +8163,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_59 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_59_we),
@@ -7992,11 +8172,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[59].q ),
+ .q (reg2hw.le[59].q),
// to register interface (read)
.qs (le_1_le_59_qs)
@@ -8009,8 +8189,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_60 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_60_we),
@@ -8018,11 +8198,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[60].q ),
+ .q (reg2hw.le[60].q),
// to register interface (read)
.qs (le_1_le_60_qs)
@@ -8035,8 +8215,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_61 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_61_we),
@@ -8044,11 +8224,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[61].q ),
+ .q (reg2hw.le[61].q),
// to register interface (read)
.qs (le_1_le_61_qs)
@@ -8061,8 +8241,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_62 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_62_we),
@@ -8070,11 +8250,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[62].q ),
+ .q (reg2hw.le[62].q),
// to register interface (read)
.qs (le_1_le_62_qs)
@@ -8087,8 +8267,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_1_le_63 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_1_le_63_we),
@@ -8096,11 +8276,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[63].q ),
+ .q (reg2hw.le[63].q),
// to register interface (read)
.qs (le_1_le_63_qs)
@@ -8116,8 +8296,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_64 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_64_we),
@@ -8125,11 +8305,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[64].q ),
+ .q (reg2hw.le[64].q),
// to register interface (read)
.qs (le_2_le_64_qs)
@@ -8142,8 +8322,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_65 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_65_we),
@@ -8151,11 +8331,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[65].q ),
+ .q (reg2hw.le[65].q),
// to register interface (read)
.qs (le_2_le_65_qs)
@@ -8168,8 +8348,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_66 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_66_we),
@@ -8177,11 +8357,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[66].q ),
+ .q (reg2hw.le[66].q),
// to register interface (read)
.qs (le_2_le_66_qs)
@@ -8194,8 +8374,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_67 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_67_we),
@@ -8203,11 +8383,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[67].q ),
+ .q (reg2hw.le[67].q),
// to register interface (read)
.qs (le_2_le_67_qs)
@@ -8220,8 +8400,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_68 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_68_we),
@@ -8229,11 +8409,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[68].q ),
+ .q (reg2hw.le[68].q),
// to register interface (read)
.qs (le_2_le_68_qs)
@@ -8246,8 +8426,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_69 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_69_we),
@@ -8255,11 +8435,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[69].q ),
+ .q (reg2hw.le[69].q),
// to register interface (read)
.qs (le_2_le_69_qs)
@@ -8272,8 +8452,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_70 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_70_we),
@@ -8281,11 +8461,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[70].q ),
+ .q (reg2hw.le[70].q),
// to register interface (read)
.qs (le_2_le_70_qs)
@@ -8298,8 +8478,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_71 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_71_we),
@@ -8307,11 +8487,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[71].q ),
+ .q (reg2hw.le[71].q),
// to register interface (read)
.qs (le_2_le_71_qs)
@@ -8324,8 +8504,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_72 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_72_we),
@@ -8333,11 +8513,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[72].q ),
+ .q (reg2hw.le[72].q),
// to register interface (read)
.qs (le_2_le_72_qs)
@@ -8350,8 +8530,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_73 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_73_we),
@@ -8359,11 +8539,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[73].q ),
+ .q (reg2hw.le[73].q),
// to register interface (read)
.qs (le_2_le_73_qs)
@@ -8376,8 +8556,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_74 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_74_we),
@@ -8385,11 +8565,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[74].q ),
+ .q (reg2hw.le[74].q),
// to register interface (read)
.qs (le_2_le_74_qs)
@@ -8402,8 +8582,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_75 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_75_we),
@@ -8411,11 +8591,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[75].q ),
+ .q (reg2hw.le[75].q),
// to register interface (read)
.qs (le_2_le_75_qs)
@@ -8428,8 +8608,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_76 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_76_we),
@@ -8437,11 +8617,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[76].q ),
+ .q (reg2hw.le[76].q),
// to register interface (read)
.qs (le_2_le_76_qs)
@@ -8454,8 +8634,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_77 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_77_we),
@@ -8463,11 +8643,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[77].q ),
+ .q (reg2hw.le[77].q),
// to register interface (read)
.qs (le_2_le_77_qs)
@@ -8480,8 +8660,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_78 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_78_we),
@@ -8489,11 +8669,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[78].q ),
+ .q (reg2hw.le[78].q),
// to register interface (read)
.qs (le_2_le_78_qs)
@@ -8506,8 +8686,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_79 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_79_we),
@@ -8515,11 +8695,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[79].q ),
+ .q (reg2hw.le[79].q),
// to register interface (read)
.qs (le_2_le_79_qs)
@@ -8532,8 +8712,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_80 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_80_we),
@@ -8541,11 +8721,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[80].q ),
+ .q (reg2hw.le[80].q),
// to register interface (read)
.qs (le_2_le_80_qs)
@@ -8558,8 +8738,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_81 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_81_we),
@@ -8567,11 +8747,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[81].q ),
+ .q (reg2hw.le[81].q),
// to register interface (read)
.qs (le_2_le_81_qs)
@@ -8584,8 +8764,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_82 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_82_we),
@@ -8593,11 +8773,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[82].q ),
+ .q (reg2hw.le[82].q),
// to register interface (read)
.qs (le_2_le_82_qs)
@@ -8610,8 +8790,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_83 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_83_we),
@@ -8619,11 +8799,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[83].q ),
+ .q (reg2hw.le[83].q),
// to register interface (read)
.qs (le_2_le_83_qs)
@@ -8636,8 +8816,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_84 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_84_we),
@@ -8645,11 +8825,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[84].q ),
+ .q (reg2hw.le[84].q),
// to register interface (read)
.qs (le_2_le_84_qs)
@@ -8662,8 +8842,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_85 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_85_we),
@@ -8671,11 +8851,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[85].q ),
+ .q (reg2hw.le[85].q),
// to register interface (read)
.qs (le_2_le_85_qs)
@@ -8688,8 +8868,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_86 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_86_we),
@@ -8697,11 +8877,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[86].q ),
+ .q (reg2hw.le[86].q),
// to register interface (read)
.qs (le_2_le_86_qs)
@@ -8714,8 +8894,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_87 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_87_we),
@@ -8723,11 +8903,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[87].q ),
+ .q (reg2hw.le[87].q),
// to register interface (read)
.qs (le_2_le_87_qs)
@@ -8740,8 +8920,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_88 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_88_we),
@@ -8749,11 +8929,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[88].q ),
+ .q (reg2hw.le[88].q),
// to register interface (read)
.qs (le_2_le_88_qs)
@@ -8766,8 +8946,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_89 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_89_we),
@@ -8775,11 +8955,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[89].q ),
+ .q (reg2hw.le[89].q),
// to register interface (read)
.qs (le_2_le_89_qs)
@@ -8792,8 +8972,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_90 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_90_we),
@@ -8801,11 +8981,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[90].q ),
+ .q (reg2hw.le[90].q),
// to register interface (read)
.qs (le_2_le_90_qs)
@@ -8818,8 +8998,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_91 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_91_we),
@@ -8827,11 +9007,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[91].q ),
+ .q (reg2hw.le[91].q),
// to register interface (read)
.qs (le_2_le_91_qs)
@@ -8844,8 +9024,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_92 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_92_we),
@@ -8853,11 +9033,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[92].q ),
+ .q (reg2hw.le[92].q),
// to register interface (read)
.qs (le_2_le_92_qs)
@@ -8870,8 +9050,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_93 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_93_we),
@@ -8879,11 +9059,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[93].q ),
+ .q (reg2hw.le[93].q),
// to register interface (read)
.qs (le_2_le_93_qs)
@@ -8896,8 +9076,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_94 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_94_we),
@@ -8905,11 +9085,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[94].q ),
+ .q (reg2hw.le[94].q),
// to register interface (read)
.qs (le_2_le_94_qs)
@@ -8922,8 +9102,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_2_le_95 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_2_le_95_we),
@@ -8931,11 +9111,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[95].q ),
+ .q (reg2hw.le[95].q),
// to register interface (read)
.qs (le_2_le_95_qs)
@@ -8951,8 +9131,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_96 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_96_we),
@@ -8960,11 +9140,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[96].q ),
+ .q (reg2hw.le[96].q),
// to register interface (read)
.qs (le_3_le_96_qs)
@@ -8977,8 +9157,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_97 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_97_we),
@@ -8986,11 +9166,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[97].q ),
+ .q (reg2hw.le[97].q),
// to register interface (read)
.qs (le_3_le_97_qs)
@@ -9003,8 +9183,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_98 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_98_we),
@@ -9012,11 +9192,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[98].q ),
+ .q (reg2hw.le[98].q),
// to register interface (read)
.qs (le_3_le_98_qs)
@@ -9029,8 +9209,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_99 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_99_we),
@@ -9038,11 +9218,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[99].q ),
+ .q (reg2hw.le[99].q),
// to register interface (read)
.qs (le_3_le_99_qs)
@@ -9055,8 +9235,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_100 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_100_we),
@@ -9064,11 +9244,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[100].q ),
+ .q (reg2hw.le[100].q),
// to register interface (read)
.qs (le_3_le_100_qs)
@@ -9081,8 +9261,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_101 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_101_we),
@@ -9090,11 +9270,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[101].q ),
+ .q (reg2hw.le[101].q),
// to register interface (read)
.qs (le_3_le_101_qs)
@@ -9107,8 +9287,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_102 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_102_we),
@@ -9116,11 +9296,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[102].q ),
+ .q (reg2hw.le[102].q),
// to register interface (read)
.qs (le_3_le_102_qs)
@@ -9133,8 +9313,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_103 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_103_we),
@@ -9142,11 +9322,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[103].q ),
+ .q (reg2hw.le[103].q),
// to register interface (read)
.qs (le_3_le_103_qs)
@@ -9159,8 +9339,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_104 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_104_we),
@@ -9168,11 +9348,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[104].q ),
+ .q (reg2hw.le[104].q),
// to register interface (read)
.qs (le_3_le_104_qs)
@@ -9185,8 +9365,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_105 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_105_we),
@@ -9194,11 +9374,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[105].q ),
+ .q (reg2hw.le[105].q),
// to register interface (read)
.qs (le_3_le_105_qs)
@@ -9211,8 +9391,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_106 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_106_we),
@@ -9220,11 +9400,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[106].q ),
+ .q (reg2hw.le[106].q),
// to register interface (read)
.qs (le_3_le_106_qs)
@@ -9237,8 +9417,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_107 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_107_we),
@@ -9246,11 +9426,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[107].q ),
+ .q (reg2hw.le[107].q),
// to register interface (read)
.qs (le_3_le_107_qs)
@@ -9263,8 +9443,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_108 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_108_we),
@@ -9272,11 +9452,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[108].q ),
+ .q (reg2hw.le[108].q),
// to register interface (read)
.qs (le_3_le_108_qs)
@@ -9289,8 +9469,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_109 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_109_we),
@@ -9298,11 +9478,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[109].q ),
+ .q (reg2hw.le[109].q),
// to register interface (read)
.qs (le_3_le_109_qs)
@@ -9315,8 +9495,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_110 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_110_we),
@@ -9324,11 +9504,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[110].q ),
+ .q (reg2hw.le[110].q),
// to register interface (read)
.qs (le_3_le_110_qs)
@@ -9341,8 +9521,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_111 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_111_we),
@@ -9350,11 +9530,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[111].q ),
+ .q (reg2hw.le[111].q),
// to register interface (read)
.qs (le_3_le_111_qs)
@@ -9367,8 +9547,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_112 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_112_we),
@@ -9376,11 +9556,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[112].q ),
+ .q (reg2hw.le[112].q),
// to register interface (read)
.qs (le_3_le_112_qs)
@@ -9393,8 +9573,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_113 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_113_we),
@@ -9402,11 +9582,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[113].q ),
+ .q (reg2hw.le[113].q),
// to register interface (read)
.qs (le_3_le_113_qs)
@@ -9419,8 +9599,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_114 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_114_we),
@@ -9428,11 +9608,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[114].q ),
+ .q (reg2hw.le[114].q),
// to register interface (read)
.qs (le_3_le_114_qs)
@@ -9445,8 +9625,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_115 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_115_we),
@@ -9454,11 +9634,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[115].q ),
+ .q (reg2hw.le[115].q),
// to register interface (read)
.qs (le_3_le_115_qs)
@@ -9471,8 +9651,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_116 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_116_we),
@@ -9480,11 +9660,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[116].q ),
+ .q (reg2hw.le[116].q),
// to register interface (read)
.qs (le_3_le_116_qs)
@@ -9497,8 +9677,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_117 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_117_we),
@@ -9506,11 +9686,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[117].q ),
+ .q (reg2hw.le[117].q),
// to register interface (read)
.qs (le_3_le_117_qs)
@@ -9523,8 +9703,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_118 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_118_we),
@@ -9532,11 +9712,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[118].q ),
+ .q (reg2hw.le[118].q),
// to register interface (read)
.qs (le_3_le_118_qs)
@@ -9549,8 +9729,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_119 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_119_we),
@@ -9558,11 +9738,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[119].q ),
+ .q (reg2hw.le[119].q),
// to register interface (read)
.qs (le_3_le_119_qs)
@@ -9575,8 +9755,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_120 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_120_we),
@@ -9584,11 +9764,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[120].q ),
+ .q (reg2hw.le[120].q),
// to register interface (read)
.qs (le_3_le_120_qs)
@@ -9601,8 +9781,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_121 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_121_we),
@@ -9610,11 +9790,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[121].q ),
+ .q (reg2hw.le[121].q),
// to register interface (read)
.qs (le_3_le_121_qs)
@@ -9627,8 +9807,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_122 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_122_we),
@@ -9636,11 +9816,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[122].q ),
+ .q (reg2hw.le[122].q),
// to register interface (read)
.qs (le_3_le_122_qs)
@@ -9653,8 +9833,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_123 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_123_we),
@@ -9662,11 +9842,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[123].q ),
+ .q (reg2hw.le[123].q),
// to register interface (read)
.qs (le_3_le_123_qs)
@@ -9679,8 +9859,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_124 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_124_we),
@@ -9688,11 +9868,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[124].q ),
+ .q (reg2hw.le[124].q),
// to register interface (read)
.qs (le_3_le_124_qs)
@@ -9705,8 +9885,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_125 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_125_we),
@@ -9714,11 +9894,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[125].q ),
+ .q (reg2hw.le[125].q),
// to register interface (read)
.qs (le_3_le_125_qs)
@@ -9731,8 +9911,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_126 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_126_we),
@@ -9740,11 +9920,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[126].q ),
+ .q (reg2hw.le[126].q),
// to register interface (read)
.qs (le_3_le_126_qs)
@@ -9757,8 +9937,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_3_le_127 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_3_le_127_we),
@@ -9766,11 +9946,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[127].q ),
+ .q (reg2hw.le[127].q),
// to register interface (read)
.qs (le_3_le_127_qs)
@@ -9786,8 +9966,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_128 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_128_we),
@@ -9795,11 +9975,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[128].q ),
+ .q (reg2hw.le[128].q),
// to register interface (read)
.qs (le_4_le_128_qs)
@@ -9812,8 +9992,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_129 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_129_we),
@@ -9821,11 +10001,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[129].q ),
+ .q (reg2hw.le[129].q),
// to register interface (read)
.qs (le_4_le_129_qs)
@@ -9838,8 +10018,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_130 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_130_we),
@@ -9847,11 +10027,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[130].q ),
+ .q (reg2hw.le[130].q),
// to register interface (read)
.qs (le_4_le_130_qs)
@@ -9864,8 +10044,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_131 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_131_we),
@@ -9873,11 +10053,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[131].q ),
+ .q (reg2hw.le[131].q),
// to register interface (read)
.qs (le_4_le_131_qs)
@@ -9890,8 +10070,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_132 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_132_we),
@@ -9899,11 +10079,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[132].q ),
+ .q (reg2hw.le[132].q),
// to register interface (read)
.qs (le_4_le_132_qs)
@@ -9916,8 +10096,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_133 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_133_we),
@@ -9925,11 +10105,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[133].q ),
+ .q (reg2hw.le[133].q),
// to register interface (read)
.qs (le_4_le_133_qs)
@@ -9942,8 +10122,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_134 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_134_we),
@@ -9951,11 +10131,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[134].q ),
+ .q (reg2hw.le[134].q),
// to register interface (read)
.qs (le_4_le_134_qs)
@@ -9968,8 +10148,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_135 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_135_we),
@@ -9977,11 +10157,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[135].q ),
+ .q (reg2hw.le[135].q),
// to register interface (read)
.qs (le_4_le_135_qs)
@@ -9994,8 +10174,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_136 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_136_we),
@@ -10003,11 +10183,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[136].q ),
+ .q (reg2hw.le[136].q),
// to register interface (read)
.qs (le_4_le_136_qs)
@@ -10020,8 +10200,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_137 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_137_we),
@@ -10029,11 +10209,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[137].q ),
+ .q (reg2hw.le[137].q),
// to register interface (read)
.qs (le_4_le_137_qs)
@@ -10046,8 +10226,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_138 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_138_we),
@@ -10055,11 +10235,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[138].q ),
+ .q (reg2hw.le[138].q),
// to register interface (read)
.qs (le_4_le_138_qs)
@@ -10072,8 +10252,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_139 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_139_we),
@@ -10081,11 +10261,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[139].q ),
+ .q (reg2hw.le[139].q),
// to register interface (read)
.qs (le_4_le_139_qs)
@@ -10098,8 +10278,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_140 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_140_we),
@@ -10107,11 +10287,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[140].q ),
+ .q (reg2hw.le[140].q),
// to register interface (read)
.qs (le_4_le_140_qs)
@@ -10124,8 +10304,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_141 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_141_we),
@@ -10133,11 +10313,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[141].q ),
+ .q (reg2hw.le[141].q),
// to register interface (read)
.qs (le_4_le_141_qs)
@@ -10150,8 +10330,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_142 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_142_we),
@@ -10159,11 +10339,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[142].q ),
+ .q (reg2hw.le[142].q),
// to register interface (read)
.qs (le_4_le_142_qs)
@@ -10176,8 +10356,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_143 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_143_we),
@@ -10185,11 +10365,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[143].q ),
+ .q (reg2hw.le[143].q),
// to register interface (read)
.qs (le_4_le_143_qs)
@@ -10202,8 +10382,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_144 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_144_we),
@@ -10211,11 +10391,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[144].q ),
+ .q (reg2hw.le[144].q),
// to register interface (read)
.qs (le_4_le_144_qs)
@@ -10228,8 +10408,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_145 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_145_we),
@@ -10237,11 +10417,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[145].q ),
+ .q (reg2hw.le[145].q),
// to register interface (read)
.qs (le_4_le_145_qs)
@@ -10254,8 +10434,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_146 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_146_we),
@@ -10263,11 +10443,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[146].q ),
+ .q (reg2hw.le[146].q),
// to register interface (read)
.qs (le_4_le_146_qs)
@@ -10280,8 +10460,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_147 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_147_we),
@@ -10289,11 +10469,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[147].q ),
+ .q (reg2hw.le[147].q),
// to register interface (read)
.qs (le_4_le_147_qs)
@@ -10306,8 +10486,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_148 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_148_we),
@@ -10315,11 +10495,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[148].q ),
+ .q (reg2hw.le[148].q),
// to register interface (read)
.qs (le_4_le_148_qs)
@@ -10332,8 +10512,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_149 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_149_we),
@@ -10341,11 +10521,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[149].q ),
+ .q (reg2hw.le[149].q),
// to register interface (read)
.qs (le_4_le_149_qs)
@@ -10358,8 +10538,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_150 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_150_we),
@@ -10367,11 +10547,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[150].q ),
+ .q (reg2hw.le[150].q),
// to register interface (read)
.qs (le_4_le_150_qs)
@@ -10384,8 +10564,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_151 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_151_we),
@@ -10393,11 +10573,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[151].q ),
+ .q (reg2hw.le[151].q),
// to register interface (read)
.qs (le_4_le_151_qs)
@@ -10410,8 +10590,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_152 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_152_we),
@@ -10419,11 +10599,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[152].q ),
+ .q (reg2hw.le[152].q),
// to register interface (read)
.qs (le_4_le_152_qs)
@@ -10436,8 +10616,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_153 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_153_we),
@@ -10445,11 +10625,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[153].q ),
+ .q (reg2hw.le[153].q),
// to register interface (read)
.qs (le_4_le_153_qs)
@@ -10462,8 +10642,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_154 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_154_we),
@@ -10471,11 +10651,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[154].q ),
+ .q (reg2hw.le[154].q),
// to register interface (read)
.qs (le_4_le_154_qs)
@@ -10488,8 +10668,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_155 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_155_we),
@@ -10497,11 +10677,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[155].q ),
+ .q (reg2hw.le[155].q),
// to register interface (read)
.qs (le_4_le_155_qs)
@@ -10514,8 +10694,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_156 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_156_we),
@@ -10523,11 +10703,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[156].q ),
+ .q (reg2hw.le[156].q),
// to register interface (read)
.qs (le_4_le_156_qs)
@@ -10540,8 +10720,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_157 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_157_we),
@@ -10549,11 +10729,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[157].q ),
+ .q (reg2hw.le[157].q),
// to register interface (read)
.qs (le_4_le_157_qs)
@@ -10566,8 +10746,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_158 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_158_we),
@@ -10575,11 +10755,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[158].q ),
+ .q (reg2hw.le[158].q),
// to register interface (read)
.qs (le_4_le_158_qs)
@@ -10592,8 +10772,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_4_le_159 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_4_le_159_we),
@@ -10601,11 +10781,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[159].q ),
+ .q (reg2hw.le[159].q),
// to register interface (read)
.qs (le_4_le_159_qs)
@@ -10621,8 +10801,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_160 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_160_we),
@@ -10630,11 +10810,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[160].q ),
+ .q (reg2hw.le[160].q),
// to register interface (read)
.qs (le_5_le_160_qs)
@@ -10647,8 +10827,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_161 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_161_we),
@@ -10656,11 +10836,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[161].q ),
+ .q (reg2hw.le[161].q),
// to register interface (read)
.qs (le_5_le_161_qs)
@@ -10673,8 +10853,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_162 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_162_we),
@@ -10682,11 +10862,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[162].q ),
+ .q (reg2hw.le[162].q),
// to register interface (read)
.qs (le_5_le_162_qs)
@@ -10699,8 +10879,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_163 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_163_we),
@@ -10708,11 +10888,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[163].q ),
+ .q (reg2hw.le[163].q),
// to register interface (read)
.qs (le_5_le_163_qs)
@@ -10725,8 +10905,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_164 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_164_we),
@@ -10734,11 +10914,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[164].q ),
+ .q (reg2hw.le[164].q),
// to register interface (read)
.qs (le_5_le_164_qs)
@@ -10751,8 +10931,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_165 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_165_we),
@@ -10760,11 +10940,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[165].q ),
+ .q (reg2hw.le[165].q),
// to register interface (read)
.qs (le_5_le_165_qs)
@@ -10777,8 +10957,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_166 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_166_we),
@@ -10786,11 +10966,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[166].q ),
+ .q (reg2hw.le[166].q),
// to register interface (read)
.qs (le_5_le_166_qs)
@@ -10803,8 +10983,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_167 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_167_we),
@@ -10812,11 +10992,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[167].q ),
+ .q (reg2hw.le[167].q),
// to register interface (read)
.qs (le_5_le_167_qs)
@@ -10829,8 +11009,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_168 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_168_we),
@@ -10838,11 +11018,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[168].q ),
+ .q (reg2hw.le[168].q),
// to register interface (read)
.qs (le_5_le_168_qs)
@@ -10855,8 +11035,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_169 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_169_we),
@@ -10864,11 +11044,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[169].q ),
+ .q (reg2hw.le[169].q),
// to register interface (read)
.qs (le_5_le_169_qs)
@@ -10881,8 +11061,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_170 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_170_we),
@@ -10890,11 +11070,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[170].q ),
+ .q (reg2hw.le[170].q),
// to register interface (read)
.qs (le_5_le_170_qs)
@@ -10907,8 +11087,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_171 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_171_we),
@@ -10916,11 +11096,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[171].q ),
+ .q (reg2hw.le[171].q),
// to register interface (read)
.qs (le_5_le_171_qs)
@@ -10933,8 +11113,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_172 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_172_we),
@@ -10942,11 +11122,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[172].q ),
+ .q (reg2hw.le[172].q),
// to register interface (read)
.qs (le_5_le_172_qs)
@@ -10959,8 +11139,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_173 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_173_we),
@@ -10968,11 +11148,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[173].q ),
+ .q (reg2hw.le[173].q),
// to register interface (read)
.qs (le_5_le_173_qs)
@@ -10985,8 +11165,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_174 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_174_we),
@@ -10994,11 +11174,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[174].q ),
+ .q (reg2hw.le[174].q),
// to register interface (read)
.qs (le_5_le_174_qs)
@@ -11011,8 +11191,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_175 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_175_we),
@@ -11020,11 +11200,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[175].q ),
+ .q (reg2hw.le[175].q),
// to register interface (read)
.qs (le_5_le_175_qs)
@@ -11037,8 +11217,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_176 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_176_we),
@@ -11046,11 +11226,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[176].q ),
+ .q (reg2hw.le[176].q),
// to register interface (read)
.qs (le_5_le_176_qs)
@@ -11063,8 +11243,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_177 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_177_we),
@@ -11072,11 +11252,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[177].q ),
+ .q (reg2hw.le[177].q),
// to register interface (read)
.qs (le_5_le_177_qs)
@@ -11089,8 +11269,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_178 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_178_we),
@@ -11098,11 +11278,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[178].q ),
+ .q (reg2hw.le[178].q),
// to register interface (read)
.qs (le_5_le_178_qs)
@@ -11115,8 +11295,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_le_5_le_179 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (le_5_le_179_we),
@@ -11124,11 +11304,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.le[179].q ),
+ .q (reg2hw.le[179].q),
// to register interface (read)
.qs (le_5_le_179_qs)
@@ -11143,8 +11323,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio0_we),
@@ -11152,11 +11332,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio0.q ),
+ .q (reg2hw.prio0.q),
// to register interface (read)
.qs (prio0_qs)
@@ -11170,8 +11350,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio1_we),
@@ -11179,11 +11359,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio1.q ),
+ .q (reg2hw.prio1.q),
// to register interface (read)
.qs (prio1_qs)
@@ -11197,8 +11377,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio2_we),
@@ -11206,11 +11386,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio2.q ),
+ .q (reg2hw.prio2.q),
// to register interface (read)
.qs (prio2_qs)
@@ -11224,8 +11404,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio3_we),
@@ -11233,11 +11413,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio3.q ),
+ .q (reg2hw.prio3.q),
// to register interface (read)
.qs (prio3_qs)
@@ -11251,8 +11431,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio4_we),
@@ -11260,11 +11440,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio4.q ),
+ .q (reg2hw.prio4.q),
// to register interface (read)
.qs (prio4_qs)
@@ -11278,8 +11458,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio5_we),
@@ -11287,11 +11467,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio5.q ),
+ .q (reg2hw.prio5.q),
// to register interface (read)
.qs (prio5_qs)
@@ -11305,8 +11485,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio6_we),
@@ -11314,11 +11494,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio6.q ),
+ .q (reg2hw.prio6.q),
// to register interface (read)
.qs (prio6_qs)
@@ -11332,8 +11512,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio7_we),
@@ -11341,11 +11521,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio7.q ),
+ .q (reg2hw.prio7.q),
// to register interface (read)
.qs (prio7_qs)
@@ -11359,8 +11539,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio8_we),
@@ -11368,11 +11548,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio8.q ),
+ .q (reg2hw.prio8.q),
// to register interface (read)
.qs (prio8_qs)
@@ -11386,8 +11566,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio9_we),
@@ -11395,11 +11575,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio9.q ),
+ .q (reg2hw.prio9.q),
// to register interface (read)
.qs (prio9_qs)
@@ -11413,8 +11593,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio10_we),
@@ -11422,11 +11602,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio10.q ),
+ .q (reg2hw.prio10.q),
// to register interface (read)
.qs (prio10_qs)
@@ -11440,8 +11620,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio11_we),
@@ -11449,11 +11629,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio11.q ),
+ .q (reg2hw.prio11.q),
// to register interface (read)
.qs (prio11_qs)
@@ -11467,8 +11647,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio12_we),
@@ -11476,11 +11656,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio12.q ),
+ .q (reg2hw.prio12.q),
// to register interface (read)
.qs (prio12_qs)
@@ -11494,8 +11674,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio13_we),
@@ -11503,11 +11683,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio13.q ),
+ .q (reg2hw.prio13.q),
// to register interface (read)
.qs (prio13_qs)
@@ -11521,8 +11701,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio14_we),
@@ -11530,11 +11710,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio14.q ),
+ .q (reg2hw.prio14.q),
// to register interface (read)
.qs (prio14_qs)
@@ -11548,8 +11728,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio15_we),
@@ -11557,11 +11737,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio15.q ),
+ .q (reg2hw.prio15.q),
// to register interface (read)
.qs (prio15_qs)
@@ -11575,8 +11755,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio16_we),
@@ -11584,11 +11764,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio16.q ),
+ .q (reg2hw.prio16.q),
// to register interface (read)
.qs (prio16_qs)
@@ -11602,8 +11782,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio17_we),
@@ -11611,11 +11791,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio17.q ),
+ .q (reg2hw.prio17.q),
// to register interface (read)
.qs (prio17_qs)
@@ -11629,8 +11809,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio18_we),
@@ -11638,11 +11818,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio18.q ),
+ .q (reg2hw.prio18.q),
// to register interface (read)
.qs (prio18_qs)
@@ -11656,8 +11836,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio19_we),
@@ -11665,11 +11845,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio19.q ),
+ .q (reg2hw.prio19.q),
// to register interface (read)
.qs (prio19_qs)
@@ -11683,8 +11863,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio20_we),
@@ -11692,11 +11872,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio20.q ),
+ .q (reg2hw.prio20.q),
// to register interface (read)
.qs (prio20_qs)
@@ -11710,8 +11890,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio21_we),
@@ -11719,11 +11899,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio21.q ),
+ .q (reg2hw.prio21.q),
// to register interface (read)
.qs (prio21_qs)
@@ -11737,8 +11917,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio22_we),
@@ -11746,11 +11926,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio22.q ),
+ .q (reg2hw.prio22.q),
// to register interface (read)
.qs (prio22_qs)
@@ -11764,8 +11944,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio23_we),
@@ -11773,11 +11953,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio23.q ),
+ .q (reg2hw.prio23.q),
// to register interface (read)
.qs (prio23_qs)
@@ -11791,8 +11971,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio24_we),
@@ -11800,11 +11980,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio24.q ),
+ .q (reg2hw.prio24.q),
// to register interface (read)
.qs (prio24_qs)
@@ -11818,8 +11998,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio25_we),
@@ -11827,11 +12007,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio25.q ),
+ .q (reg2hw.prio25.q),
// to register interface (read)
.qs (prio25_qs)
@@ -11845,8 +12025,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio26_we),
@@ -11854,11 +12034,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio26.q ),
+ .q (reg2hw.prio26.q),
// to register interface (read)
.qs (prio26_qs)
@@ -11872,8 +12052,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio27_we),
@@ -11881,11 +12061,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio27.q ),
+ .q (reg2hw.prio27.q),
// to register interface (read)
.qs (prio27_qs)
@@ -11899,8 +12079,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio28_we),
@@ -11908,11 +12088,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio28.q ),
+ .q (reg2hw.prio28.q),
// to register interface (read)
.qs (prio28_qs)
@@ -11926,8 +12106,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio29_we),
@@ -11935,11 +12115,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio29.q ),
+ .q (reg2hw.prio29.q),
// to register interface (read)
.qs (prio29_qs)
@@ -11953,8 +12133,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio30_we),
@@ -11962,11 +12142,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio30.q ),
+ .q (reg2hw.prio30.q),
// to register interface (read)
.qs (prio30_qs)
@@ -11980,8 +12160,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio31_we),
@@ -11989,11 +12169,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio31.q ),
+ .q (reg2hw.prio31.q),
// to register interface (read)
.qs (prio31_qs)
@@ -12007,8 +12187,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio32_we),
@@ -12016,11 +12196,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio32.q ),
+ .q (reg2hw.prio32.q),
// to register interface (read)
.qs (prio32_qs)
@@ -12034,8 +12214,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio33_we),
@@ -12043,11 +12223,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio33.q ),
+ .q (reg2hw.prio33.q),
// to register interface (read)
.qs (prio33_qs)
@@ -12061,8 +12241,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio34_we),
@@ -12070,11 +12250,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio34.q ),
+ .q (reg2hw.prio34.q),
// to register interface (read)
.qs (prio34_qs)
@@ -12088,8 +12268,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio35_we),
@@ -12097,11 +12277,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio35.q ),
+ .q (reg2hw.prio35.q),
// to register interface (read)
.qs (prio35_qs)
@@ -12115,8 +12295,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio36_we),
@@ -12124,11 +12304,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio36.q ),
+ .q (reg2hw.prio36.q),
// to register interface (read)
.qs (prio36_qs)
@@ -12142,8 +12322,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio37_we),
@@ -12151,11 +12331,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio37.q ),
+ .q (reg2hw.prio37.q),
// to register interface (read)
.qs (prio37_qs)
@@ -12169,8 +12349,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio38_we),
@@ -12178,11 +12358,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio38.q ),
+ .q (reg2hw.prio38.q),
// to register interface (read)
.qs (prio38_qs)
@@ -12196,8 +12376,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio39_we),
@@ -12205,11 +12385,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio39.q ),
+ .q (reg2hw.prio39.q),
// to register interface (read)
.qs (prio39_qs)
@@ -12223,8 +12403,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio40_we),
@@ -12232,11 +12412,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio40.q ),
+ .q (reg2hw.prio40.q),
// to register interface (read)
.qs (prio40_qs)
@@ -12250,8 +12430,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio41_we),
@@ -12259,11 +12439,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio41.q ),
+ .q (reg2hw.prio41.q),
// to register interface (read)
.qs (prio41_qs)
@@ -12277,8 +12457,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio42_we),
@@ -12286,11 +12466,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio42.q ),
+ .q (reg2hw.prio42.q),
// to register interface (read)
.qs (prio42_qs)
@@ -12304,8 +12484,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio43_we),
@@ -12313,11 +12493,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio43.q ),
+ .q (reg2hw.prio43.q),
// to register interface (read)
.qs (prio43_qs)
@@ -12331,8 +12511,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio44_we),
@@ -12340,11 +12520,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio44.q ),
+ .q (reg2hw.prio44.q),
// to register interface (read)
.qs (prio44_qs)
@@ -12358,8 +12538,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio45_we),
@@ -12367,11 +12547,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio45.q ),
+ .q (reg2hw.prio45.q),
// to register interface (read)
.qs (prio45_qs)
@@ -12385,8 +12565,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio46_we),
@@ -12394,11 +12574,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio46.q ),
+ .q (reg2hw.prio46.q),
// to register interface (read)
.qs (prio46_qs)
@@ -12412,8 +12592,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio47 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio47_we),
@@ -12421,11 +12601,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio47.q ),
+ .q (reg2hw.prio47.q),
// to register interface (read)
.qs (prio47_qs)
@@ -12439,8 +12619,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio48 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio48_we),
@@ -12448,11 +12628,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio48.q ),
+ .q (reg2hw.prio48.q),
// to register interface (read)
.qs (prio48_qs)
@@ -12466,8 +12646,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio49 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio49_we),
@@ -12475,11 +12655,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio49.q ),
+ .q (reg2hw.prio49.q),
// to register interface (read)
.qs (prio49_qs)
@@ -12493,8 +12673,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio50 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio50_we),
@@ -12502,11 +12682,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio50.q ),
+ .q (reg2hw.prio50.q),
// to register interface (read)
.qs (prio50_qs)
@@ -12520,8 +12700,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio51 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio51_we),
@@ -12529,11 +12709,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio51.q ),
+ .q (reg2hw.prio51.q),
// to register interface (read)
.qs (prio51_qs)
@@ -12547,8 +12727,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio52_we),
@@ -12556,11 +12736,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio52.q ),
+ .q (reg2hw.prio52.q),
// to register interface (read)
.qs (prio52_qs)
@@ -12574,8 +12754,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio53_we),
@@ -12583,11 +12763,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio53.q ),
+ .q (reg2hw.prio53.q),
// to register interface (read)
.qs (prio53_qs)
@@ -12601,8 +12781,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio54 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio54_we),
@@ -12610,11 +12790,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio54.q ),
+ .q (reg2hw.prio54.q),
// to register interface (read)
.qs (prio54_qs)
@@ -12628,8 +12808,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio55 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio55_we),
@@ -12637,11 +12817,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio55.q ),
+ .q (reg2hw.prio55.q),
// to register interface (read)
.qs (prio55_qs)
@@ -12655,8 +12835,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio56 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio56_we),
@@ -12664,11 +12844,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio56.q ),
+ .q (reg2hw.prio56.q),
// to register interface (read)
.qs (prio56_qs)
@@ -12682,8 +12862,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio57 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio57_we),
@@ -12691,11 +12871,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio57.q ),
+ .q (reg2hw.prio57.q),
// to register interface (read)
.qs (prio57_qs)
@@ -12709,8 +12889,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio58 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio58_we),
@@ -12718,11 +12898,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio58.q ),
+ .q (reg2hw.prio58.q),
// to register interface (read)
.qs (prio58_qs)
@@ -12736,8 +12916,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio59 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio59_we),
@@ -12745,11 +12925,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio59.q ),
+ .q (reg2hw.prio59.q),
// to register interface (read)
.qs (prio59_qs)
@@ -12763,8 +12943,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio60 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio60_we),
@@ -12772,11 +12952,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio60.q ),
+ .q (reg2hw.prio60.q),
// to register interface (read)
.qs (prio60_qs)
@@ -12790,8 +12970,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio61 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio61_we),
@@ -12799,11 +12979,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio61.q ),
+ .q (reg2hw.prio61.q),
// to register interface (read)
.qs (prio61_qs)
@@ -12817,8 +12997,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio62 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio62_we),
@@ -12826,11 +13006,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio62.q ),
+ .q (reg2hw.prio62.q),
// to register interface (read)
.qs (prio62_qs)
@@ -12844,8 +13024,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio63 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio63_we),
@@ -12853,11 +13033,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio63.q ),
+ .q (reg2hw.prio63.q),
// to register interface (read)
.qs (prio63_qs)
@@ -12871,8 +13051,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio64 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio64_we),
@@ -12880,11 +13060,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio64.q ),
+ .q (reg2hw.prio64.q),
// to register interface (read)
.qs (prio64_qs)
@@ -12898,8 +13078,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio65 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio65_we),
@@ -12907,11 +13087,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio65.q ),
+ .q (reg2hw.prio65.q),
// to register interface (read)
.qs (prio65_qs)
@@ -12925,8 +13105,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio66 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio66_we),
@@ -12934,11 +13114,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio66.q ),
+ .q (reg2hw.prio66.q),
// to register interface (read)
.qs (prio66_qs)
@@ -12952,8 +13132,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio67 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio67_we),
@@ -12961,11 +13141,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio67.q ),
+ .q (reg2hw.prio67.q),
// to register interface (read)
.qs (prio67_qs)
@@ -12979,8 +13159,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio68 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio68_we),
@@ -12988,11 +13168,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio68.q ),
+ .q (reg2hw.prio68.q),
// to register interface (read)
.qs (prio68_qs)
@@ -13006,8 +13186,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio69 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio69_we),
@@ -13015,11 +13195,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio69.q ),
+ .q (reg2hw.prio69.q),
// to register interface (read)
.qs (prio69_qs)
@@ -13033,8 +13213,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio70 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio70_we),
@@ -13042,11 +13222,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio70.q ),
+ .q (reg2hw.prio70.q),
// to register interface (read)
.qs (prio70_qs)
@@ -13060,8 +13240,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio71 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio71_we),
@@ -13069,11 +13249,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio71.q ),
+ .q (reg2hw.prio71.q),
// to register interface (read)
.qs (prio71_qs)
@@ -13087,8 +13267,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio72 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio72_we),
@@ -13096,11 +13276,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio72.q ),
+ .q (reg2hw.prio72.q),
// to register interface (read)
.qs (prio72_qs)
@@ -13114,8 +13294,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio73 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio73_we),
@@ -13123,11 +13303,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio73.q ),
+ .q (reg2hw.prio73.q),
// to register interface (read)
.qs (prio73_qs)
@@ -13141,8 +13321,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio74 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio74_we),
@@ -13150,11 +13330,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio74.q ),
+ .q (reg2hw.prio74.q),
// to register interface (read)
.qs (prio74_qs)
@@ -13168,8 +13348,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio75 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio75_we),
@@ -13177,11 +13357,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio75.q ),
+ .q (reg2hw.prio75.q),
// to register interface (read)
.qs (prio75_qs)
@@ -13195,8 +13375,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio76 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio76_we),
@@ -13204,11 +13384,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio76.q ),
+ .q (reg2hw.prio76.q),
// to register interface (read)
.qs (prio76_qs)
@@ -13222,8 +13402,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio77 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio77_we),
@@ -13231,11 +13411,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio77.q ),
+ .q (reg2hw.prio77.q),
// to register interface (read)
.qs (prio77_qs)
@@ -13249,8 +13429,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio78 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio78_we),
@@ -13258,11 +13438,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio78.q ),
+ .q (reg2hw.prio78.q),
// to register interface (read)
.qs (prio78_qs)
@@ -13276,8 +13456,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio79 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio79_we),
@@ -13285,11 +13465,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio79.q ),
+ .q (reg2hw.prio79.q),
// to register interface (read)
.qs (prio79_qs)
@@ -13303,8 +13483,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio80 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio80_we),
@@ -13312,11 +13492,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio80.q ),
+ .q (reg2hw.prio80.q),
// to register interface (read)
.qs (prio80_qs)
@@ -13330,8 +13510,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio81 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio81_we),
@@ -13339,11 +13519,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio81.q ),
+ .q (reg2hw.prio81.q),
// to register interface (read)
.qs (prio81_qs)
@@ -13357,8 +13537,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio82 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio82_we),
@@ -13366,11 +13546,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio82.q ),
+ .q (reg2hw.prio82.q),
// to register interface (read)
.qs (prio82_qs)
@@ -13384,8 +13564,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio83 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio83_we),
@@ -13393,11 +13573,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio83.q ),
+ .q (reg2hw.prio83.q),
// to register interface (read)
.qs (prio83_qs)
@@ -13411,8 +13591,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio84 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio84_we),
@@ -13420,11 +13600,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio84.q ),
+ .q (reg2hw.prio84.q),
// to register interface (read)
.qs (prio84_qs)
@@ -13438,8 +13618,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio85 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio85_we),
@@ -13447,11 +13627,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio85.q ),
+ .q (reg2hw.prio85.q),
// to register interface (read)
.qs (prio85_qs)
@@ -13465,8 +13645,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio86 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio86_we),
@@ -13474,11 +13654,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio86.q ),
+ .q (reg2hw.prio86.q),
// to register interface (read)
.qs (prio86_qs)
@@ -13492,8 +13672,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio87 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio87_we),
@@ -13501,11 +13681,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio87.q ),
+ .q (reg2hw.prio87.q),
// to register interface (read)
.qs (prio87_qs)
@@ -13519,8 +13699,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio88 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio88_we),
@@ -13528,11 +13708,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio88.q ),
+ .q (reg2hw.prio88.q),
// to register interface (read)
.qs (prio88_qs)
@@ -13546,8 +13726,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio89 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio89_we),
@@ -13555,11 +13735,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio89.q ),
+ .q (reg2hw.prio89.q),
// to register interface (read)
.qs (prio89_qs)
@@ -13573,8 +13753,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio90 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio90_we),
@@ -13582,11 +13762,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio90.q ),
+ .q (reg2hw.prio90.q),
// to register interface (read)
.qs (prio90_qs)
@@ -13600,8 +13780,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio91 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio91_we),
@@ -13609,11 +13789,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio91.q ),
+ .q (reg2hw.prio91.q),
// to register interface (read)
.qs (prio91_qs)
@@ -13627,8 +13807,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio92 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio92_we),
@@ -13636,11 +13816,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio92.q ),
+ .q (reg2hw.prio92.q),
// to register interface (read)
.qs (prio92_qs)
@@ -13654,8 +13834,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio93 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio93_we),
@@ -13663,11 +13843,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio93.q ),
+ .q (reg2hw.prio93.q),
// to register interface (read)
.qs (prio93_qs)
@@ -13681,8 +13861,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio94 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio94_we),
@@ -13690,11 +13870,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio94.q ),
+ .q (reg2hw.prio94.q),
// to register interface (read)
.qs (prio94_qs)
@@ -13708,8 +13888,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio95 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio95_we),
@@ -13717,11 +13897,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio95.q ),
+ .q (reg2hw.prio95.q),
// to register interface (read)
.qs (prio95_qs)
@@ -13735,8 +13915,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio96 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio96_we),
@@ -13744,11 +13924,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio96.q ),
+ .q (reg2hw.prio96.q),
// to register interface (read)
.qs (prio96_qs)
@@ -13762,8 +13942,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio97 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio97_we),
@@ -13771,11 +13951,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio97.q ),
+ .q (reg2hw.prio97.q),
// to register interface (read)
.qs (prio97_qs)
@@ -13789,8 +13969,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio98 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio98_we),
@@ -13798,11 +13978,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio98.q ),
+ .q (reg2hw.prio98.q),
// to register interface (read)
.qs (prio98_qs)
@@ -13816,8 +13996,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio99 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio99_we),
@@ -13825,11 +14005,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio99.q ),
+ .q (reg2hw.prio99.q),
// to register interface (read)
.qs (prio99_qs)
@@ -13843,8 +14023,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio100 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio100_we),
@@ -13852,11 +14032,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio100.q ),
+ .q (reg2hw.prio100.q),
// to register interface (read)
.qs (prio100_qs)
@@ -13870,8 +14050,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio101 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio101_we),
@@ -13879,11 +14059,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio101.q ),
+ .q (reg2hw.prio101.q),
// to register interface (read)
.qs (prio101_qs)
@@ -13897,8 +14077,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio102 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio102_we),
@@ -13906,11 +14086,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio102.q ),
+ .q (reg2hw.prio102.q),
// to register interface (read)
.qs (prio102_qs)
@@ -13924,8 +14104,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio103 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio103_we),
@@ -13933,11 +14113,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio103.q ),
+ .q (reg2hw.prio103.q),
// to register interface (read)
.qs (prio103_qs)
@@ -13951,8 +14131,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio104 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio104_we),
@@ -13960,11 +14140,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio104.q ),
+ .q (reg2hw.prio104.q),
// to register interface (read)
.qs (prio104_qs)
@@ -13978,8 +14158,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio105 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio105_we),
@@ -13987,11 +14167,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio105.q ),
+ .q (reg2hw.prio105.q),
// to register interface (read)
.qs (prio105_qs)
@@ -14005,8 +14185,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio106 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio106_we),
@@ -14014,11 +14194,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio106.q ),
+ .q (reg2hw.prio106.q),
// to register interface (read)
.qs (prio106_qs)
@@ -14032,8 +14212,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio107 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio107_we),
@@ -14041,11 +14221,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio107.q ),
+ .q (reg2hw.prio107.q),
// to register interface (read)
.qs (prio107_qs)
@@ -14059,8 +14239,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio108 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio108_we),
@@ -14068,11 +14248,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio108.q ),
+ .q (reg2hw.prio108.q),
// to register interface (read)
.qs (prio108_qs)
@@ -14086,8 +14266,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio109 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio109_we),
@@ -14095,11 +14275,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio109.q ),
+ .q (reg2hw.prio109.q),
// to register interface (read)
.qs (prio109_qs)
@@ -14113,8 +14293,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio110 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio110_we),
@@ -14122,11 +14302,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio110.q ),
+ .q (reg2hw.prio110.q),
// to register interface (read)
.qs (prio110_qs)
@@ -14140,8 +14320,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio111 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio111_we),
@@ -14149,11 +14329,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio111.q ),
+ .q (reg2hw.prio111.q),
// to register interface (read)
.qs (prio111_qs)
@@ -14167,8 +14347,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio112 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio112_we),
@@ -14176,11 +14356,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio112.q ),
+ .q (reg2hw.prio112.q),
// to register interface (read)
.qs (prio112_qs)
@@ -14194,8 +14374,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio113 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio113_we),
@@ -14203,11 +14383,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio113.q ),
+ .q (reg2hw.prio113.q),
// to register interface (read)
.qs (prio113_qs)
@@ -14221,8 +14401,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio114 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio114_we),
@@ -14230,11 +14410,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio114.q ),
+ .q (reg2hw.prio114.q),
// to register interface (read)
.qs (prio114_qs)
@@ -14248,8 +14428,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio115 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio115_we),
@@ -14257,11 +14437,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio115.q ),
+ .q (reg2hw.prio115.q),
// to register interface (read)
.qs (prio115_qs)
@@ -14275,8 +14455,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio116 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio116_we),
@@ -14284,11 +14464,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio116.q ),
+ .q (reg2hw.prio116.q),
// to register interface (read)
.qs (prio116_qs)
@@ -14302,8 +14482,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio117 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio117_we),
@@ -14311,11 +14491,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio117.q ),
+ .q (reg2hw.prio117.q),
// to register interface (read)
.qs (prio117_qs)
@@ -14329,8 +14509,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio118 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio118_we),
@@ -14338,11 +14518,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio118.q ),
+ .q (reg2hw.prio118.q),
// to register interface (read)
.qs (prio118_qs)
@@ -14356,8 +14536,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio119 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio119_we),
@@ -14365,11 +14545,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio119.q ),
+ .q (reg2hw.prio119.q),
// to register interface (read)
.qs (prio119_qs)
@@ -14383,8 +14563,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio120 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio120_we),
@@ -14392,11 +14572,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio120.q ),
+ .q (reg2hw.prio120.q),
// to register interface (read)
.qs (prio120_qs)
@@ -14410,8 +14590,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio121 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio121_we),
@@ -14419,11 +14599,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio121.q ),
+ .q (reg2hw.prio121.q),
// to register interface (read)
.qs (prio121_qs)
@@ -14437,8 +14617,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio122 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio122_we),
@@ -14446,11 +14626,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio122.q ),
+ .q (reg2hw.prio122.q),
// to register interface (read)
.qs (prio122_qs)
@@ -14464,8 +14644,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio123 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio123_we),
@@ -14473,11 +14653,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio123.q ),
+ .q (reg2hw.prio123.q),
// to register interface (read)
.qs (prio123_qs)
@@ -14491,8 +14671,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio124 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio124_we),
@@ -14500,11 +14680,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio124.q ),
+ .q (reg2hw.prio124.q),
// to register interface (read)
.qs (prio124_qs)
@@ -14518,8 +14698,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio125 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio125_we),
@@ -14527,11 +14707,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio125.q ),
+ .q (reg2hw.prio125.q),
// to register interface (read)
.qs (prio125_qs)
@@ -14545,8 +14725,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio126 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio126_we),
@@ -14554,11 +14734,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio126.q ),
+ .q (reg2hw.prio126.q),
// to register interface (read)
.qs (prio126_qs)
@@ -14572,8 +14752,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio127 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio127_we),
@@ -14581,11 +14761,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio127.q ),
+ .q (reg2hw.prio127.q),
// to register interface (read)
.qs (prio127_qs)
@@ -14599,8 +14779,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio128 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio128_we),
@@ -14608,11 +14788,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio128.q ),
+ .q (reg2hw.prio128.q),
// to register interface (read)
.qs (prio128_qs)
@@ -14626,8 +14806,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio129 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio129_we),
@@ -14635,11 +14815,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio129.q ),
+ .q (reg2hw.prio129.q),
// to register interface (read)
.qs (prio129_qs)
@@ -14653,8 +14833,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio130 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio130_we),
@@ -14662,11 +14842,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio130.q ),
+ .q (reg2hw.prio130.q),
// to register interface (read)
.qs (prio130_qs)
@@ -14680,8 +14860,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio131 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio131_we),
@@ -14689,11 +14869,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio131.q ),
+ .q (reg2hw.prio131.q),
// to register interface (read)
.qs (prio131_qs)
@@ -14707,8 +14887,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio132 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio132_we),
@@ -14716,11 +14896,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio132.q ),
+ .q (reg2hw.prio132.q),
// to register interface (read)
.qs (prio132_qs)
@@ -14734,8 +14914,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio133 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio133_we),
@@ -14743,11 +14923,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio133.q ),
+ .q (reg2hw.prio133.q),
// to register interface (read)
.qs (prio133_qs)
@@ -14761,8 +14941,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio134 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio134_we),
@@ -14770,11 +14950,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio134.q ),
+ .q (reg2hw.prio134.q),
// to register interface (read)
.qs (prio134_qs)
@@ -14788,8 +14968,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio135 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio135_we),
@@ -14797,11 +14977,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio135.q ),
+ .q (reg2hw.prio135.q),
// to register interface (read)
.qs (prio135_qs)
@@ -14815,8 +14995,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio136 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio136_we),
@@ -14824,11 +15004,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio136.q ),
+ .q (reg2hw.prio136.q),
// to register interface (read)
.qs (prio136_qs)
@@ -14842,8 +15022,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio137 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio137_we),
@@ -14851,11 +15031,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio137.q ),
+ .q (reg2hw.prio137.q),
// to register interface (read)
.qs (prio137_qs)
@@ -14869,8 +15049,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio138 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio138_we),
@@ -14878,11 +15058,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio138.q ),
+ .q (reg2hw.prio138.q),
// to register interface (read)
.qs (prio138_qs)
@@ -14896,8 +15076,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio139 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio139_we),
@@ -14905,11 +15085,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio139.q ),
+ .q (reg2hw.prio139.q),
// to register interface (read)
.qs (prio139_qs)
@@ -14923,8 +15103,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio140 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio140_we),
@@ -14932,11 +15112,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio140.q ),
+ .q (reg2hw.prio140.q),
// to register interface (read)
.qs (prio140_qs)
@@ -14950,8 +15130,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio141 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio141_we),
@@ -14959,11 +15139,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio141.q ),
+ .q (reg2hw.prio141.q),
// to register interface (read)
.qs (prio141_qs)
@@ -14977,8 +15157,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio142 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio142_we),
@@ -14986,11 +15166,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio142.q ),
+ .q (reg2hw.prio142.q),
// to register interface (read)
.qs (prio142_qs)
@@ -15004,8 +15184,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio143 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio143_we),
@@ -15013,11 +15193,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio143.q ),
+ .q (reg2hw.prio143.q),
// to register interface (read)
.qs (prio143_qs)
@@ -15031,8 +15211,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio144 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio144_we),
@@ -15040,11 +15220,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio144.q ),
+ .q (reg2hw.prio144.q),
// to register interface (read)
.qs (prio144_qs)
@@ -15058,8 +15238,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio145 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio145_we),
@@ -15067,11 +15247,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio145.q ),
+ .q (reg2hw.prio145.q),
// to register interface (read)
.qs (prio145_qs)
@@ -15085,8 +15265,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio146 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio146_we),
@@ -15094,11 +15274,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio146.q ),
+ .q (reg2hw.prio146.q),
// to register interface (read)
.qs (prio146_qs)
@@ -15112,8 +15292,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio147 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio147_we),
@@ -15121,11 +15301,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio147.q ),
+ .q (reg2hw.prio147.q),
// to register interface (read)
.qs (prio147_qs)
@@ -15139,8 +15319,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio148 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio148_we),
@@ -15148,11 +15328,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio148.q ),
+ .q (reg2hw.prio148.q),
// to register interface (read)
.qs (prio148_qs)
@@ -15166,8 +15346,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio149 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio149_we),
@@ -15175,11 +15355,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio149.q ),
+ .q (reg2hw.prio149.q),
// to register interface (read)
.qs (prio149_qs)
@@ -15193,8 +15373,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio150 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio150_we),
@@ -15202,11 +15382,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio150.q ),
+ .q (reg2hw.prio150.q),
// to register interface (read)
.qs (prio150_qs)
@@ -15220,8 +15400,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio151 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio151_we),
@@ -15229,11 +15409,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio151.q ),
+ .q (reg2hw.prio151.q),
// to register interface (read)
.qs (prio151_qs)
@@ -15247,8 +15427,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio152 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio152_we),
@@ -15256,11 +15436,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio152.q ),
+ .q (reg2hw.prio152.q),
// to register interface (read)
.qs (prio152_qs)
@@ -15274,8 +15454,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio153 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio153_we),
@@ -15283,11 +15463,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio153.q ),
+ .q (reg2hw.prio153.q),
// to register interface (read)
.qs (prio153_qs)
@@ -15301,8 +15481,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio154 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio154_we),
@@ -15310,11 +15490,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio154.q ),
+ .q (reg2hw.prio154.q),
// to register interface (read)
.qs (prio154_qs)
@@ -15328,8 +15508,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio155 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio155_we),
@@ -15337,11 +15517,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio155.q ),
+ .q (reg2hw.prio155.q),
// to register interface (read)
.qs (prio155_qs)
@@ -15355,8 +15535,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio156 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio156_we),
@@ -15364,11 +15544,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio156.q ),
+ .q (reg2hw.prio156.q),
// to register interface (read)
.qs (prio156_qs)
@@ -15382,8 +15562,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio157 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio157_we),
@@ -15391,11 +15571,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio157.q ),
+ .q (reg2hw.prio157.q),
// to register interface (read)
.qs (prio157_qs)
@@ -15409,8 +15589,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio158 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio158_we),
@@ -15418,11 +15598,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio158.q ),
+ .q (reg2hw.prio158.q),
// to register interface (read)
.qs (prio158_qs)
@@ -15436,8 +15616,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio159 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio159_we),
@@ -15445,11 +15625,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio159.q ),
+ .q (reg2hw.prio159.q),
// to register interface (read)
.qs (prio159_qs)
@@ -15463,8 +15643,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio160 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio160_we),
@@ -15472,11 +15652,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio160.q ),
+ .q (reg2hw.prio160.q),
// to register interface (read)
.qs (prio160_qs)
@@ -15490,8 +15670,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio161 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio161_we),
@@ -15499,11 +15679,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio161.q ),
+ .q (reg2hw.prio161.q),
// to register interface (read)
.qs (prio161_qs)
@@ -15517,8 +15697,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio162 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio162_we),
@@ -15526,11 +15706,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio162.q ),
+ .q (reg2hw.prio162.q),
// to register interface (read)
.qs (prio162_qs)
@@ -15544,8 +15724,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio163 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio163_we),
@@ -15553,11 +15733,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio163.q ),
+ .q (reg2hw.prio163.q),
// to register interface (read)
.qs (prio163_qs)
@@ -15571,8 +15751,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio164 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio164_we),
@@ -15580,11 +15760,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio164.q ),
+ .q (reg2hw.prio164.q),
// to register interface (read)
.qs (prio164_qs)
@@ -15598,8 +15778,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio165 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio165_we),
@@ -15607,11 +15787,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio165.q ),
+ .q (reg2hw.prio165.q),
// to register interface (read)
.qs (prio165_qs)
@@ -15625,8 +15805,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio166 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio166_we),
@@ -15634,11 +15814,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio166.q ),
+ .q (reg2hw.prio166.q),
// to register interface (read)
.qs (prio166_qs)
@@ -15652,8 +15832,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio167 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio167_we),
@@ -15661,11 +15841,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio167.q ),
+ .q (reg2hw.prio167.q),
// to register interface (read)
.qs (prio167_qs)
@@ -15679,8 +15859,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio168 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio168_we),
@@ -15688,11 +15868,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio168.q ),
+ .q (reg2hw.prio168.q),
// to register interface (read)
.qs (prio168_qs)
@@ -15706,8 +15886,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio169 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio169_we),
@@ -15715,11 +15895,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio169.q ),
+ .q (reg2hw.prio169.q),
// to register interface (read)
.qs (prio169_qs)
@@ -15733,8 +15913,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio170 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio170_we),
@@ -15742,11 +15922,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio170.q ),
+ .q (reg2hw.prio170.q),
// to register interface (read)
.qs (prio170_qs)
@@ -15760,8 +15940,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio171 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio171_we),
@@ -15769,11 +15949,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio171.q ),
+ .q (reg2hw.prio171.q),
// to register interface (read)
.qs (prio171_qs)
@@ -15787,8 +15967,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio172 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio172_we),
@@ -15796,11 +15976,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio172.q ),
+ .q (reg2hw.prio172.q),
// to register interface (read)
.qs (prio172_qs)
@@ -15814,8 +15994,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio173 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio173_we),
@@ -15823,11 +16003,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio173.q ),
+ .q (reg2hw.prio173.q),
// to register interface (read)
.qs (prio173_qs)
@@ -15841,8 +16021,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio174 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio174_we),
@@ -15850,11 +16030,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio174.q ),
+ .q (reg2hw.prio174.q),
// to register interface (read)
.qs (prio174_qs)
@@ -15868,8 +16048,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio175 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio175_we),
@@ -15877,11 +16057,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio175.q ),
+ .q (reg2hw.prio175.q),
// to register interface (read)
.qs (prio175_qs)
@@ -15895,8 +16075,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio176 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio176_we),
@@ -15904,11 +16084,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio176.q ),
+ .q (reg2hw.prio176.q),
// to register interface (read)
.qs (prio176_qs)
@@ -15922,8 +16102,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio177 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio177_we),
@@ -15931,11 +16111,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio177.q ),
+ .q (reg2hw.prio177.q),
// to register interface (read)
.qs (prio177_qs)
@@ -15949,8 +16129,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio178 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio178_we),
@@ -15958,11 +16138,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio178.q ),
+ .q (reg2hw.prio178.q),
// to register interface (read)
.qs (prio178_qs)
@@ -15976,8 +16156,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_prio179 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (prio179_we),
@@ -15985,11 +16165,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.prio179.q ),
+ .q (reg2hw.prio179.q),
// to register interface (read)
.qs (prio179_qs)
@@ -16006,8 +16186,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_0_we),
@@ -16015,11 +16195,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[0].q ),
+ .q (reg2hw.ie0[0].q),
// to register interface (read)
.qs (ie0_0_e_0_qs)
@@ -16032,8 +16212,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_1_we),
@@ -16041,11 +16221,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[1].q ),
+ .q (reg2hw.ie0[1].q),
// to register interface (read)
.qs (ie0_0_e_1_qs)
@@ -16058,8 +16238,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_2_we),
@@ -16067,11 +16247,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[2].q ),
+ .q (reg2hw.ie0[2].q),
// to register interface (read)
.qs (ie0_0_e_2_qs)
@@ -16084,8 +16264,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_3_we),
@@ -16093,11 +16273,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[3].q ),
+ .q (reg2hw.ie0[3].q),
// to register interface (read)
.qs (ie0_0_e_3_qs)
@@ -16110,8 +16290,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_4_we),
@@ -16119,11 +16299,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[4].q ),
+ .q (reg2hw.ie0[4].q),
// to register interface (read)
.qs (ie0_0_e_4_qs)
@@ -16136,8 +16316,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_5_we),
@@ -16145,11 +16325,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[5].q ),
+ .q (reg2hw.ie0[5].q),
// to register interface (read)
.qs (ie0_0_e_5_qs)
@@ -16162,8 +16342,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_6_we),
@@ -16171,11 +16351,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[6].q ),
+ .q (reg2hw.ie0[6].q),
// to register interface (read)
.qs (ie0_0_e_6_qs)
@@ -16188,8 +16368,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_7_we),
@@ -16197,11 +16377,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[7].q ),
+ .q (reg2hw.ie0[7].q),
// to register interface (read)
.qs (ie0_0_e_7_qs)
@@ -16214,8 +16394,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_8_we),
@@ -16223,11 +16403,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[8].q ),
+ .q (reg2hw.ie0[8].q),
// to register interface (read)
.qs (ie0_0_e_8_qs)
@@ -16240,8 +16420,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_9_we),
@@ -16249,11 +16429,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[9].q ),
+ .q (reg2hw.ie0[9].q),
// to register interface (read)
.qs (ie0_0_e_9_qs)
@@ -16266,8 +16446,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_10_we),
@@ -16275,11 +16455,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[10].q ),
+ .q (reg2hw.ie0[10].q),
// to register interface (read)
.qs (ie0_0_e_10_qs)
@@ -16292,8 +16472,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_11 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_11_we),
@@ -16301,11 +16481,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[11].q ),
+ .q (reg2hw.ie0[11].q),
// to register interface (read)
.qs (ie0_0_e_11_qs)
@@ -16318,8 +16498,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_12 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_12_we),
@@ -16327,11 +16507,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[12].q ),
+ .q (reg2hw.ie0[12].q),
// to register interface (read)
.qs (ie0_0_e_12_qs)
@@ -16344,8 +16524,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_13 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_13_we),
@@ -16353,11 +16533,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[13].q ),
+ .q (reg2hw.ie0[13].q),
// to register interface (read)
.qs (ie0_0_e_13_qs)
@@ -16370,8 +16550,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_14 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_14_we),
@@ -16379,11 +16559,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[14].q ),
+ .q (reg2hw.ie0[14].q),
// to register interface (read)
.qs (ie0_0_e_14_qs)
@@ -16396,8 +16576,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_15 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_15_we),
@@ -16405,11 +16585,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[15].q ),
+ .q (reg2hw.ie0[15].q),
// to register interface (read)
.qs (ie0_0_e_15_qs)
@@ -16422,8 +16602,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_16 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_16_we),
@@ -16431,11 +16611,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[16].q ),
+ .q (reg2hw.ie0[16].q),
// to register interface (read)
.qs (ie0_0_e_16_qs)
@@ -16448,8 +16628,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_17 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_17_we),
@@ -16457,11 +16637,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[17].q ),
+ .q (reg2hw.ie0[17].q),
// to register interface (read)
.qs (ie0_0_e_17_qs)
@@ -16474,8 +16654,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_18 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_18_we),
@@ -16483,11 +16663,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[18].q ),
+ .q (reg2hw.ie0[18].q),
// to register interface (read)
.qs (ie0_0_e_18_qs)
@@ -16500,8 +16680,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_19 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_19_we),
@@ -16509,11 +16689,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[19].q ),
+ .q (reg2hw.ie0[19].q),
// to register interface (read)
.qs (ie0_0_e_19_qs)
@@ -16526,8 +16706,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_20 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_20_we),
@@ -16535,11 +16715,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[20].q ),
+ .q (reg2hw.ie0[20].q),
// to register interface (read)
.qs (ie0_0_e_20_qs)
@@ -16552,8 +16732,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_21 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_21_we),
@@ -16561,11 +16741,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[21].q ),
+ .q (reg2hw.ie0[21].q),
// to register interface (read)
.qs (ie0_0_e_21_qs)
@@ -16578,8 +16758,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_22 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_22_we),
@@ -16587,11 +16767,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[22].q ),
+ .q (reg2hw.ie0[22].q),
// to register interface (read)
.qs (ie0_0_e_22_qs)
@@ -16604,8 +16784,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_23 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_23_we),
@@ -16613,11 +16793,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[23].q ),
+ .q (reg2hw.ie0[23].q),
// to register interface (read)
.qs (ie0_0_e_23_qs)
@@ -16630,8 +16810,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_24 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_24_we),
@@ -16639,11 +16819,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[24].q ),
+ .q (reg2hw.ie0[24].q),
// to register interface (read)
.qs (ie0_0_e_24_qs)
@@ -16656,8 +16836,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_25 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_25_we),
@@ -16665,11 +16845,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[25].q ),
+ .q (reg2hw.ie0[25].q),
// to register interface (read)
.qs (ie0_0_e_25_qs)
@@ -16682,8 +16862,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_26 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_26_we),
@@ -16691,11 +16871,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[26].q ),
+ .q (reg2hw.ie0[26].q),
// to register interface (read)
.qs (ie0_0_e_26_qs)
@@ -16708,8 +16888,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_27 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_27_we),
@@ -16717,11 +16897,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[27].q ),
+ .q (reg2hw.ie0[27].q),
// to register interface (read)
.qs (ie0_0_e_27_qs)
@@ -16734,8 +16914,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_28 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_28_we),
@@ -16743,11 +16923,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[28].q ),
+ .q (reg2hw.ie0[28].q),
// to register interface (read)
.qs (ie0_0_e_28_qs)
@@ -16760,8 +16940,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_29 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_29_we),
@@ -16769,11 +16949,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[29].q ),
+ .q (reg2hw.ie0[29].q),
// to register interface (read)
.qs (ie0_0_e_29_qs)
@@ -16786,8 +16966,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_30 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_30_we),
@@ -16795,11 +16975,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[30].q ),
+ .q (reg2hw.ie0[30].q),
// to register interface (read)
.qs (ie0_0_e_30_qs)
@@ -16812,8 +16992,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_0_e_31 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_0_e_31_we),
@@ -16821,11 +17001,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[31].q ),
+ .q (reg2hw.ie0[31].q),
// to register interface (read)
.qs (ie0_0_e_31_qs)
@@ -16841,8 +17021,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_32 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_32_we),
@@ -16850,11 +17030,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[32].q ),
+ .q (reg2hw.ie0[32].q),
// to register interface (read)
.qs (ie0_1_e_32_qs)
@@ -16867,8 +17047,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_33 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_33_we),
@@ -16876,11 +17056,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[33].q ),
+ .q (reg2hw.ie0[33].q),
// to register interface (read)
.qs (ie0_1_e_33_qs)
@@ -16893,8 +17073,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_34 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_34_we),
@@ -16902,11 +17082,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[34].q ),
+ .q (reg2hw.ie0[34].q),
// to register interface (read)
.qs (ie0_1_e_34_qs)
@@ -16919,8 +17099,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_35 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_35_we),
@@ -16928,11 +17108,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[35].q ),
+ .q (reg2hw.ie0[35].q),
// to register interface (read)
.qs (ie0_1_e_35_qs)
@@ -16945,8 +17125,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_36 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_36_we),
@@ -16954,11 +17134,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[36].q ),
+ .q (reg2hw.ie0[36].q),
// to register interface (read)
.qs (ie0_1_e_36_qs)
@@ -16971,8 +17151,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_37 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_37_we),
@@ -16980,11 +17160,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[37].q ),
+ .q (reg2hw.ie0[37].q),
// to register interface (read)
.qs (ie0_1_e_37_qs)
@@ -16997,8 +17177,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_38 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_38_we),
@@ -17006,11 +17186,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[38].q ),
+ .q (reg2hw.ie0[38].q),
// to register interface (read)
.qs (ie0_1_e_38_qs)
@@ -17023,8 +17203,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_39 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_39_we),
@@ -17032,11 +17212,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[39].q ),
+ .q (reg2hw.ie0[39].q),
// to register interface (read)
.qs (ie0_1_e_39_qs)
@@ -17049,8 +17229,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_40 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_40_we),
@@ -17058,11 +17238,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[40].q ),
+ .q (reg2hw.ie0[40].q),
// to register interface (read)
.qs (ie0_1_e_40_qs)
@@ -17075,8 +17255,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_41 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_41_we),
@@ -17084,11 +17264,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[41].q ),
+ .q (reg2hw.ie0[41].q),
// to register interface (read)
.qs (ie0_1_e_41_qs)
@@ -17101,8 +17281,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_42 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_42_we),
@@ -17110,11 +17290,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[42].q ),
+ .q (reg2hw.ie0[42].q),
// to register interface (read)
.qs (ie0_1_e_42_qs)
@@ -17127,8 +17307,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_43 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_43_we),
@@ -17136,11 +17316,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[43].q ),
+ .q (reg2hw.ie0[43].q),
// to register interface (read)
.qs (ie0_1_e_43_qs)
@@ -17153,8 +17333,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_44 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_44_we),
@@ -17162,11 +17342,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[44].q ),
+ .q (reg2hw.ie0[44].q),
// to register interface (read)
.qs (ie0_1_e_44_qs)
@@ -17179,8 +17359,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_45 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_45_we),
@@ -17188,11 +17368,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[45].q ),
+ .q (reg2hw.ie0[45].q),
// to register interface (read)
.qs (ie0_1_e_45_qs)
@@ -17205,8 +17385,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_46 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_46_we),
@@ -17214,11 +17394,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[46].q ),
+ .q (reg2hw.ie0[46].q),
// to register interface (read)
.qs (ie0_1_e_46_qs)
@@ -17231,8 +17411,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_47 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_47_we),
@@ -17240,11 +17420,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[47].q ),
+ .q (reg2hw.ie0[47].q),
// to register interface (read)
.qs (ie0_1_e_47_qs)
@@ -17257,8 +17437,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_48 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_48_we),
@@ -17266,11 +17446,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[48].q ),
+ .q (reg2hw.ie0[48].q),
// to register interface (read)
.qs (ie0_1_e_48_qs)
@@ -17283,8 +17463,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_49 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_49_we),
@@ -17292,11 +17472,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[49].q ),
+ .q (reg2hw.ie0[49].q),
// to register interface (read)
.qs (ie0_1_e_49_qs)
@@ -17309,8 +17489,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_50 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_50_we),
@@ -17318,11 +17498,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[50].q ),
+ .q (reg2hw.ie0[50].q),
// to register interface (read)
.qs (ie0_1_e_50_qs)
@@ -17335,8 +17515,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_51 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_51_we),
@@ -17344,11 +17524,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[51].q ),
+ .q (reg2hw.ie0[51].q),
// to register interface (read)
.qs (ie0_1_e_51_qs)
@@ -17361,8 +17541,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_52_we),
@@ -17370,11 +17550,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[52].q ),
+ .q (reg2hw.ie0[52].q),
// to register interface (read)
.qs (ie0_1_e_52_qs)
@@ -17387,8 +17567,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_53_we),
@@ -17396,11 +17576,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[53].q ),
+ .q (reg2hw.ie0[53].q),
// to register interface (read)
.qs (ie0_1_e_53_qs)
@@ -17413,8 +17593,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_54 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_54_we),
@@ -17422,11 +17602,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[54].q ),
+ .q (reg2hw.ie0[54].q),
// to register interface (read)
.qs (ie0_1_e_54_qs)
@@ -17439,8 +17619,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_55 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_55_we),
@@ -17448,11 +17628,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[55].q ),
+ .q (reg2hw.ie0[55].q),
// to register interface (read)
.qs (ie0_1_e_55_qs)
@@ -17465,8 +17645,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_56 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_56_we),
@@ -17474,11 +17654,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[56].q ),
+ .q (reg2hw.ie0[56].q),
// to register interface (read)
.qs (ie0_1_e_56_qs)
@@ -17491,8 +17671,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_57 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_57_we),
@@ -17500,11 +17680,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[57].q ),
+ .q (reg2hw.ie0[57].q),
// to register interface (read)
.qs (ie0_1_e_57_qs)
@@ -17517,8 +17697,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_58 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_58_we),
@@ -17526,11 +17706,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[58].q ),
+ .q (reg2hw.ie0[58].q),
// to register interface (read)
.qs (ie0_1_e_58_qs)
@@ -17543,8 +17723,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_59 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_59_we),
@@ -17552,11 +17732,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[59].q ),
+ .q (reg2hw.ie0[59].q),
// to register interface (read)
.qs (ie0_1_e_59_qs)
@@ -17569,8 +17749,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_60 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_60_we),
@@ -17578,11 +17758,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[60].q ),
+ .q (reg2hw.ie0[60].q),
// to register interface (read)
.qs (ie0_1_e_60_qs)
@@ -17595,8 +17775,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_61 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_61_we),
@@ -17604,11 +17784,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[61].q ),
+ .q (reg2hw.ie0[61].q),
// to register interface (read)
.qs (ie0_1_e_61_qs)
@@ -17621,8 +17801,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_62 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_62_we),
@@ -17630,11 +17810,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[62].q ),
+ .q (reg2hw.ie0[62].q),
// to register interface (read)
.qs (ie0_1_e_62_qs)
@@ -17647,8 +17827,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_1_e_63 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_1_e_63_we),
@@ -17656,11 +17836,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[63].q ),
+ .q (reg2hw.ie0[63].q),
// to register interface (read)
.qs (ie0_1_e_63_qs)
@@ -17676,8 +17856,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_64 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_64_we),
@@ -17685,11 +17865,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[64].q ),
+ .q (reg2hw.ie0[64].q),
// to register interface (read)
.qs (ie0_2_e_64_qs)
@@ -17702,8 +17882,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_65 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_65_we),
@@ -17711,11 +17891,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[65].q ),
+ .q (reg2hw.ie0[65].q),
// to register interface (read)
.qs (ie0_2_e_65_qs)
@@ -17728,8 +17908,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_66 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_66_we),
@@ -17737,11 +17917,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[66].q ),
+ .q (reg2hw.ie0[66].q),
// to register interface (read)
.qs (ie0_2_e_66_qs)
@@ -17754,8 +17934,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_67 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_67_we),
@@ -17763,11 +17943,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[67].q ),
+ .q (reg2hw.ie0[67].q),
// to register interface (read)
.qs (ie0_2_e_67_qs)
@@ -17780,8 +17960,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_68 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_68_we),
@@ -17789,11 +17969,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[68].q ),
+ .q (reg2hw.ie0[68].q),
// to register interface (read)
.qs (ie0_2_e_68_qs)
@@ -17806,8 +17986,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_69 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_69_we),
@@ -17815,11 +17995,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[69].q ),
+ .q (reg2hw.ie0[69].q),
// to register interface (read)
.qs (ie0_2_e_69_qs)
@@ -17832,8 +18012,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_70 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_70_we),
@@ -17841,11 +18021,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[70].q ),
+ .q (reg2hw.ie0[70].q),
// to register interface (read)
.qs (ie0_2_e_70_qs)
@@ -17858,8 +18038,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_71 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_71_we),
@@ -17867,11 +18047,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[71].q ),
+ .q (reg2hw.ie0[71].q),
// to register interface (read)
.qs (ie0_2_e_71_qs)
@@ -17884,8 +18064,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_72 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_72_we),
@@ -17893,11 +18073,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[72].q ),
+ .q (reg2hw.ie0[72].q),
// to register interface (read)
.qs (ie0_2_e_72_qs)
@@ -17910,8 +18090,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_73 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_73_we),
@@ -17919,11 +18099,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[73].q ),
+ .q (reg2hw.ie0[73].q),
// to register interface (read)
.qs (ie0_2_e_73_qs)
@@ -17936,8 +18116,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_74 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_74_we),
@@ -17945,11 +18125,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[74].q ),
+ .q (reg2hw.ie0[74].q),
// to register interface (read)
.qs (ie0_2_e_74_qs)
@@ -17962,8 +18142,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_75 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_75_we),
@@ -17971,11 +18151,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[75].q ),
+ .q (reg2hw.ie0[75].q),
// to register interface (read)
.qs (ie0_2_e_75_qs)
@@ -17988,8 +18168,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_76 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_76_we),
@@ -17997,11 +18177,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[76].q ),
+ .q (reg2hw.ie0[76].q),
// to register interface (read)
.qs (ie0_2_e_76_qs)
@@ -18014,8 +18194,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_77 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_77_we),
@@ -18023,11 +18203,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[77].q ),
+ .q (reg2hw.ie0[77].q),
// to register interface (read)
.qs (ie0_2_e_77_qs)
@@ -18040,8 +18220,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_78 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_78_we),
@@ -18049,11 +18229,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[78].q ),
+ .q (reg2hw.ie0[78].q),
// to register interface (read)
.qs (ie0_2_e_78_qs)
@@ -18066,8 +18246,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_79 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_79_we),
@@ -18075,11 +18255,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[79].q ),
+ .q (reg2hw.ie0[79].q),
// to register interface (read)
.qs (ie0_2_e_79_qs)
@@ -18092,8 +18272,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_80 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_80_we),
@@ -18101,11 +18281,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[80].q ),
+ .q (reg2hw.ie0[80].q),
// to register interface (read)
.qs (ie0_2_e_80_qs)
@@ -18118,8 +18298,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_81 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_81_we),
@@ -18127,11 +18307,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[81].q ),
+ .q (reg2hw.ie0[81].q),
// to register interface (read)
.qs (ie0_2_e_81_qs)
@@ -18144,8 +18324,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_82 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_82_we),
@@ -18153,11 +18333,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[82].q ),
+ .q (reg2hw.ie0[82].q),
// to register interface (read)
.qs (ie0_2_e_82_qs)
@@ -18170,8 +18350,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_83 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_83_we),
@@ -18179,11 +18359,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[83].q ),
+ .q (reg2hw.ie0[83].q),
// to register interface (read)
.qs (ie0_2_e_83_qs)
@@ -18196,8 +18376,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_84 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_84_we),
@@ -18205,11 +18385,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[84].q ),
+ .q (reg2hw.ie0[84].q),
// to register interface (read)
.qs (ie0_2_e_84_qs)
@@ -18222,8 +18402,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_85 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_85_we),
@@ -18231,11 +18411,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[85].q ),
+ .q (reg2hw.ie0[85].q),
// to register interface (read)
.qs (ie0_2_e_85_qs)
@@ -18248,8 +18428,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_86 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_86_we),
@@ -18257,11 +18437,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[86].q ),
+ .q (reg2hw.ie0[86].q),
// to register interface (read)
.qs (ie0_2_e_86_qs)
@@ -18274,8 +18454,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_87 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_87_we),
@@ -18283,11 +18463,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[87].q ),
+ .q (reg2hw.ie0[87].q),
// to register interface (read)
.qs (ie0_2_e_87_qs)
@@ -18300,8 +18480,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_88 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_88_we),
@@ -18309,11 +18489,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[88].q ),
+ .q (reg2hw.ie0[88].q),
// to register interface (read)
.qs (ie0_2_e_88_qs)
@@ -18326,8 +18506,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_89 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_89_we),
@@ -18335,11 +18515,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[89].q ),
+ .q (reg2hw.ie0[89].q),
// to register interface (read)
.qs (ie0_2_e_89_qs)
@@ -18352,8 +18532,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_90 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_90_we),
@@ -18361,11 +18541,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[90].q ),
+ .q (reg2hw.ie0[90].q),
// to register interface (read)
.qs (ie0_2_e_90_qs)
@@ -18378,8 +18558,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_91 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_91_we),
@@ -18387,11 +18567,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[91].q ),
+ .q (reg2hw.ie0[91].q),
// to register interface (read)
.qs (ie0_2_e_91_qs)
@@ -18404,8 +18584,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_92 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_92_we),
@@ -18413,11 +18593,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[92].q ),
+ .q (reg2hw.ie0[92].q),
// to register interface (read)
.qs (ie0_2_e_92_qs)
@@ -18430,8 +18610,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_93 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_93_we),
@@ -18439,11 +18619,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[93].q ),
+ .q (reg2hw.ie0[93].q),
// to register interface (read)
.qs (ie0_2_e_93_qs)
@@ -18456,8 +18636,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_94 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_94_we),
@@ -18465,11 +18645,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[94].q ),
+ .q (reg2hw.ie0[94].q),
// to register interface (read)
.qs (ie0_2_e_94_qs)
@@ -18482,8 +18662,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_2_e_95 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_2_e_95_we),
@@ -18491,11 +18671,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[95].q ),
+ .q (reg2hw.ie0[95].q),
// to register interface (read)
.qs (ie0_2_e_95_qs)
@@ -18511,8 +18691,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_96 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_96_we),
@@ -18520,11 +18700,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[96].q ),
+ .q (reg2hw.ie0[96].q),
// to register interface (read)
.qs (ie0_3_e_96_qs)
@@ -18537,8 +18717,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_97 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_97_we),
@@ -18546,11 +18726,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[97].q ),
+ .q (reg2hw.ie0[97].q),
// to register interface (read)
.qs (ie0_3_e_97_qs)
@@ -18563,8 +18743,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_98 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_98_we),
@@ -18572,11 +18752,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[98].q ),
+ .q (reg2hw.ie0[98].q),
// to register interface (read)
.qs (ie0_3_e_98_qs)
@@ -18589,8 +18769,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_99 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_99_we),
@@ -18598,11 +18778,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[99].q ),
+ .q (reg2hw.ie0[99].q),
// to register interface (read)
.qs (ie0_3_e_99_qs)
@@ -18615,8 +18795,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_100 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_100_we),
@@ -18624,11 +18804,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[100].q ),
+ .q (reg2hw.ie0[100].q),
// to register interface (read)
.qs (ie0_3_e_100_qs)
@@ -18641,8 +18821,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_101 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_101_we),
@@ -18650,11 +18830,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[101].q ),
+ .q (reg2hw.ie0[101].q),
// to register interface (read)
.qs (ie0_3_e_101_qs)
@@ -18667,8 +18847,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_102 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_102_we),
@@ -18676,11 +18856,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[102].q ),
+ .q (reg2hw.ie0[102].q),
// to register interface (read)
.qs (ie0_3_e_102_qs)
@@ -18693,8 +18873,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_103 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_103_we),
@@ -18702,11 +18882,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[103].q ),
+ .q (reg2hw.ie0[103].q),
// to register interface (read)
.qs (ie0_3_e_103_qs)
@@ -18719,8 +18899,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_104 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_104_we),
@@ -18728,11 +18908,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[104].q ),
+ .q (reg2hw.ie0[104].q),
// to register interface (read)
.qs (ie0_3_e_104_qs)
@@ -18745,8 +18925,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_105 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_105_we),
@@ -18754,11 +18934,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[105].q ),
+ .q (reg2hw.ie0[105].q),
// to register interface (read)
.qs (ie0_3_e_105_qs)
@@ -18771,8 +18951,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_106 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_106_we),
@@ -18780,11 +18960,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[106].q ),
+ .q (reg2hw.ie0[106].q),
// to register interface (read)
.qs (ie0_3_e_106_qs)
@@ -18797,8 +18977,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_107 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_107_we),
@@ -18806,11 +18986,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[107].q ),
+ .q (reg2hw.ie0[107].q),
// to register interface (read)
.qs (ie0_3_e_107_qs)
@@ -18823,8 +19003,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_108 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_108_we),
@@ -18832,11 +19012,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[108].q ),
+ .q (reg2hw.ie0[108].q),
// to register interface (read)
.qs (ie0_3_e_108_qs)
@@ -18849,8 +19029,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_109 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_109_we),
@@ -18858,11 +19038,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[109].q ),
+ .q (reg2hw.ie0[109].q),
// to register interface (read)
.qs (ie0_3_e_109_qs)
@@ -18875,8 +19055,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_110 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_110_we),
@@ -18884,11 +19064,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[110].q ),
+ .q (reg2hw.ie0[110].q),
// to register interface (read)
.qs (ie0_3_e_110_qs)
@@ -18901,8 +19081,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_111 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_111_we),
@@ -18910,11 +19090,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[111].q ),
+ .q (reg2hw.ie0[111].q),
// to register interface (read)
.qs (ie0_3_e_111_qs)
@@ -18927,8 +19107,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_112 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_112_we),
@@ -18936,11 +19116,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[112].q ),
+ .q (reg2hw.ie0[112].q),
// to register interface (read)
.qs (ie0_3_e_112_qs)
@@ -18953,8 +19133,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_113 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_113_we),
@@ -18962,11 +19142,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[113].q ),
+ .q (reg2hw.ie0[113].q),
// to register interface (read)
.qs (ie0_3_e_113_qs)
@@ -18979,8 +19159,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_114 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_114_we),
@@ -18988,11 +19168,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[114].q ),
+ .q (reg2hw.ie0[114].q),
// to register interface (read)
.qs (ie0_3_e_114_qs)
@@ -19005,8 +19185,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_115 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_115_we),
@@ -19014,11 +19194,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[115].q ),
+ .q (reg2hw.ie0[115].q),
// to register interface (read)
.qs (ie0_3_e_115_qs)
@@ -19031,8 +19211,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_116 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_116_we),
@@ -19040,11 +19220,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[116].q ),
+ .q (reg2hw.ie0[116].q),
// to register interface (read)
.qs (ie0_3_e_116_qs)
@@ -19057,8 +19237,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_117 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_117_we),
@@ -19066,11 +19246,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[117].q ),
+ .q (reg2hw.ie0[117].q),
// to register interface (read)
.qs (ie0_3_e_117_qs)
@@ -19083,8 +19263,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_118 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_118_we),
@@ -19092,11 +19272,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[118].q ),
+ .q (reg2hw.ie0[118].q),
// to register interface (read)
.qs (ie0_3_e_118_qs)
@@ -19109,8 +19289,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_119 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_119_we),
@@ -19118,11 +19298,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[119].q ),
+ .q (reg2hw.ie0[119].q),
// to register interface (read)
.qs (ie0_3_e_119_qs)
@@ -19135,8 +19315,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_120 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_120_we),
@@ -19144,11 +19324,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[120].q ),
+ .q (reg2hw.ie0[120].q),
// to register interface (read)
.qs (ie0_3_e_120_qs)
@@ -19161,8 +19341,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_121 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_121_we),
@@ -19170,11 +19350,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[121].q ),
+ .q (reg2hw.ie0[121].q),
// to register interface (read)
.qs (ie0_3_e_121_qs)
@@ -19187,8 +19367,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_122 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_122_we),
@@ -19196,11 +19376,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[122].q ),
+ .q (reg2hw.ie0[122].q),
// to register interface (read)
.qs (ie0_3_e_122_qs)
@@ -19213,8 +19393,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_123 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_123_we),
@@ -19222,11 +19402,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[123].q ),
+ .q (reg2hw.ie0[123].q),
// to register interface (read)
.qs (ie0_3_e_123_qs)
@@ -19239,8 +19419,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_124 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_124_we),
@@ -19248,11 +19428,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[124].q ),
+ .q (reg2hw.ie0[124].q),
// to register interface (read)
.qs (ie0_3_e_124_qs)
@@ -19265,8 +19445,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_125 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_125_we),
@@ -19274,11 +19454,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[125].q ),
+ .q (reg2hw.ie0[125].q),
// to register interface (read)
.qs (ie0_3_e_125_qs)
@@ -19291,8 +19471,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_126 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_126_we),
@@ -19300,11 +19480,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[126].q ),
+ .q (reg2hw.ie0[126].q),
// to register interface (read)
.qs (ie0_3_e_126_qs)
@@ -19317,8 +19497,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_3_e_127 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_3_e_127_we),
@@ -19326,11 +19506,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[127].q ),
+ .q (reg2hw.ie0[127].q),
// to register interface (read)
.qs (ie0_3_e_127_qs)
@@ -19346,8 +19526,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_128 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_128_we),
@@ -19355,11 +19535,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[128].q ),
+ .q (reg2hw.ie0[128].q),
// to register interface (read)
.qs (ie0_4_e_128_qs)
@@ -19372,8 +19552,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_129 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_129_we),
@@ -19381,11 +19561,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[129].q ),
+ .q (reg2hw.ie0[129].q),
// to register interface (read)
.qs (ie0_4_e_129_qs)
@@ -19398,8 +19578,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_130 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_130_we),
@@ -19407,11 +19587,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[130].q ),
+ .q (reg2hw.ie0[130].q),
// to register interface (read)
.qs (ie0_4_e_130_qs)
@@ -19424,8 +19604,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_131 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_131_we),
@@ -19433,11 +19613,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[131].q ),
+ .q (reg2hw.ie0[131].q),
// to register interface (read)
.qs (ie0_4_e_131_qs)
@@ -19450,8 +19630,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_132 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_132_we),
@@ -19459,11 +19639,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[132].q ),
+ .q (reg2hw.ie0[132].q),
// to register interface (read)
.qs (ie0_4_e_132_qs)
@@ -19476,8 +19656,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_133 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_133_we),
@@ -19485,11 +19665,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[133].q ),
+ .q (reg2hw.ie0[133].q),
// to register interface (read)
.qs (ie0_4_e_133_qs)
@@ -19502,8 +19682,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_134 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_134_we),
@@ -19511,11 +19691,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[134].q ),
+ .q (reg2hw.ie0[134].q),
// to register interface (read)
.qs (ie0_4_e_134_qs)
@@ -19528,8 +19708,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_135 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_135_we),
@@ -19537,11 +19717,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[135].q ),
+ .q (reg2hw.ie0[135].q),
// to register interface (read)
.qs (ie0_4_e_135_qs)
@@ -19554,8 +19734,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_136 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_136_we),
@@ -19563,11 +19743,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[136].q ),
+ .q (reg2hw.ie0[136].q),
// to register interface (read)
.qs (ie0_4_e_136_qs)
@@ -19580,8 +19760,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_137 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_137_we),
@@ -19589,11 +19769,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[137].q ),
+ .q (reg2hw.ie0[137].q),
// to register interface (read)
.qs (ie0_4_e_137_qs)
@@ -19606,8 +19786,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_138 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_138_we),
@@ -19615,11 +19795,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[138].q ),
+ .q (reg2hw.ie0[138].q),
// to register interface (read)
.qs (ie0_4_e_138_qs)
@@ -19632,8 +19812,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_139 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_139_we),
@@ -19641,11 +19821,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[139].q ),
+ .q (reg2hw.ie0[139].q),
// to register interface (read)
.qs (ie0_4_e_139_qs)
@@ -19658,8 +19838,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_140 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_140_we),
@@ -19667,11 +19847,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[140].q ),
+ .q (reg2hw.ie0[140].q),
// to register interface (read)
.qs (ie0_4_e_140_qs)
@@ -19684,8 +19864,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_141 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_141_we),
@@ -19693,11 +19873,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[141].q ),
+ .q (reg2hw.ie0[141].q),
// to register interface (read)
.qs (ie0_4_e_141_qs)
@@ -19710,8 +19890,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_142 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_142_we),
@@ -19719,11 +19899,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[142].q ),
+ .q (reg2hw.ie0[142].q),
// to register interface (read)
.qs (ie0_4_e_142_qs)
@@ -19736,8 +19916,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_143 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_143_we),
@@ -19745,11 +19925,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[143].q ),
+ .q (reg2hw.ie0[143].q),
// to register interface (read)
.qs (ie0_4_e_143_qs)
@@ -19762,8 +19942,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_144 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_144_we),
@@ -19771,11 +19951,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[144].q ),
+ .q (reg2hw.ie0[144].q),
// to register interface (read)
.qs (ie0_4_e_144_qs)
@@ -19788,8 +19968,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_145 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_145_we),
@@ -19797,11 +19977,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[145].q ),
+ .q (reg2hw.ie0[145].q),
// to register interface (read)
.qs (ie0_4_e_145_qs)
@@ -19814,8 +19994,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_146 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_146_we),
@@ -19823,11 +20003,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[146].q ),
+ .q (reg2hw.ie0[146].q),
// to register interface (read)
.qs (ie0_4_e_146_qs)
@@ -19840,8 +20020,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_147 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_147_we),
@@ -19849,11 +20029,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[147].q ),
+ .q (reg2hw.ie0[147].q),
// to register interface (read)
.qs (ie0_4_e_147_qs)
@@ -19866,8 +20046,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_148 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_148_we),
@@ -19875,11 +20055,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[148].q ),
+ .q (reg2hw.ie0[148].q),
// to register interface (read)
.qs (ie0_4_e_148_qs)
@@ -19892,8 +20072,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_149 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_149_we),
@@ -19901,11 +20081,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[149].q ),
+ .q (reg2hw.ie0[149].q),
// to register interface (read)
.qs (ie0_4_e_149_qs)
@@ -19918,8 +20098,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_150 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_150_we),
@@ -19927,11 +20107,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[150].q ),
+ .q (reg2hw.ie0[150].q),
// to register interface (read)
.qs (ie0_4_e_150_qs)
@@ -19944,8 +20124,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_151 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_151_we),
@@ -19953,11 +20133,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[151].q ),
+ .q (reg2hw.ie0[151].q),
// to register interface (read)
.qs (ie0_4_e_151_qs)
@@ -19970,8 +20150,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_152 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_152_we),
@@ -19979,11 +20159,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[152].q ),
+ .q (reg2hw.ie0[152].q),
// to register interface (read)
.qs (ie0_4_e_152_qs)
@@ -19996,8 +20176,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_153 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_153_we),
@@ -20005,11 +20185,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[153].q ),
+ .q (reg2hw.ie0[153].q),
// to register interface (read)
.qs (ie0_4_e_153_qs)
@@ -20022,8 +20202,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_154 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_154_we),
@@ -20031,11 +20211,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[154].q ),
+ .q (reg2hw.ie0[154].q),
// to register interface (read)
.qs (ie0_4_e_154_qs)
@@ -20048,8 +20228,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_155 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_155_we),
@@ -20057,11 +20237,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[155].q ),
+ .q (reg2hw.ie0[155].q),
// to register interface (read)
.qs (ie0_4_e_155_qs)
@@ -20074,8 +20254,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_156 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_156_we),
@@ -20083,11 +20263,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[156].q ),
+ .q (reg2hw.ie0[156].q),
// to register interface (read)
.qs (ie0_4_e_156_qs)
@@ -20100,8 +20280,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_157 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_157_we),
@@ -20109,11 +20289,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[157].q ),
+ .q (reg2hw.ie0[157].q),
// to register interface (read)
.qs (ie0_4_e_157_qs)
@@ -20126,8 +20306,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_158 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_158_we),
@@ -20135,11 +20315,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[158].q ),
+ .q (reg2hw.ie0[158].q),
// to register interface (read)
.qs (ie0_4_e_158_qs)
@@ -20152,8 +20332,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_4_e_159 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_4_e_159_we),
@@ -20161,11 +20341,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[159].q ),
+ .q (reg2hw.ie0[159].q),
// to register interface (read)
.qs (ie0_4_e_159_qs)
@@ -20181,8 +20361,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_160 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_160_we),
@@ -20190,11 +20370,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[160].q ),
+ .q (reg2hw.ie0[160].q),
// to register interface (read)
.qs (ie0_5_e_160_qs)
@@ -20207,8 +20387,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_161 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_161_we),
@@ -20216,11 +20396,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[161].q ),
+ .q (reg2hw.ie0[161].q),
// to register interface (read)
.qs (ie0_5_e_161_qs)
@@ -20233,8 +20413,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_162 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_162_we),
@@ -20242,11 +20422,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[162].q ),
+ .q (reg2hw.ie0[162].q),
// to register interface (read)
.qs (ie0_5_e_162_qs)
@@ -20259,8 +20439,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_163 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_163_we),
@@ -20268,11 +20448,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[163].q ),
+ .q (reg2hw.ie0[163].q),
// to register interface (read)
.qs (ie0_5_e_163_qs)
@@ -20285,8 +20465,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_164 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_164_we),
@@ -20294,11 +20474,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[164].q ),
+ .q (reg2hw.ie0[164].q),
// to register interface (read)
.qs (ie0_5_e_164_qs)
@@ -20311,8 +20491,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_165 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_165_we),
@@ -20320,11 +20500,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[165].q ),
+ .q (reg2hw.ie0[165].q),
// to register interface (read)
.qs (ie0_5_e_165_qs)
@@ -20337,8 +20517,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_166 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_166_we),
@@ -20346,11 +20526,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[166].q ),
+ .q (reg2hw.ie0[166].q),
// to register interface (read)
.qs (ie0_5_e_166_qs)
@@ -20363,8 +20543,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_167 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_167_we),
@@ -20372,11 +20552,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[167].q ),
+ .q (reg2hw.ie0[167].q),
// to register interface (read)
.qs (ie0_5_e_167_qs)
@@ -20389,8 +20569,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_168 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_168_we),
@@ -20398,11 +20578,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[168].q ),
+ .q (reg2hw.ie0[168].q),
// to register interface (read)
.qs (ie0_5_e_168_qs)
@@ -20415,8 +20595,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_169 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_169_we),
@@ -20424,11 +20604,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[169].q ),
+ .q (reg2hw.ie0[169].q),
// to register interface (read)
.qs (ie0_5_e_169_qs)
@@ -20441,8 +20621,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_170 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_170_we),
@@ -20450,11 +20630,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[170].q ),
+ .q (reg2hw.ie0[170].q),
// to register interface (read)
.qs (ie0_5_e_170_qs)
@@ -20467,8 +20647,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_171 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_171_we),
@@ -20476,11 +20656,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[171].q ),
+ .q (reg2hw.ie0[171].q),
// to register interface (read)
.qs (ie0_5_e_171_qs)
@@ -20493,8 +20673,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_172 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_172_we),
@@ -20502,11 +20682,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[172].q ),
+ .q (reg2hw.ie0[172].q),
// to register interface (read)
.qs (ie0_5_e_172_qs)
@@ -20519,8 +20699,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_173 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_173_we),
@@ -20528,11 +20708,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[173].q ),
+ .q (reg2hw.ie0[173].q),
// to register interface (read)
.qs (ie0_5_e_173_qs)
@@ -20545,8 +20725,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_174 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_174_we),
@@ -20554,11 +20734,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[174].q ),
+ .q (reg2hw.ie0[174].q),
// to register interface (read)
.qs (ie0_5_e_174_qs)
@@ -20571,8 +20751,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_175 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_175_we),
@@ -20580,11 +20760,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[175].q ),
+ .q (reg2hw.ie0[175].q),
// to register interface (read)
.qs (ie0_5_e_175_qs)
@@ -20597,8 +20777,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_176 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_176_we),
@@ -20606,11 +20786,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[176].q ),
+ .q (reg2hw.ie0[176].q),
// to register interface (read)
.qs (ie0_5_e_176_qs)
@@ -20623,8 +20803,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_177 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_177_we),
@@ -20632,11 +20812,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[177].q ),
+ .q (reg2hw.ie0[177].q),
// to register interface (read)
.qs (ie0_5_e_177_qs)
@@ -20649,8 +20829,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_178 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_178_we),
@@ -20658,11 +20838,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[178].q ),
+ .q (reg2hw.ie0[178].q),
// to register interface (read)
.qs (ie0_5_e_178_qs)
@@ -20675,8 +20855,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_ie0_5_e_179 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (ie0_5_e_179_we),
@@ -20684,11 +20864,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ie0[179].q ),
+ .q (reg2hw.ie0[179].q),
// to register interface (read)
.qs (ie0_5_e_179_qs)
@@ -20703,8 +20883,8 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_threshold0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (threshold0_we),
@@ -20712,11 +20892,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.threshold0.q ),
+ .q (reg2hw.threshold0.q),
// to register interface (read)
.qs (threshold0_qs)
@@ -20734,7 +20914,7 @@
.d (hw2reg.cc0.d),
.qre (reg2hw.cc0.re),
.qe (reg2hw.cc0.qe),
- .q (reg2hw.cc0.q ),
+ .q (reg2hw.cc0.q),
.qs (cc0_qs)
);
@@ -20746,8 +20926,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_msip0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (msip0_we),
@@ -20755,11 +20935,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.msip0.q ),
+ .q (reg2hw.msip0.q),
// to register interface (read)
.qs (msip0_qs)
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
index 8716401..5fafe39 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
@@ -244,7 +244,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_as.qe),
- .q (reg2hw.alert_test.recov_as.q ),
+ .q (reg2hw.alert_test.recov_as.q),
.qs ()
);
@@ -259,7 +259,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_cg.qe),
- .q (reg2hw.alert_test.recov_cg.q ),
+ .q (reg2hw.alert_test.recov_cg.q),
.qs ()
);
@@ -274,7 +274,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_gd.qe),
- .q (reg2hw.alert_test.recov_gd.q ),
+ .q (reg2hw.alert_test.recov_gd.q),
.qs ()
);
@@ -289,7 +289,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_ts_hi.qe),
- .q (reg2hw.alert_test.recov_ts_hi.q ),
+ .q (reg2hw.alert_test.recov_ts_hi.q),
.qs ()
);
@@ -304,7 +304,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_ts_lo.qe),
- .q (reg2hw.alert_test.recov_ts_lo.q ),
+ .q (reg2hw.alert_test.recov_ts_lo.q),
.qs ()
);
@@ -319,7 +319,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_fla.qe),
- .q (reg2hw.alert_test.recov_fla.q ),
+ .q (reg2hw.alert_test.recov_fla.q),
.qs ()
);
@@ -334,7 +334,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_otp.qe),
- .q (reg2hw.alert_test.recov_otp.q ),
+ .q (reg2hw.alert_test.recov_otp.q),
.qs ()
);
@@ -349,7 +349,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_ot0.qe),
- .q (reg2hw.alert_test.recov_ot0.q ),
+ .q (reg2hw.alert_test.recov_ot0.q),
.qs ()
);
@@ -364,7 +364,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_ot1.qe),
- .q (reg2hw.alert_test.recov_ot1.q ),
+ .q (reg2hw.alert_test.recov_ot1.q),
.qs ()
);
@@ -379,7 +379,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_ot2.qe),
- .q (reg2hw.alert_test.recov_ot2.q ),
+ .q (reg2hw.alert_test.recov_ot2.q),
.qs ()
);
@@ -394,7 +394,7 @@
.d ('0),
.qre (),
.qe (reg2hw.alert_test.recov_ot3.qe),
- .q (reg2hw.alert_test.recov_ot3.q ),
+ .q (reg2hw.alert_test.recov_ot3.q),
.qs ()
);
@@ -406,8 +406,8 @@
.SWACCESS("W0C"),
.RESVAL (1'h1)
) u_cfg_regwen (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (cfg_regwen_we),
@@ -415,7 +415,7 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
@@ -436,20 +436,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_0_we & cfg_regwen_qs),
.wd (ack_mode_val_0_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[0].q ),
+ .q (reg2hw.ack_mode[0].q),
// to register interface (read)
.qs (ack_mode_val_0_qs)
@@ -462,20 +462,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_1_we & cfg_regwen_qs),
.wd (ack_mode_val_1_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[1].q ),
+ .q (reg2hw.ack_mode[1].q),
// to register interface (read)
.qs (ack_mode_val_1_qs)
@@ -488,20 +488,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_2_we & cfg_regwen_qs),
.wd (ack_mode_val_2_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[2].q ),
+ .q (reg2hw.ack_mode[2].q),
// to register interface (read)
.qs (ack_mode_val_2_qs)
@@ -514,20 +514,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_3_we & cfg_regwen_qs),
.wd (ack_mode_val_3_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[3].q ),
+ .q (reg2hw.ack_mode[3].q),
// to register interface (read)
.qs (ack_mode_val_3_qs)
@@ -540,20 +540,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_4_we & cfg_regwen_qs),
.wd (ack_mode_val_4_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[4].q ),
+ .q (reg2hw.ack_mode[4].q),
// to register interface (read)
.qs (ack_mode_val_4_qs)
@@ -566,20 +566,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_5_we & cfg_regwen_qs),
.wd (ack_mode_val_5_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[5].q ),
+ .q (reg2hw.ack_mode[5].q),
// to register interface (read)
.qs (ack_mode_val_5_qs)
@@ -592,20 +592,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_6_we & cfg_regwen_qs),
.wd (ack_mode_val_6_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[6].q ),
+ .q (reg2hw.ack_mode[6].q),
// to register interface (read)
.qs (ack_mode_val_6_qs)
@@ -618,20 +618,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_7_we & cfg_regwen_qs),
.wd (ack_mode_val_7_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[7].q ),
+ .q (reg2hw.ack_mode[7].q),
// to register interface (read)
.qs (ack_mode_val_7_qs)
@@ -644,20 +644,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_8_we & cfg_regwen_qs),
.wd (ack_mode_val_8_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[8].q ),
+ .q (reg2hw.ack_mode[8].q),
// to register interface (read)
.qs (ack_mode_val_8_qs)
@@ -670,20 +670,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_9_we & cfg_regwen_qs),
.wd (ack_mode_val_9_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[9].q ),
+ .q (reg2hw.ack_mode[9].q),
// to register interface (read)
.qs (ack_mode_val_9_qs)
@@ -696,20 +696,20 @@
.SWACCESS("RW"),
.RESVAL (2'h0)
) u_ack_mode_val_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
- // from register interface (qualified with register enable)
+ // from register interface
.we (ack_mode_val_10_we & cfg_regwen_qs),
.wd (ack_mode_val_10_wd),
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.ack_mode[10].q ),
+ .q (reg2hw.ack_mode[10].q),
// to register interface (read)
.qs (ack_mode_val_10_qs)
@@ -727,8 +727,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_0_we),
@@ -736,11 +736,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[0].q ),
+ .q (reg2hw.alert_trig[0].q),
// to register interface (read)
.qs (alert_trig_val_0_qs)
@@ -753,8 +753,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_1_we),
@@ -762,11 +762,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[1].q ),
+ .q (reg2hw.alert_trig[1].q),
// to register interface (read)
.qs (alert_trig_val_1_qs)
@@ -779,8 +779,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_2_we),
@@ -788,11 +788,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[2].q ),
+ .q (reg2hw.alert_trig[2].q),
// to register interface (read)
.qs (alert_trig_val_2_qs)
@@ -805,8 +805,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_3_we),
@@ -814,11 +814,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[3].q ),
+ .q (reg2hw.alert_trig[3].q),
// to register interface (read)
.qs (alert_trig_val_3_qs)
@@ -831,8 +831,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_4_we),
@@ -840,11 +840,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[4].q ),
+ .q (reg2hw.alert_trig[4].q),
// to register interface (read)
.qs (alert_trig_val_4_qs)
@@ -857,8 +857,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_5_we),
@@ -866,11 +866,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[5].q ),
+ .q (reg2hw.alert_trig[5].q),
// to register interface (read)
.qs (alert_trig_val_5_qs)
@@ -883,8 +883,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_6_we),
@@ -892,11 +892,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[6].q ),
+ .q (reg2hw.alert_trig[6].q),
// to register interface (read)
.qs (alert_trig_val_6_qs)
@@ -909,8 +909,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_7_we),
@@ -918,11 +918,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[7].q ),
+ .q (reg2hw.alert_trig[7].q),
// to register interface (read)
.qs (alert_trig_val_7_qs)
@@ -935,8 +935,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_8_we),
@@ -944,11 +944,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[8].q ),
+ .q (reg2hw.alert_trig[8].q),
// to register interface (read)
.qs (alert_trig_val_8_qs)
@@ -961,8 +961,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_9_we),
@@ -970,11 +970,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[9].q ),
+ .q (reg2hw.alert_trig[9].q),
// to register interface (read)
.qs (alert_trig_val_9_qs)
@@ -987,8 +987,8 @@
.SWACCESS("RW"),
.RESVAL (1'h0)
) u_alert_trig_val_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_trig_val_10_we),
@@ -996,11 +996,11 @@
// from internal hardware
.de (1'b0),
- .d ('0 ),
+ .d ('0),
// to internal hardware
.qe (),
- .q (reg2hw.alert_trig[10].q ),
+ .q (reg2hw.alert_trig[10].q),
// to register interface (read)
.qs (alert_trig_val_10_qs)
@@ -1018,8 +1018,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_0 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_0_we),
@@ -1027,11 +1027,11 @@
// from internal hardware
.de (hw2reg.alert_state[0].de),
- .d (hw2reg.alert_state[0].d ),
+ .d (hw2reg.alert_state[0].d),
// to internal hardware
.qe (reg2hw.alert_state[0].qe),
- .q (reg2hw.alert_state[0].q ),
+ .q (reg2hw.alert_state[0].q),
// to register interface (read)
.qs (alert_state_val_0_qs)
@@ -1044,8 +1044,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_1 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_1_we),
@@ -1053,11 +1053,11 @@
// from internal hardware
.de (hw2reg.alert_state[1].de),
- .d (hw2reg.alert_state[1].d ),
+ .d (hw2reg.alert_state[1].d),
// to internal hardware
.qe (reg2hw.alert_state[1].qe),
- .q (reg2hw.alert_state[1].q ),
+ .q (reg2hw.alert_state[1].q),
// to register interface (read)
.qs (alert_state_val_1_qs)
@@ -1070,8 +1070,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_2 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_2_we),
@@ -1079,11 +1079,11 @@
// from internal hardware
.de (hw2reg.alert_state[2].de),
- .d (hw2reg.alert_state[2].d ),
+ .d (hw2reg.alert_state[2].d),
// to internal hardware
.qe (reg2hw.alert_state[2].qe),
- .q (reg2hw.alert_state[2].q ),
+ .q (reg2hw.alert_state[2].q),
// to register interface (read)
.qs (alert_state_val_2_qs)
@@ -1096,8 +1096,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_3 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_3_we),
@@ -1105,11 +1105,11 @@
// from internal hardware
.de (hw2reg.alert_state[3].de),
- .d (hw2reg.alert_state[3].d ),
+ .d (hw2reg.alert_state[3].d),
// to internal hardware
.qe (reg2hw.alert_state[3].qe),
- .q (reg2hw.alert_state[3].q ),
+ .q (reg2hw.alert_state[3].q),
// to register interface (read)
.qs (alert_state_val_3_qs)
@@ -1122,8 +1122,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_4 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_4_we),
@@ -1131,11 +1131,11 @@
// from internal hardware
.de (hw2reg.alert_state[4].de),
- .d (hw2reg.alert_state[4].d ),
+ .d (hw2reg.alert_state[4].d),
// to internal hardware
.qe (reg2hw.alert_state[4].qe),
- .q (reg2hw.alert_state[4].q ),
+ .q (reg2hw.alert_state[4].q),
// to register interface (read)
.qs (alert_state_val_4_qs)
@@ -1148,8 +1148,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_5 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_5_we),
@@ -1157,11 +1157,11 @@
// from internal hardware
.de (hw2reg.alert_state[5].de),
- .d (hw2reg.alert_state[5].d ),
+ .d (hw2reg.alert_state[5].d),
// to internal hardware
.qe (reg2hw.alert_state[5].qe),
- .q (reg2hw.alert_state[5].q ),
+ .q (reg2hw.alert_state[5].q),
// to register interface (read)
.qs (alert_state_val_5_qs)
@@ -1174,8 +1174,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_6 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_6_we),
@@ -1183,11 +1183,11 @@
// from internal hardware
.de (hw2reg.alert_state[6].de),
- .d (hw2reg.alert_state[6].d ),
+ .d (hw2reg.alert_state[6].d),
// to internal hardware
.qe (reg2hw.alert_state[6].qe),
- .q (reg2hw.alert_state[6].q ),
+ .q (reg2hw.alert_state[6].q),
// to register interface (read)
.qs (alert_state_val_6_qs)
@@ -1200,8 +1200,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_7 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_7_we),
@@ -1209,11 +1209,11 @@
// from internal hardware
.de (hw2reg.alert_state[7].de),
- .d (hw2reg.alert_state[7].d ),
+ .d (hw2reg.alert_state[7].d),
// to internal hardware
.qe (reg2hw.alert_state[7].qe),
- .q (reg2hw.alert_state[7].q ),
+ .q (reg2hw.alert_state[7].q),
// to register interface (read)
.qs (alert_state_val_7_qs)
@@ -1226,8 +1226,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_8 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_8_we),
@@ -1235,11 +1235,11 @@
// from internal hardware
.de (hw2reg.alert_state[8].de),
- .d (hw2reg.alert_state[8].d ),
+ .d (hw2reg.alert_state[8].d),
// to internal hardware
.qe (reg2hw.alert_state[8].qe),
- .q (reg2hw.alert_state[8].q ),
+ .q (reg2hw.alert_state[8].q),
// to register interface (read)
.qs (alert_state_val_8_qs)
@@ -1252,8 +1252,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_9 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_9_we),
@@ -1261,11 +1261,11 @@
// from internal hardware
.de (hw2reg.alert_state[9].de),
- .d (hw2reg.alert_state[9].d ),
+ .d (hw2reg.alert_state[9].d),
// to internal hardware
.qe (reg2hw.alert_state[9].qe),
- .q (reg2hw.alert_state[9].q ),
+ .q (reg2hw.alert_state[9].q),
// to register interface (read)
.qs (alert_state_val_9_qs)
@@ -1278,8 +1278,8 @@
.SWACCESS("W1C"),
.RESVAL (1'h0)
) u_alert_state_val_10 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
// from register interface
.we (alert_state_val_10_we),
@@ -1287,11 +1287,11 @@
// from internal hardware
.de (hw2reg.alert_state[10].de),
- .d (hw2reg.alert_state[10].d ),
+ .d (hw2reg.alert_state[10].d),
// to internal hardware
.qe (reg2hw.alert_state[10].qe),
- .q (reg2hw.alert_state[10].q ),
+ .q (reg2hw.alert_state[10].q),
// to register interface (read)
.qs (alert_state_val_10_qs)
@@ -1307,15 +1307,16 @@
.SWACCESS("RO"),
.RESVAL (1'h0)
) u_status_ast_init_done (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.ast_init_done.de),
- .d (hw2reg.status.ast_init_done.d ),
+ .d (hw2reg.status.ast_init_done.d),
// to internal hardware
.qe (),
@@ -1332,15 +1333,16 @@
.SWACCESS("RO"),
.RESVAL (2'h3)
) u_status_io_pok (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
// from internal hardware
.de (hw2reg.status.io_pok.de),
- .d (hw2reg.status.io_pok.d ),
+ .d (hw2reg.status.io_pok.d),
// to internal hardware
.qe (),
diff --git a/util/reggen/reg_top.sv.tpl b/util/reggen/reg_top.sv.tpl
index 8b4e8d3..fc8f671 100644
--- a/util/reggen/reg_top.sv.tpl
+++ b/util/reggen/reg_top.sv.tpl
@@ -454,7 +454,6 @@
% endif
% if field.swaccess.allows_write():
% if regwen:
- // qualified with register enable
.we (${finst_name}_we & ${regwen.lower()}_qs),
% else:
.we (${finst_name}_we),
@@ -483,7 +482,7 @@
% else:
.qe (),
% endif
- .q (reg2hw.${fsig_name}.q ),
+ .q (reg2hw.${fsig_name}.q),
% endif
% if field.swaccess.allows_read():
.qs (${finst_name}_qs)
@@ -508,33 +507,32 @@
.SWACCESS("${field.swaccess.value[1].name.upper()}"),
.RESVAL (${field.bits.width()}'h${"%x" % (field.resval or 0)})
) u_${finst_name} (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ // from register interface
% if shadowed:
.re (${finst_name}_re),
% endif
% if field.swaccess.allows_write(): ## non-RO types
% if regwen:
- // from register interface (qualified with register enable)
.we (${finst_name}_we & ${regwen.lower()}_qs),
% else:
- // from register interface
.we (${finst_name}_we),
% endif
.wd (${finst_name}_wd),
% else: ## RO types
.we (1'b0),
- .wd ('0 ),
+ .wd ('0),
% endif
// from internal hardware
% if field.hwaccess.allows_write():
.de (hw2reg.${fsig_name}.de),
- .d (hw2reg.${fsig_name}.d ),
+ .d (hw2reg.${fsig_name}.d),
% else:
.de (1'b0),
- .d ('0 ),
+ .d ('0),
% endif
// to internal hardware
@@ -547,26 +545,25 @@
% else:
.qe (),
% endif
- .q (reg2hw.${fsig_name}.q ),
+ .q (reg2hw.${fsig_name}.q),
% endif
+ // to register interface (read)
% if not shadowed:
% if field.swaccess.allows_read():
- // to register interface (read)
.qs (${finst_name}_qs)
% else:
.qs ()
% endif
% else:
% if field.swaccess.allows_read():
- // to register interface (read)
.qs (${finst_name}_qs),
% else:
.qs (),
% endif
// Shadow register error conditions
- .err_update (reg2hw.${fsig_name}.err_update ),
+ .err_update (reg2hw.${fsig_name}.err_update),
.err_storage (reg2hw.${fsig_name}.err_storage)
% endif
);
