| commit | be106f192e7e77a9038adf577aafa6c2d4e03b6c | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Aug 19 13:27:55 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Thu Aug 28 16:49:59 2025 -0700 |
| tree | 952c899da41243dae45144168d4f4eb585d02780 | |
| parent | 148e450ec330c1cd4236d5caa317c0b4b1e34f9f [diff] |
feat(bus): Add TileLink-UL primitives This commit introduces a collection of primitive modules for building TileLink-UL interconnects, including FIFOs, sockets, and a width bridge. The new modules are: - TlulFifoSync: A synchronous TileLink FIFO with optional spare side-channels. - TlulFifoAsync: An asynchronous TileLink FIFO for clock domain crossing, built on the rocket-chip AsyncQueue. - TlulSocket1N: A 1-to-N socket for steering requests from a single host to one of N devices. - TlulSocketM1: An M-to-1 socket that arbitrates requests from M hosts to a single device using a round-robin arbiter. - TlulWidthBridge: A bridge for connecting TileLink-UL buses of different widths. Each of these modules is accompanied by a comprehensive cocotb test suite to ensure its correctness. Change-Id: I2ca34caad9332b0621a68957c043a91deee45999
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog