tree 952c899da41243dae45144168d4f4eb585d02780
parent 148e450ec330c1cd4236d5caa317c0b4b1e34f9f
author Alex Van Damme <atv@google.com> 1755635275 -0700
committer Alex Van Damme <atv@google.com> 1756424999 -0700

feat(bus): Add TileLink-UL primitives

This commit introduces a collection of primitive modules for building
TileLink-UL interconnects, including FIFOs, sockets, and a width
bridge.

The new modules are:
- TlulFifoSync: A synchronous TileLink FIFO with optional spare
  side-channels.
- TlulFifoAsync: An asynchronous TileLink FIFO for clock domain
  crossing, built on the rocket-chip AsyncQueue.
- TlulSocket1N: A 1-to-N socket for steering requests from a single
  host to one of N devices.
- TlulSocketM1: An M-to-1 socket that arbitrates requests from M
  hosts to a single device using a round-robin arbiter.
- TlulWidthBridge: A bridge for connecting TileLink-UL buses of
  different widths.

Each of these modules is accompanied by a comprehensive cocotb test
suite to ensure its correctness.

Change-Id: I2ca34caad9332b0621a68957c043a91deee45999