| commit | 148e450ec330c1cd4236d5caa317c0b4b1e34f9f | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Aug 19 13:27:12 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Thu Aug 28 16:49:58 2025 -0700 |
| tree | 126e67a850338811ada1742451acf848e9af47e0 | |
| parent | b9b0d55ba96b549756bb207a33dae793a9495859 [diff] |
refactor(bus): Clean up AXI/TL-UL bridges and tests This commit refactors the AXI-to-TileLink and TileLink-to-AXI bridge logic and cleans up the associated test infrastructure. Key changes: - Simplified the ready signal logic in `Axi2TLUL.scala` for better clarity and correctness. - Moved the cocotb test files for the AXI/TL-UL bridges from `hdl/chisel/src/bus` to a dedicated `tests/cocotb/tlul` directory. - Reorganized the Bazel BUILD files to reflect the new test locations and improve dependency management. - Added minor delays at the end of the `tlul2axi` tests to facilitate easier waveform debugging. Change-Id: I9a2a3c6510d34b010e0ecc2ba1da1db3e1462f2b
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog