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{
  "commit": "be106f192e7e77a9038adf577aafa6c2d4e03b6c",
  "tree": "952c899da41243dae45144168d4f4eb585d02780",
  "parents": [
    "148e450ec330c1cd4236d5caa317c0b4b1e34f9f"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Tue Aug 19 13:27:55 2025 -0700"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Thu Aug 28 16:49:59 2025 -0700"
  },
  "message": "feat(bus): Add TileLink-UL primitives\n\nThis commit introduces a collection of primitive modules for building\nTileLink-UL interconnects, including FIFOs, sockets, and a width\nbridge.\n\nThe new modules are:\n- TlulFifoSync: A synchronous TileLink FIFO with optional spare\n  side-channels.\n- TlulFifoAsync: An asynchronous TileLink FIFO for clock domain\n  crossing, built on the rocket-chip AsyncQueue.\n- TlulSocket1N: A 1-to-N socket for steering requests from a single\n  host to one of N devices.\n- TlulSocketM1: An M-to-1 socket that arbitrates requests from M\n  hosts to a single device using a round-robin arbiter.\n- TlulWidthBridge: A bridge for connecting TileLink-UL buses of\n  different widths.\n\nEach of these modules is accompanied by a comprehensive cocotb test\nsuite to ensure its correctness.\n\nChange-Id: I2ca34caad9332b0621a68957c043a91deee45999\n",
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