36ad2bdd5bb63d49898a105341a4bc0a6dd06d0e - hw/kelvin

commit: 36ad2bdd5bb63d49898a105341a4bc0a6dd06d0e
[log]
author: Derek Chow <derekjchow@google.com>
Tue Aug 01 11:10:05 2023 -0700
committer: Derek Chow <derekjchow@google.com>
Thu Aug 03 14:34:03 2023 -0700
tree: e17df483e21dc69d8f85216d0608857c4ab67c13
parent: 9df05a8aefef0514b8b83778257777dea50e6863 [diff]

Kelvin core, with bazel support.

Change-Id: I11ceb466009c1b2e01929327cb946a0f2ab80116

.bazelrc[Added - diff]
.gitignore[Added - diff]
WORKSPACE[Added - diff]
external/0001-Update-version-of-Googletest-for-bazel-compatitibili.patch[Added - diff]
external/0002-SystemC-support-for-verilator.patch[Added - diff]
external/systemc.BUILD[Added - diff]
hdl/chisel/.scalafmt.conf[Added - diff]
hdl/chisel/BUILD[Added - diff]
hdl/chisel/src/common/Fifo.scala[Added - diff]
hdl/chisel/src/common/Fifo4.scala[Added - diff]
hdl/chisel/src/common/Fifo4e.scala[Added - diff]
hdl/chisel/src/common/Fifo4x4.scala[Added - diff]
hdl/chisel/src/common/IDiv.scala[Added - diff]
hdl/chisel/src/common/Library.scala[Added - diff]
hdl/chisel/src/common/Slice.scala[Added - diff]
hdl/chisel/src/kelvin/Axi.scala[Added - diff]
hdl/chisel/src/kelvin/ClockGate.scala[Added - diff]
hdl/chisel/src/kelvin/Core.scala[Added - diff]
hdl/chisel/src/kelvin/DBus2Axi.scala[Added - diff]
hdl/chisel/src/kelvin/DBusMux.scala[Added - diff]
hdl/chisel/src/kelvin/L1DCache.scala[Added - diff]
hdl/chisel/src/kelvin/L1ICache.scala[Added - diff]
hdl/chisel/src/kelvin/Library.scala[Added - diff]
hdl/chisel/src/kelvin/Parameters.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Alu.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Bru.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Csr.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Debug.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Decode.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Dvu.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Fetch.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Flush.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Lsu.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Mlu.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/Regfile.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/SCore.scala[Added - diff]
hdl/chisel/src/kelvin/scalar/SLog.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VAlu.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VAluInt.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VCmdq.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VCommon.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VConvAlu.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VConvCtrl.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VCore.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VDecode.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VDecodeInstruction.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VDecodeOp.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VDot.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VEncodeOp.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VInst.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VLd.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VLdSt.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VRegfile.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VRegfileSegment.scala[Added - diff]
hdl/chisel/src/kelvin/vector/VSt.scala[Added - diff]
hdl/verilog/BUILD[Added - diff]
hdl/verilog/ClockGate.v[Added - diff]
hdl/verilog/Sram_1rw_256x256.v[Added - diff]
hdl/verilog/Sram_1rwm_256x288.v[Added - diff]
lib/BUILD[Added - diff]
rules/BUILD[Added - diff]
rules/chisel.bzl[Added - diff]
rules/deps.bzl[Added - diff]
rules/repos.bzl[Added - diff]
rules/verilator.bzl[Added - diff]
tests/verilator_sim/BUILD[Added - diff]
tests/verilator_sim/fifo.h[Added - diff]
tests/verilator_sim/kelvin/core_if.h[Added - diff]
tests/verilator_sim/kelvin/core_tb.cc[Added - diff]
tests/verilator_sim/kelvin/dbus2axi_tb.cc[Added - diff]
tests/verilator_sim/kelvin/debug_if.h[Added - diff]
tests/verilator_sim/kelvin/kelvin_cfg.h[Added - diff]
tests/verilator_sim/kelvin/l1dcache_tb.cc[Added - diff]
tests/verilator_sim/kelvin/l1dcachebank_tb.cc[Added - diff]
tests/verilator_sim/kelvin/l1icache_tb.cc[Added - diff]
tests/verilator_sim/kelvin/memory_if.h[Added - diff]
tests/verilator_sim/kelvin/valu.h[Added - diff]
tests/verilator_sim/kelvin/valu_tb.cc[Added - diff]
tests/verilator_sim/kelvin/valuint_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vcmdq_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vconvalu_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vconvctrl_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vdecode.h[Added - diff]
tests/verilator_sim/kelvin/vdecode_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vdecodeinstruction_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vdecodeop.h[Added - diff]
tests/verilator_sim/kelvin/vencodeop.h[Added - diff]
tests/verilator_sim/kelvin/vld_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vldst_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vregfile_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vregfilesegment_tb.cc[Added - diff]
tests/verilator_sim/kelvin/vst_tb.cc[Added - diff]
tests/verilator_sim/sysc_module.h[Added - diff]
tests/verilator_sim/sysc_tb.h[Added - diff]

94 files changed

tree: e17df483e21dc69d8f85216d0608857c4ab67c13