| commit | 5a16231216eeb507e8863578a299b9de672a6218 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Sep 02 16:23:24 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Thu Sep 18 10:30:34 2025 -0700 |
| tree | ae80734f8bb9cb8ecf44501ea4a7cca0ed86cdfa | |
| parent | bd14438f39e4979800bf8f043c50bd78c2084f4c [diff] |
feat(fpga): Add SPI DPI Master for Verilator simulation This commit introduces a SPI DPI master module to enable host-driven testing of the SoC in Verilator simulations. This provides a way to interact with the simulated design over SPI, mimicking how a host computer would interact with the physical FPGA. The implementation consists of: - **`spi_dpi_master.sv`**: A SystemVerilog module that uses the SystemVerilog DPI to call into a C++ backend. - **`spi_dpi_master.cc`**: A C++ backend that implements the DPI functions. It starts a TCP server that listens for high-level commands (e.g., WRITE_REG, BULK_READ). It then translates these commands into the correct sequence of SPI signal toggles, which are driven back into the simulation. This DPI module allows Python test scripts to connect to the simulation via a TCP socket and drive SPI transactions, enabling more realistic and hardware-in-the-loop style testing. Change-Id: I030bdbbb5598c75a9b11f82895de60a8c77d588f
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog