| commit | bd14438f39e4979800bf8f043c50bd78c2084f4c | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Tue Sep 02 16:21:16 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Thu Sep 18 10:30:34 2025 -0700 |
| tree | fe87d8b037c729dad530c39d701b59734bd43ca6 | |
| parent | 813d03e1c896c4c6c44a9eda9e25e7686d0b4e85 [diff] |
refactor(soc): Introduce unified KelvinChiselSubsystem
This commit introduces a major architectural refactoring by creating a unified `KelvinChiselSubsystem`. This new top-level module programmatically instantiates and connects all Chisel-based components of the SoC, including the RV core, crossbar, and peripherals like the Spi2TLUL bridge.
Key changes:
- **`SoCChiselConfig.scala`**: A new central configuration file that defines the modules to be instantiated, their parameters, and their connections. This allows for a more flexible and maintainable SoC architecture.
- **`KelvinChiselSubsystem.scala`**: The new top-level module that reads the configuration and builds the hardware graph, connecting modules to the crossbar and exposing external ports.
- **`CrossbarConfig.scala`**: Updated to be more dynamic. It now sources its configuration from `SoCChiselConfig` and supports a test harness mode. The Ibex core hosts have been removed and replaced by the `spi2tlul` host and a generic 32-bit test host.
- **Tests**:
- The existing crossbar tests (`kelvin_xbar_test.py`) have been updated to use the new test harness and reflect the new port mapping.
- A new subsystem-level test suite (`test_subsystem.py`) has been added to verify the integrated subsystem. These tests demonstrate loading and executing an ELF file on the core via both a TL-UL test host and the SPI bridge.
This refactoring simplifies the top-level Verilog (`kelvin_soc.sv`) and provides a more scalable and configurable way to build the SoC.
Change-Id: Ib8249023d3df3da32a62b00006e103b5f8236f4f
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog