| commit | 813d03e1c896c4c6c44a9eda9e25e7686d0b4e85 | [log] [tgz] |
|---|---|---|
| author | Alex Van Damme <atv@google.com> | Wed Sep 17 16:16:46 2025 -0700 |
| committer | Alex Van Damme <atv@google.com> | Thu Sep 18 10:30:34 2025 -0700 |
| tree | 114e4c42a1fe8dbdfc879d3c3ae917052527877c | |
| parent | 7759a66faa0121563684b83fabb179db5f0ca410 [diff] |
feat(spi): Increase Spi2TLUL bulk transfer size to 16-bit This change increases the maximum bulk transfer size of the Spi2TLUL module from 256 bytes to 65536 bytes by widening the length registers from 8 to 16 bits. The key changes include: - Updated the Spi2TLUL Chisel module to use 16-bit length registers for both bulk and regular TileLink transfers. - Modified the SPI command state machine to handle two-byte length transactions. - Re-implemented the internal data buffers using SyncReadMem to support larger, configurable depths, and increased the buffer size to 4KB. - Introduced pipelining for SRAM reads to improve performance with larger data transfers. - Updated the Python SPI master utility and cocotb tests to support 16-bit register accesses and larger data transfers. - Added new cocotb tests to verify large (up to 4KB) packed writes and pipelined reads. Change-Id: I4420f969584976c4fb16b25513c1791e54aced4c
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog