)]}'
{
  "commit": "5a16231216eeb507e8863578a299b9de672a6218",
  "tree": "ae80734f8bb9cb8ecf44501ea4a7cca0ed86cdfa",
  "parents": [
    "bd14438f39e4979800bf8f043c50bd78c2084f4c"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Tue Sep 02 16:23:24 2025 -0700"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Thu Sep 18 10:30:34 2025 -0700"
  },
  "message": "feat(fpga): Add SPI DPI Master for Verilator simulation\n\nThis commit introduces a SPI DPI master module to enable host-driven testing of the SoC in Verilator simulations. This provides a way to interact with the simulated design over SPI, mimicking how a host computer would interact with the physical FPGA.\n\nThe implementation consists of:\n- **`spi_dpi_master.sv`**: A SystemVerilog module that uses the SystemVerilog DPI to call into a C++ backend.\n- **`spi_dpi_master.cc`**: A C++ backend that implements the DPI functions. It starts a TCP server that listens for high-level commands (e.g., WRITE_REG, BULK_READ). It then translates these commands into the correct sequence of SPI signal toggles, which are driven back into the simulation.\n\nThis DPI module allows Python test scripts to connect to the simulation via a TCP socket and drive SPI transactions, enabling more realistic and hardware-in-the-loop style testing.\n\nChange-Id: I030bdbbb5598c75a9b11f82895de60a8c77d588f\n",
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