tree ae80734f8bb9cb8ecf44501ea4a7cca0ed86cdfa
parent bd14438f39e4979800bf8f043c50bd78c2084f4c
author Alex Van Damme <atv@google.com> 1756855404 -0700
committer Alex Van Damme <atv@google.com> 1758216634 -0700

feat(fpga): Add SPI DPI Master for Verilator simulation

This commit introduces a SPI DPI master module to enable host-driven testing of the SoC in Verilator simulations. This provides a way to interact with the simulated design over SPI, mimicking how a host computer would interact with the physical FPGA.

The implementation consists of:
- **`spi_dpi_master.sv`**: A SystemVerilog module that uses the SystemVerilog DPI to call into a C++ backend.
- **`spi_dpi_master.cc`**: A C++ backend that implements the DPI functions. It starts a TCP server that listens for high-level commands (e.g., WRITE_REG, BULK_READ). It then translates these commands into the correct sequence of SPI signal toggles, which are driven back into the simulation.

This DPI module allows Python test scripts to connect to the simulation via a TCP socket and drive SPI transactions, enabling more realistic and hardware-in-the-loop style testing.

Change-Id: I030bdbbb5598c75a9b11f82895de60a8c77d588f