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opensecura / hw / kelvin / 3a18e1d3be283f77e66660c5c09face6fa416459
commit3a18e1d3be283f77e66660c5c09face6fa416459[log] [tgz]
authorAlex Van Damme <atv@google.com>Mon Aug 04 14:55:53 2025 -0700
committerAlex Van Damme <atv@google.com>Wed Aug 06 16:54:35 2025 -0700
treedd2ce71d36b559baf7acbbd8c5224deb9c566a9b
parent4782b765cbd4a159b3791b2fca67243e1d47f9c3 [diff]
refactor(hdl): Make CoreAxiCSR bus-width agnostic

This change refactors the CoreAxiCSR module to be bus-width agnostic.
This is a precursor to adding TileLink support, which has a different
bus width than AXI.

Change-Id: I83424b4b587a5bd6833d9a5e9db862a613af2210
2 files changed
tree: dd2ce71d36b559baf7acbbd8c5224deb9c566a9b
  1. doc/
  2. examples/
  3. external/
  4. hdl/
  5. hw_sim/
  6. kelvin_test_utils/
  7. lib/
  8. platforms/
  9. rules/
  10. tests/
  11. third_party/
  12. toolchain/
  13. utils/
  14. .bazelrc
  15. .bazelversion
  16. .gitignore
  17. CONTRIBUTING.md
  18. LICENSE
  19. PREUPLOAD.cfg
  20. README.md
  21. WORKSPACE
README.md

Kelvin

Kelvin is a RISC-V32IM core with a custom instruction set.

Kelvin block diagram

More information on the design can be found in the overview.

Getting Started

  • If you are hardware engineer looking to integrate Kelvin into your design, check out our integration guide.
  • If you are a software engineer looking to write code for Kelvin, start with this tutorial.

Building

Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:

bazel build //tests/verilator_sim:core_sim

The verilog source for the Kelvin core can be generated using:

bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog

Verilog source for the Matcha SoC can be generated using:

bazel clean --expunge  # To generate the ToT sha
bazel build //hdl/chisel:matcha_kelvin_verilog