refactor(hdl): Make CoreAxiCSR bus-width agnostic This change refactors the CoreAxiCSR module to be bus-width agnostic. This is a precursor to adding TileLink support, which has a different bus width than AXI. Change-Id: I83424b4b587a5bd6833d9a5e9db862a613af2210
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog