commit | 4782b765cbd4a159b3791b2fca67243e1d47f9c3 | [log] [tgz] |
---|---|---|
author | Alex Van Damme <atv@google.com> | Mon Aug 04 14:54:34 2025 -0700 |
committer | Alex Van Damme <atv@google.com> | Wed Aug 06 16:54:35 2025 -0700 |
tree | 48769ed4790e6f6150b990501be247ac08a8f711 | |
parent | 97b73bfa8229815735763bc6335181a8c732ffc8 [diff] |
feat(hdl): Add Chisel TL-UL <-> AXI bridges and CoreTlul Change-Id: I2ffc39a7d559eb64074c214c18e5f46e30f84aa1
Kelvin is a RISC-V32IM core with a custom instruction set.
More information on the design can be found in the overview.
Kelvin uses bazel as it's build system. The Verilated simulator for Kelvin can be generated using:
bazel build //tests/verilator_sim:core_sim
The verilog source for the Kelvin core can be generated using:
bazel build //hdl/chisel/src/kelvin:core_cc_library_emit_verilog
Verilog source for the Matcha SoC can be generated using:
bazel clean --expunge # To generate the ToT sha bazel build //hdl/chisel:matcha_kelvin_verilog