)]}'
{
  "commit": "3a18e1d3be283f77e66660c5c09face6fa416459",
  "tree": "dd2ce71d36b559baf7acbbd8c5224deb9c566a9b",
  "parents": [
    "4782b765cbd4a159b3791b2fca67243e1d47f9c3"
  ],
  "author": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Mon Aug 04 14:55:53 2025 -0700"
  },
  "committer": {
    "name": "Alex Van Damme",
    "email": "atv@google.com",
    "time": "Wed Aug 06 16:54:35 2025 -0700"
  },
  "message": "refactor(hdl): Make CoreAxiCSR bus-width agnostic\n\nThis change refactors the CoreAxiCSR module to be bus-width agnostic.\nThis is a precursor to adding TileLink support, which has a different\nbus width than AXI.\n\nChange-Id: I83424b4b587a5bd6833d9a5e9db862a613af2210\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3aac4a8ed27350af0b700d210e1b7fb0119e11ad",
      "old_mode": 33188,
      "old_path": "hdl/chisel/src/kelvin/CoreAxiCSR.scala",
      "new_id": "96390903aa433339381015c98a777d028c24589f",
      "new_mode": 33188,
      "new_path": "hdl/chisel/src/kelvin/CoreAxiCSR.scala"
    },
    {
      "type": "modify",
      "old_id": "b2b187af90c6cc638ad1a47d32a03904c9f6eff6",
      "old_mode": 33188,
      "old_path": "hdl/chisel/src/kelvin/CoreAxiCSRTest.scala",
      "new_id": "8715c094d850ad65bf5389a37f0ae2e63ec13588",
      "new_mode": 33188,
      "new_path": "hdl/chisel/src/kelvin/CoreAxiCSRTest.scala"
    }
  ]
}