- 3525aa8 [Draft] - clock manager WIP by Timothy Chen · 5 years ago
- 79408a2 [sw] Fix PASS!, FAIL! signatures for CI by Srikrishna Iyer · 5 years ago
- 7d7f1e1 [sw] main.c SW abstraction by Srikrishna Iyer · 5 years ago
- 256a7f3 [chip dv] Update the SW aes_test.c to run in DV by Srikrishna Iyer · 5 years ago
- 64b7a6e [chip dv] Add `aes_test` to chip level DV by Srikrishna Iyer · 5 years ago
- e89bc96 [fpv/pwrmgr] Add pwrmgr and top_earlgrey to FPV by Cindy Chen · 5 years ago
- e022e4d [doc] Document Docker clang-format version by Sam Elliott · 5 years ago
- ae19bec [dvsim] small fix on css style by Cindy Chen · 5 years ago
- 75639fe [sw, dif_uart] Return enum error codes instead of bool by Silvestrs Timofejevs · 5 years ago
- a0b0c4c [sw, uart] Fix ConfigTest NullArgs test by Silvestrs Timofejevs · 5 years ago
- 1cf66af [util] Add optional fields to reggen, topgen by Eunchan Kim · 5 years ago
- 5a90f7d [sw/dif] Fix UART *irq_state_clear by Srikrishna Iyer · 5 years ago
- 9286ee6 Add extern declarations for mmion_region_write_only_set*32() functions. by Alphan Ulusoy · 5 years ago
- 837c796 [util/tlgen] Fix flake8 lint errors by Eunchan Kim · 5 years ago
- df151aa [prim] Add primitive for REQ/ACK synchronization by Pirmin Vogel · 5 years ago
- f2eb1d5 [aes/dv] Adapt CSR test exclusions by Pirmin Vogel · 5 years ago
- adb3462 [doc/comportability] Add inter-module field by Eunchan Kim · 5 years ago
- 0bd7566 [reggen] Flake8 lint fix for reggen by Eunchan Kim · 5 years ago
- ce335d9 [dv/alert_handler] reduce the stress_all run time by Cindy Chen · 5 years ago
- 049eead [topgen] Check valid pairs of inter-module type/act by Eunchan Kim · 5 years ago
- 1aff665 [dvsim] support css format for email by Cindy Chen · 5 years ago
- 5686df3 [sw] Add DIF Stages for Committed DIFs by Sam Elliott · 5 years ago
- 108420c [doc] Track DIF Development Stages on HW Dashboard by Sam Elliott · 5 years ago
- b988cbc [doc] Add DIF Specification and Checklists by Sam Elliott · 5 years ago
- 2061d8b [doc] Rename Hardware -> Development Stages by Sam Elliott · 5 years ago
- 2b10f69 [docker] Added clang-format-3.8 to docker by Srikrishna Iyer · 5 years ago
- 920b48f [prim/secded] Revise comment by Eunchan Kim · 5 years ago
- 2b2e363 [dv/spi_device] Fix csr test failure and intr test by Weicai Yang · 5 years ago
- 3c8553d [dv] Add test csr_mem_rw_with_rand_reset by Weicai Yang · 5 years ago
- 7681285 [doc] Show mask usage in prim_packer example by Sam Elliott · 5 years ago
- 1d5bbcc [topgen] Add External to the top port by Eunchan Kim · 5 years ago
- fd561be [top_earlgrey] Change the `earlgrey` to generic by Eunchan Kim · 5 years ago
- 95142f7 [sw] Clean up boot_rom SPI bootstrap code. by Miguel Young de la Sota · 5 years ago
- 16367c9 [sw] Remove Interrupt Definitions from PLIC DIF by Sam Elliott · 5 years ago
- e5a5289 [doc] Linked DV plan & testplan in HW stages by Srikrishna Iyer · 5 years ago
- 1d17b12 [fpv] Fix compile error by Cindy Chen · 5 years ago
- 4564cc5 [dv/alert_handler] entropy length adjustment by Cindy Chen · 5 years ago
- 75e3e65 [dv] Add excl for rstmgr, pwrmgr and fix top-level csr test by Weicai Yang · 5 years ago
- 7d38bf9 [dv] Allow dv_lib-based sequences to have different RSP/REQ types by Rupert Swarbrick · 5 years ago
- 6cc2011 [dvsim] PEP8 fixes in dvsim by Rupert Swarbrick · 5 years ago
- ec62b3e [dvsim] Fix PEP8 error and slightly tidy code in testplan_utils.py by Rupert Swarbrick · 5 years ago
- 5dbaee7 [dvsim] Correct bug in regression creation in dvsim's Modes.py by Rupert Swarbrick · 5 years ago
- 35ca616 [sw] Introduce write_only_set_*32() functions to mmio.h by Miguel Young de la Sota · 5 years ago
- 82e824c [sw] Add a get_field function to bitfield.h by Miguel Young de la Sota · 5 years ago
- 07372da [sw] Add a wfi to the bootrom irq handlers by Miguel Young de la Sota · 5 years ago
- 6a55c6f [dv] Use uvm_config_db to control tlul_assert by Weicai Yang · 5 years ago
- c59f701 [top_earlgrey] - Top level changes to integrate rstmgr / pwrmgr by Timothy Chen · 5 years ago
- b473c93 [rstmgr] - rstmgr updates to enable pwrmgr integration by Timothy Chen · 5 years ago
- 0ab7fb7 [sw] Update to flash_ctrl test to ensure DV build runs by Timothy Chen · 5 years ago
- 15cae7a [sw] Avoid clang-format-ing Vendored Software by Sam Elliott · 5 years ago
- 2a4448b [topgen] Clang-format ignore top_earlgrey.{c,h} by Sam Elliott · 5 years ago
- 7fe0fb0 [topgen] Generate Peripheral Base Addresses for C by Sam Elliott · 5 years ago
- 6d3f9f8 [chip dv] Add support for %s in DV logging by Srikrishna Iyer · 5 years ago
- 529134b [topgen] flake8 lint fix by Eunchan Kim · 5 years ago
- 387aec6 [hw] Add name to padctrl REGEN field by Greg Chadwick · 5 years ago
- 06f7809 [usb/doc] Revise documenation by Pirmin Vogel · 5 years ago
- 2bc2f01 Use StrictMock in MmioTest by Alphan Ulusoy · 5 years ago
- a24497b [util] vendor.py now re-clones by default by Sam Elliott · 5 years ago
- 0550d69 [topgen] - Generate top clock groups variable by Timothy Chen · 5 years ago
- 67689cd [dv] Update top-level to extend from cip_base by Weicai Yang · 5 years ago
- a863a28 [sw, tock] Add the option to build Tock locally by Jon Flatley · 5 years ago
- e1b2a85 [sw] Move check.h back into libruntime by Miguel Young de la Sota · 5 years ago
- 458e7bc [prim_lfsr] - Update assertion comment by Timothy Chen · 5 years ago
- 45a1831 [pwrmgr] Various clean-up and updates by Timothy Chen · 5 years ago
- 55b2cdf [dv] Support WO, RO type for mem by Weicai Yang · 5 years ago
- b61ef1b [sw] Fix for DV logging by Srikrishna Iyer · 5 years ago
- 2d6c5b0 [dv,sw] SW -> DV tb self-checking mechanism - C by Srikrishna Iyer · 5 years ago
- 3cb7c16 [dv,sw] SW -> DV tb self-checking mechanism - SV by Srikrishna Iyer · 5 years ago
- 163050b [pwrmgr] - pwrmgr integration into top_earlgrey by Timothy Chen · 5 years ago
- 04379d9 [alert_handler/doc] Update documentation of escalation signalling. by Michael Schaffner · 5 years ago
- b8fcc7b [regtool] Generate C Defines for Interrupt Fields by Sam Elliott · 5 years ago
- 37d4fbe [topgen] Auto-format Generated top_earlgrey.h by Sam Elliott · 5 years ago
- 7e36bd7 [topgen] Generate PLIC Enums and Peripheral Mapping by Sam Elliott · 5 years ago
- 0938b33 [topgen] Add Module Name When Prefixing Signals by Sam Elliott · 5 years ago
- 025d35d [dv] Enable xcelium coverage publish by Weicai Yang · 5 years ago
- 346b918 [aes/dv/aes_model_dpi] Add DPI call to encrypt/decrypt entire messages by Pirmin Vogel · 5 years ago
- 581a211 [prim] Update lfsr assertion checks coming out of reset by Timothy Chen · 5 years ago
- 63919ca [topgen] support uni/broadcast and multibit of req_rsp by Eunchan Kim · 5 years ago
- 9663405 [dv/alert_handler] random issue esc_clear by Cindy Chen · 5 years ago
- 193ee38 [CI] Re-enable RISC-V Conformance suite CI. by Greg Chadwick · 5 years ago
- 81b8c6c Update riscv_compliance to riscv/riscv-compliance@5a978cf by Greg Chadwick · 5 years ago
- 1287104 [sw] Generate 32-bit and 64-bit .vmem by Greg Chadwick · 5 years ago
- f2c90ba [sw] Adds @lenary to SW Codeowners by Sam Elliott · 5 years ago
- e2ef60a [prim/ram] Allow > 32bit elf loading by Tom Roberts · 5 years ago
- d14b37a Update lowrisc_ibex to lowRISC/ibex@a3a1f9f by Tom Roberts · 5 years ago
- 41a3e43 [mock_testing, dif_uart] Introduce UART mock tests by Silvestrs Timofejevs · 5 years ago
- 6902211 [sw, dif_uart] Introduce public FIFO size constant by Silvestrs Timofejevs · 5 years ago
- 4d26aa9 [sw, dif_uart] Remove null check for base_addr.base by Silvestrs Timofejevs · 5 years ago
- d4b7b50 [ci] Temporarily disable risc-v compliance CI by Greg Chadwick · 5 years ago
- 40098a9 [topgen] Refactor Inter-module to support all by Eunchan Kim · 5 years ago
- 752f06d [dv] Update xcelium option to fix compile error by Weicai Yang · 5 years ago
- f743b44 [dv/rv_timer] fix nighly regression failure by Cindy Chen · 5 years ago
- de344b1 [doc/rv_plic] fix broken doc link by Cindy Chen · 5 years ago
- 6c05c51 [spi_device] Remove latches by Eunchan Kim · 5 years ago
- b6041e5 [tool/dvsim] Enable Xcelium coverage and clean up email arg by Cindy Chen · 5 years ago
- 458e14d [rv_plic] Reaching D2/V2 stage by Eunchan Kim · 5 years ago
- d4d5d2f [lint] Fix several style-lint warnings by Michael Schaffner · 5 years ago
- a912092 [dv] add send email option to dvsim.py by Cindy Chen · 5 years ago
- e8cb3bd [topgen] - Generate reset paths for top level connection by Timothy Chen · 5 years ago
- 612901b [rstmgr] First draft of reset manager by Timothy Chen · 5 years ago
