| commit | 7d38bf9095e6e911259b9e6831bebf0a073839af | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Wed Apr 22 15:27:22 2020 +0100 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Mon Apr 27 10:36:44 2020 -0700 |
| tree | 0de7f3932f23e8011f33a9b076da2b22d3f0d03e | |
| parent | 6cc20110913878ddb1a917f5aca03f648ce3f056 [diff] |
[dv] Allow dv_lib-based sequences to have different RSP/REQ types
Most UVM sequences just send items and don't receive any response:
start_item(req);
`DV_CHECK_RANDOMIZE_FATAL(req)
finish_item(req);
However, sometimes a driver needs to report what happened. For
example, there might have been some sort of error on the bus which
will affect the next sequence item to send. In this case, the driver
calls
seq_item_port.item_done(rsp);
and the sequencer's code looks like
start_item(req);
`DV_CHECK_RANDOMIZE_FATAL(req)
finish_item(req);
get_response(rsp);
// Do something based on rsp...
But what type is rsp? Sometimes, it's enough to send the request item
back. This works nicely when the sequence items are actually
pipelined (so that the sequence can figure out what item finished).
Sometimes, however, you might want to use a different type from the
request type - it's a bit of a bodge just to add another field to the
request for a "back channel".
To support this, many UVM classes are parameterised by "REQ" and
"RSP": the type of request and response item, respectively. Some of
the dv_lib code supported this already (dv_base_seq), but the
sequencer and driver base classes didn't.
This patch adds that support, defaulting to RSP = REQ. The ordering of
parameters looks a little odd, but it seems that lots of OpenTitan
code sets parameters by position, rather than name, so we have to add
any new optional parameter at the end of the list.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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