blob: 1d6d374b2b880de7215078c58c9d8b2a766ce87f [file] [log] [blame]
Rupert Swarbricke77e2f12021-09-03 18:09:53 +01001#!/bin/bash
2# Copyright lowRISC contributors.
3# Licensed under the Apache License, Version 2.0, see LICENSE for details.
4# SPDX-License-Identifier: Apache-2.0
5
6# Build a chip-level verilator simulation
7#
8# Expects three arguments: the toplevel to build, the fusesoc core and
9# the intermediate Verilated binary name
10
11set -e
12
13if [ $# != 1 ]; then
14 echo >&2 "Usage: build-chip-verilator.sh <toplevel>"
15 exit 1
16fi
17tl="$1"
18
19case "$tl" in
20 earlgrey)
21 fileset=fileset_top
22 fusesoc_core=lowrisc:dv:chip_verilator_sim
23 vname=Vchip_sim_tb
Miles Dai91d811e2022-05-10 15:51:17 -040024 verilator_options="--threads 4"
Drew Macraeacfd5d02022-10-31 22:39:44 -040025 make_options="-j 4"
Rupert Swarbricke77e2f12021-09-03 18:09:53 +010026 ;;
27 englishbreakfast)
28 fileset=fileset_topgen
29 fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
30 vname=Vchip_englishbreakfast_verilator
Miles Dai91d811e2022-05-10 15:51:17 -040031 # Englishbreakfast on CI runs on a 2-core CPU
32 verilator_options="--threads 2"
Drew Macraeacfd5d02022-10-31 22:39:44 -040033 make_options="-j 2"
Philipp Wagner83d3b332021-09-29 18:10:14 +010034 util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast
Rupert Swarbricke77e2f12021-09-03 18:09:53 +010035 ;;
36 *)
37 echo >&2 "Unknown toplevel: $tl"
38 exit 1
39esac
40
41# Move to project root
Miles Dai6c340f82022-07-07 14:41:20 -040042cd "$(git rev-parse --show-toplevel)"
Rupert Swarbricke77e2f12021-09-03 18:09:53 +010043
44. util/build_consts.sh
45
46set -x
47
48mkdir -p "$OBJ_DIR/hw"
49mkdir -p "$BIN_DIR/hw/top_${tl}"
50
51fusesoc --cores-root=. \
52 run --flag=$fileset --target=sim --setup --build \
53 --build-root="$OBJ_DIR/hw" \
54 $fusesoc_core \
Drew Macraeacfd5d02022-10-31 22:39:44 -040055 --verilator_options="${verilator_options}" \
56 --make_options="${make_options}"
Rupert Swarbricke77e2f12021-09-03 18:09:53 +010057
58cp "$OBJ_DIR/hw/sim-verilator/${vname}" \
59 "$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator"