Rupert Swarbrick | e77e2f1 | 2021-09-03 18:09:53 +0100 | [diff] [blame] | 1 | #!/bin/bash |
| 2 | # Copyright lowRISC contributors. |
| 3 | # Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 4 | # SPDX-License-Identifier: Apache-2.0 |
| 5 | |
| 6 | # Build a chip-level verilator simulation |
| 7 | # |
| 8 | # Expects three arguments: the toplevel to build, the fusesoc core and |
| 9 | # the intermediate Verilated binary name |
| 10 | |
| 11 | set -e |
| 12 | |
| 13 | if [ $# != 1 ]; then |
| 14 | echo >&2 "Usage: build-chip-verilator.sh <toplevel>" |
| 15 | exit 1 |
| 16 | fi |
| 17 | tl="$1" |
| 18 | |
| 19 | case "$tl" in |
| 20 | earlgrey) |
| 21 | fileset=fileset_top |
| 22 | fusesoc_core=lowrisc:dv:chip_verilator_sim |
| 23 | vname=Vchip_sim_tb |
Miles Dai | 91d811e | 2022-05-10 15:51:17 -0400 | [diff] [blame] | 24 | verilator_options="--threads 4" |
Drew Macrae | acfd5d0 | 2022-10-31 22:39:44 -0400 | [diff] [blame] | 25 | make_options="-j 4" |
Rupert Swarbrick | e77e2f1 | 2021-09-03 18:09:53 +0100 | [diff] [blame] | 26 | ;; |
| 27 | englishbreakfast) |
| 28 | fileset=fileset_topgen |
| 29 | fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator |
| 30 | vname=Vchip_englishbreakfast_verilator |
Miles Dai | 91d811e | 2022-05-10 15:51:17 -0400 | [diff] [blame] | 31 | # Englishbreakfast on CI runs on a 2-core CPU |
| 32 | verilator_options="--threads 2" |
Drew Macrae | acfd5d0 | 2022-10-31 22:39:44 -0400 | [diff] [blame] | 33 | make_options="-j 2" |
Philipp Wagner | 83d3b33 | 2021-09-29 18:10:14 +0100 | [diff] [blame] | 34 | util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast |
Rupert Swarbrick | e77e2f1 | 2021-09-03 18:09:53 +0100 | [diff] [blame] | 35 | ;; |
| 36 | *) |
| 37 | echo >&2 "Unknown toplevel: $tl" |
| 38 | exit 1 |
| 39 | esac |
| 40 | |
| 41 | # Move to project root |
Miles Dai | 6c340f8 | 2022-07-07 14:41:20 -0400 | [diff] [blame] | 42 | cd "$(git rev-parse --show-toplevel)" |
Rupert Swarbrick | e77e2f1 | 2021-09-03 18:09:53 +0100 | [diff] [blame] | 43 | |
| 44 | . util/build_consts.sh |
| 45 | |
| 46 | set -x |
| 47 | |
| 48 | mkdir -p "$OBJ_DIR/hw" |
| 49 | mkdir -p "$BIN_DIR/hw/top_${tl}" |
| 50 | |
| 51 | fusesoc --cores-root=. \ |
| 52 | run --flag=$fileset --target=sim --setup --build \ |
| 53 | --build-root="$OBJ_DIR/hw" \ |
| 54 | $fusesoc_core \ |
Drew Macrae | acfd5d0 | 2022-10-31 22:39:44 -0400 | [diff] [blame] | 55 | --verilator_options="${verilator_options}" \ |
| 56 | --make_options="${make_options}" |
Rupert Swarbrick | e77e2f1 | 2021-09-03 18:09:53 +0100 | [diff] [blame] | 57 | |
| 58 | cp "$OBJ_DIR/hw/sim-verilator/${vname}" \ |
| 59 | "$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator" |