commit | 83d3b33147695615f9b7538bf381ae712c14af12 | [log] [tgz] |
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author | Philipp Wagner <phw@lowrisc.org> | Wed Sep 29 18:10:14 2021 +0100 |
committer | Philipp Wagner <mail@philipp-wagner.com> | Thu Sep 30 11:42:19 2021 +0100 |
tree | c57bc4b3d773777a42a147d8b159ab41519b6416 | |
parent | b1db01379784045a6a49bc1845eb4e3ffc87d774 [diff] |
[englishbreakfast] Don't run topgen as generator Previously, we ran `util/topgen-fusesoc.py` twice as FuseSoC generator; the script produces a number of core files specific for the English Breakfast toplevel on the fly (files similar to the ones we check in for Earl Grey). Running this script as FuseSoC generator had the beauty of hiding it from the developer; running fusesoc was sufficient to generate the files and use them. However, there's also a downside: All cores (i.e. all files ending in `*.core`) which are produced by the script or subprocesses of the script are automatically made a dependency (in FuseSoC terms) of top_englishbreakfast. With upcoming changes, topgen will produce not only cores which can actually be synthesized, but also cores referencing unsynthesizable DV code. This code cannot be made a dependency of top_englishbreakfast, or the build fails (e.g. due to Verilator or Vivado being unable to read the language constructs in those files). With this change, the user trying to simulator or synthesize the English Breakfast toplevel has to first call `util/topgen-fusesoc.py`, which will produce the same files it produced before, and put them into the `build/top_englishbreakfast-autogen` folder. The cores in this folder are available for FuseSoC to pick if needed, but not automatically added as dependency. The actual dependencies that top_englishbreakfast and other IP cores need are then listed in `topgen.core` and `topgen-reg-only.core`, where the generator was called previously. All of this is a stop-gap for the transition period until we have ipgen fully hooked up. Signed-off-by: Philipp Wagner <phw@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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