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Hugo McNallyf6298b32023-02-12 14:47:22 +00001# RSTMGR DV document
Guillermo Maturana0fd914d2021-07-01 15:02:17 -07002
Guillermo Maturana0fd914d2021-07-01 15:02:17 -07003## Goals
4* **DV**
5 * Verify all RSTMGR IP features by running dynamic simulations with a SV/UVM based testbench
Srikrishna Iyer01c56b42021-08-02 12:50:11 -07006 * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules
Guillermo Maturana0fd914d2021-07-01 15:02:17 -07007* **FPV**
8 * Verify TileLink device protocol compliance with an SVA based testbench
9
10## Current status
Hugo McNallyaef0a662023-02-11 19:44:55 +000011* [Design & verification stage](../../../README.md)
12 * [HW development stages](../../../../doc/project_governance/development_stages.md)
Marno van der Maas24f53112023-01-30 14:56:50 +000013* [Simulation results](https://reports.opentitan.org/hw/ip/rstmgr/dv/latest/report.html)
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070014
15## Design features
Hugo McNallyaef0a662023-02-11 19:44:55 +000016For detailed information on RSTMGR design features, please see the [RSTMGR HWIP technical specification](../README.md).
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070017
18## Testbench architecture
Hugo McNallyaef0a662023-02-11 19:44:55 +000019RSTMGR testbench has been constructed based on the [CIP testbench architecture](../../../dv/sv/cip_lib/README.md).
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070020
21### Block diagram
Hugo McNallyaef0a662023-02-11 19:44:55 +000022![Block diagram](./doc/tb.svg)
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070023
24### Top level testbench
Guillermo Maturana0f16fe02022-02-08 11:36:12 -080025The top level testbench is located at [`hw/ip/rstmgr/dv/tb.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/rstmgr/dv/tb.sv).
26It instantiates the RSTMGR DUT module [`hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv).
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070027In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
Hugo McNallyaef0a662023-02-11 19:44:55 +000028* [Clock and reset interface](../../../dv/sv/common_ifs/README.md)
29* [TileLink host interface](../../../dv/sv/tl_agent/README.md)
Guillermo Maturana0f16fe02022-02-08 11:36:12 -080030* RSTMGR interface [`hw/ip/rstmgr/dv/env/rstmgr_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/rstmgr/dv/env/rstmgr_if.sv)
Hugo McNallyaef0a662023-02-11 19:44:55 +000031* Alerts ([`alert_esc_if`](../../../dv/sv/alert_esc_agent/README.md))
32* Devmode ([`pins_if`](../../../dv/sv/common_ifs/README.md))
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070033
34### Common DV utility components
35The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Hugo McNallyaef0a662023-02-11 19:44:55 +000036* [dv_utils_pkg](../../../dv/sv/dv_utils/README.md)
37* [csr_utils_pkg](../../../dv/sv/csr_utils/README.md)
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070038
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070039### Global types & methods
40All common types and methods defined at the package level can be found in
41`rstmgr_env_pkg`. Some of them in use are:
42```systemverilog
Guillermo Maturana0f16fe02022-02-08 11:36:12 -080043 typedef logic [NumSwResets-1:0] sw_rst_t;
44 typedef logic [$bits(alert_pkg::alert_crashdump_t)-1:0] linearized_alert_dump_t;
45 typedef virtual pwrmgr_rstmgr_sva_if #(.CHECK_RSTREQS(0)) parameterized_pwrmgr_rstmgr_sva_vif;
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070046```
47### TL_agent
Hugo McNallyaef0a662023-02-11 19:44:55 +000048The RSTMGR testbench instantiates (already handled in CIP base env) [tl_agent](../../../dv/sv/tl_agent/README.md).
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070049This provides the ability to drive and independently monitor random traffic via the TL host interface into the RSTMGR device.
50
51### Alert_agents
Hugo McNallyaef0a662023-02-11 19:44:55 +000052RSTMGR testbench instantiates (already handled in CIP base env) [alert_agents](../../../dv/sv/alert_esc_agent/README.md):
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070053[list alert names].
54The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in RSTMGR device.
55
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070056### UVM RAL Model
Hugo McNallyaef0a662023-02-11 19:44:55 +000057The RSTMGR RAL model is created with the [`ralgen`](../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage.
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070058
Hugo McNallyaef0a662023-02-11 19:44:55 +000059It can be created manually by invoking [`regtool`](../../../../util/reggen/doc/setup_and_use.md).
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070060
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070061### Stimulus strategy
Guillermo Maturanaa2ca9982021-08-12 12:08:47 -070062The following test sequences and covergroups are described in more detail in the testplan at `hw/ip/pwrmgr/data/rstmgr_testplan.hjson`, and also included [below](#testplan).
Guillermo Maturanafa4085c2021-07-27 11:48:19 -070063
Guillermo Maturanabb09c792021-08-29 09:53:28 -070064This IP is only reset via the `por_n_i` input, and by `scan_rst_ni` qualified by `scanmode_i` being active.
65The regular `rst_ni` input is connected to its own `resets_o.rst_por_io_div4_n[0]` output, so the reset output from `clk_rst_if` is not connected.
66Similarly, all reset outputs from other `clk_rst_if` instances are ignored, and only their clock output is used.
67This is consistent with this IP being in charge of all derived resets in the chip.
68
Guillermo Maturana0f16fe02022-02-08 11:36:12 -080069Besides the POR resets above, the test sequences mostly assert various reset requests from pwrmgr and trigger resets vir RESET_REQ CSR.
70Alert and CPU dump info is randomized and checked on resets.
71
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070072#### Test sequences
Guillermo Maturana0f16fe02022-02-08 11:36:12 -080073The test sequences reside in [`hw/ip/rstmgr/dv/env/seq_lib`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/rstmgr/dv/env/seq_lib).
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070074All test sequences are extended from `rstmgr_base_vseq`, which is extended from `cip_base_vseq` and serves as a starting point.
75It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
76Some of the most commonly used tasks / functions are as follows:
Guillermo Maturanafa4085c2021-07-27 11:48:19 -070077* task `wait_for_cpu_out_of_reset`:
Guillermo Maturanabb09c792021-08-29 09:53:28 -070078 Waits for the `resets_o.rst_sys_n[1]` output to go high, indicating the CPU is out of reset and CSRs can be accessed.
Guillermo Maturanaa2ca9982021-08-12 12:08:47 -070079* task `check_cpu_dump_info`:
80 Reads and compares each field in the `cpu_info` CSR against the given cpu dump.
81* task `check_software_reset_csr_and_pins`:
82 Reads and compares the `sw_rst_ctrl_n` CSR and the output reset ports against the given value.
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070083
Guillermo Maturanabb09c792021-08-29 09:53:28 -070084Other sequences follow:
85* `rstmgr_smoke_vseq` tests the rstmgr through software initiated low power, peripheral reset, ndm reset, and software initiated resets.
86* `rstmgr_reset_stretcher_vseq` tests the `resets_o.rst_por_aon_n[0]` output is asserted after 32 stable cycles of `ast_i.aon_pok`.
Guillermo Maturanaef60f5f2021-09-24 12:54:29 -070087* `rstmgr_sw_rst_vseq` tests the functionality provided by the `sw_rst_regwen` and `sw_rst_ctrl_n`.
Guillermo Maturanabb09c792021-08-29 09:53:28 -070088* `rstmgr_reset_info_vseq` tests the `reset_info` CSR contents correspond to the different resets.
89* `rstmgr_cpu_info_vseq` tests the `cpu_info` CSR contents capture to the `cpu_dump_i` present at the time of a reset.
90* `rstmgr_alert_info_vseq` tests the `alert_info` CSR contents capture to the `alert_dump_i` present at the time of a reset.
Guillermo Maturana5523a662021-08-23 18:46:38 -070091
Guillermo Maturana0fd914d2021-07-01 15:02:17 -070092#### Functional coverage
93To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model.
94The following covergroups have been developed to prove that the test intent has been adequately met:
Guillermo Maturanaa2ca9982021-08-12 12:08:47 -070095* `reset_stretcher_cg`
96* `alert_info_cg`
97* `cpu_info_cg`
98* `alert_info_capture_cg`
99* `cpu_info_capture_cg`
Guillermo Maturana0f16fe02022-02-08 11:36:12 -0800100* `sw_rst_cg`
Guillermo Maturanaa2ca9982021-08-12 12:08:47 -0700101
Guillermo Maturana0fd914d2021-07-01 15:02:17 -0700102### Self-checking strategy
Guillermo Maturana0f16fe02022-02-08 11:36:12 -0800103Most self checking is done using SVA, and via explicit CSR reads.
104The latter are described in the testplan.
Guillermo Maturana0fd914d2021-07-01 15:02:17 -0700105
106#### Assertions
Hugo McNallyaef0a662023-02-11 19:44:55 +0000107* TLUL assertions: The `tb/rstmgr_bind.sv` file binds the `tlul_assert` [assertions](../../tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance.
Guillermo Maturana0fd914d2021-07-01 15:02:17 -0700108* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Guillermo Maturanaa2ca9982021-08-12 12:08:47 -0700109* Response to pwrmgr's `rst_lc_req` and `rst_sys_req` inputs: these trigger transitions in `rst_lc_src_n` and `rst_sys_rst_n` outputs.
Guillermo Maturana0f16fe02022-02-08 11:36:12 -0800110 Checked via SVAs in [`hw/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv).
Guillermo Maturanaa2ca9982021-08-12 12:08:47 -0700111* Response to `cpu_i.ndmreset_req` input: after it is asserted, rstmgr's `rst_sys_src_n` should go active.
Guillermo Maturana0f16fe02022-02-08 11:36:12 -0800112 Checked via SVA in [`hw/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv).
Hugo McNally544e7a62023-02-12 01:12:36 +0000113* Resets cascade hierarchically per [Reset Topology](../README.md#reset-topology).
Guillermo Maturana0f16fe02022-02-08 11:36:12 -0800114 Checked via SVA in [`hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv).
Guillermo Maturanabb09c792021-08-29 09:53:28 -0700115* POR must be active for at least 32 consecutive cycles before going inactive before output resets go inactive.
Guillermo Maturana0f16fe02022-02-08 11:36:12 -0800116 Checked via SVA in [`hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv).
Guillermo Maturanabb09c792021-08-29 09:53:28 -0700117* The scan reset `scan_rst_ni` qualified by `scanmode_i` triggers all cascaded resets that `por_n_i` does.
Guillermo Maturana0f16fe02022-02-08 11:36:12 -0800118 Checked via SVA in [`hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv).
119* Software resets to peripherals also cascade hierarchically.
120 Checked via SVA in [`hw/ip/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv).
121* The output `rst_en_o` for alert_handler tracks their corresponding resets.
122 Checked via SVA in both [`hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv) and [`hw/ip/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/ip/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv).
Guillermo Maturanaef60f5f2021-09-24 12:54:29 -0700123* The `alert` and `cpu_info_attr` indicate the number of 32-bit words needed to capture their inputs.
124 Checked via SVA in `hw/ip/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv`.
Guillermo Maturana0fd914d2021-07-01 15:02:17 -0700125
Guillermo Maturana0f16fe02022-02-08 11:36:12 -0800126## Testing V2S components
127The rstmgr_cnsty_chk module is a D2S component.
128It depends on very specific timing, and requires tampering stimulus to verify its functionality.
129It has its own separate dv environment and tests at `hw/ip/rstmgr/dv/rstmgr_cnsty_chk`.
130It is excluded from coverage for the rstmgr dv tests.
131
Guillermo Maturana0fd914d2021-07-01 15:02:17 -0700132## Building and running tests
Hugo McNallyaef0a662023-02-11 19:44:55 +0000133We are using our in-house developed [regression tool](../../../../util/dvsim/README.md) for building and running our tests and regressions.
Guillermo Maturana0fd914d2021-07-01 15:02:17 -0700134Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
135Here's how to run a smoke test:
136```console
137$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson -i rstmgr_smoke
138```
139
Srikrishna Iyer01c56b42021-08-02 12:50:11 -0700140## Testplan
Amaury Poulyb30b1fd2023-02-13 17:20:27 +0000141[Testplan](../data/rstmgr_testplan.hjson)