[dv, doc] Replace all 'dv.plan' with testplan
This commit purges all instances of "DV plan" to make the documentation
nomenclature as described in our DV methodology consistent.
what we capture in the HJSon -> testplan
what we capture in the markdown doc -> DV document
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/ip/rstmgr/doc/dv/index.md b/hw/ip/rstmgr/doc/dv/index.md
index c9d594a..02af673 100644
--- a/hw/ip/rstmgr/doc/dv/index.md
+++ b/hw/ip/rstmgr/doc/dv/index.md
@@ -14,7 +14,7 @@
## Goals
* **DV**
* Verify all RSTMGR IP features by running dynamic simulations with a SV/UVM based testbench
- * Develop and run all tests based on the [DV plan](#dv-plan) below towards closing code and functional coverage on the IP and all of its sub-modules
+ * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules
* **FPV**
* Verify TileLink device protocol compliance with an SVA based testbench
@@ -80,7 +80,7 @@
[Describe reference models in use if applicable, example: SHA256/HMAC]
### Stimulus strategy
-The following test sequences and covergroupsare described in more detail in the testplan at `hw/ip/pwrmgr/data/rstmgr_testplan.hjson`, and also included [below](#dv-plan).
+The following test sequences and covergroupsare described in more detail in the testplan at `hw/ip/pwrmgr/data/rstmgr_testplan.hjson`, and also included [below](#testplan).
#### Test sequences
The test sequences reside in `hw/ip/rstmgr/dv/env/seq_lib`.
@@ -121,7 +121,7 @@
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson -i rstmgr_smoke
```
-## DV plan
+## Testplan
<!-- TODO: uncomment the line below after adding the testplan.
Please make sure the testplan is added to `/util/build_docs.py`. -->
{{</* incGenFromIpDesc "hw/ip/rstmgr/data/rstmgr_testplan.hjson" "testplan" */>}}
