lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 1 | // Copyright lowRISC contributors. |
| 2 | // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| 3 | // SPDX-License-Identifier: Apache-2.0 |
| 4 | |
Weicai Yang | 67689cd | 2020-04-21 14:51:14 -0700 | [diff] [blame] | 5 | class chip_base_test extends cip_base_test #( |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 6 | .ENV_T(chip_env), |
| 7 | .CFG_T(chip_env_cfg) |
| 8 | ); |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 9 | `uvm_component_new |
Srikrishna Iyer | a6f0f3a | 2022-03-09 13:19:22 -0800 | [diff] [blame] | 10 | `uvm_component_utils(chip_base_test) |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 11 | |
Srikrishna Iyer | 9b340db | 2020-05-14 15:14:25 -0700 | [diff] [blame] | 12 | // The base class dv_base_test creates the following instances: |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 13 | // chip_env_cfg: cfg |
| 14 | // chip_env: env |
| 15 | |
Srikrishna Iyer | 9b340db | 2020-05-14 15:14:25 -0700 | [diff] [blame] | 16 | // The base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in |
| 17 | // the run_phase; as such, nothing more needs to be done. |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 18 | |
| 19 | virtual function void build_phase(uvm_phase phase); |
Michael Schaffner | 4c609f8 | 2021-03-04 18:20:43 -0800 | [diff] [blame] | 20 | string sw_images_plusarg; |
Srikrishna Iyer | d9881e4 | 2021-11-23 17:30:20 -0800 | [diff] [blame] | 21 | string use_otp_image_plusarg; |
| 22 | |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 23 | super.build_phase(phase); |
Michael Schaffner | 4c609f8 | 2021-03-04 18:20:43 -0800 | [diff] [blame] | 24 | |
Srikrishna Iyer | cb1c9d0 | 2021-11-15 17:18:25 -0800 | [diff] [blame] | 25 | // Set the number of RAM tiles (1 each). |
| 26 | cfg.num_ram_main_tiles = 1; |
| 27 | cfg.num_ram_ret_tiles = 1; |
Michael Schaffner | f8144ad | 2022-08-22 15:21:56 -0700 | [diff] [blame] | 28 | cfg.num_otbn_dmem_tiles = 1; |
Srikrishna Iyer | cb1c9d0 | 2021-11-15 17:18:25 -0800 | [diff] [blame] | 29 | |
Srikrishna Iyer | 64346b4 | 2022-09-13 16:25:10 -0700 | [diff] [blame] | 30 | // Knob to select the chip clock source. |
| 31 | `DV_GET_ENUM_PLUSARG(chip_clock_source_e, cfg.chip_clock_source, chip_clock_source) |
| 32 | if (cfg.chip_clock_source != ChipClockSourceInternal) begin |
| 33 | cfg.clk_freq_mhz = cfg.chip_clock_source; |
| 34 | end |
| 35 | |
Srikrishna Iyer | 9b340db | 2020-05-14 15:14:25 -0700 | [diff] [blame] | 36 | // Knob to set the UART baud rate (set to 2M by default). |
| 37 | void'($value$plusargs("uart_baud_rate=%0d", cfg.uart_baud_rate)); |
| 38 | |
Michael Schaffner | 4c609f8 | 2021-03-04 18:20:43 -0800 | [diff] [blame] | 39 | // The following plusargs are only valid for SW based tests (i.e., no stubbed CPU). |
| 40 | // Knob to configure writing sw logs to a separate file (enabled by default). |
| 41 | void'($value$plusargs("write_sw_logs_to_file=%0b", cfg.write_sw_logs_to_file)); |
Srikrishna Iyer | 3cb7c16 | 2020-04-22 14:45:00 -0700 | [diff] [blame] | 42 | |
Michael Schaffner | 4c609f8 | 2021-03-04 18:20:43 -0800 | [diff] [blame] | 43 | // Knob to enable logging over UART (disabled by default). |
| 44 | void'($value$plusargs("en_uart_logger=%0b", cfg.en_uart_logger)); |
Weicai Yang | ad5907d | 2021-03-09 17:37:44 -0800 | [diff] [blame] | 45 | cfg.m_uart_agent_cfgs[0].en_logger = cfg.en_uart_logger; |
| 46 | cfg.m_uart_agent_cfgs[0].write_logs_to_file = cfg.write_sw_logs_to_file; |
Weicai Yang | 67689cd | 2020-04-21 14:51:14 -0700 | [diff] [blame] | 47 | |
Timothy Chen | 2fb2767 | 2022-09-09 12:20:00 -0700 | [diff] [blame] | 48 | // all the spi_agents talking to the host interface should be configured into |
| 49 | // device mode |
| 50 | foreach (cfg.m_spi_device_agent_cfgs[i]) begin |
| 51 | cfg.m_spi_device_agent_cfgs[i].if_mode = dv_utils_pkg::Device; |
| 52 | end |
| 53 | |
Srikrishna Iyer | 5e40007 | 2022-04-05 16:12:27 -0700 | [diff] [blame] | 54 | // Knob to set the sw_test_timeout_ns (set to 12ms by default). |
Michael Schaffner | 4c609f8 | 2021-03-04 18:20:43 -0800 | [diff] [blame] | 55 | void'($value$plusargs("sw_test_timeout_ns=%0d", cfg.sw_test_timeout_ns)); |
Weicai Yang | 50f2f52 | 2020-08-27 15:10:51 -0700 | [diff] [blame] | 56 | |
Michael Schaffner | 4c609f8 | 2021-03-04 18:20:43 -0800 | [diff] [blame] | 57 | // Knob to use SPI to load image via ROM bootstrap. |
| 58 | void'($value$plusargs("use_spi_load_bootstrap=%0b", cfg.use_spi_load_bootstrap)); |
Srikrishna Iyer | 1bd0adf | 2020-10-14 11:55:30 -0700 | [diff] [blame] | 59 | |
Michael Schaffner | 4c609f8 | 2021-03-04 18:20:43 -0800 | [diff] [blame] | 60 | // Knob to indicate what build device to use (DV, Verilator or FPGA). |
| 61 | void'($value$plusargs("sw_build_device=%0s", cfg.sw_build_device)); |
Srikrishna Iyer | 1076358 | 2020-11-20 23:36:50 -0800 | [diff] [blame] | 62 | |
Michael Schaffner | 4c609f8 | 2021-03-04 18:20:43 -0800 | [diff] [blame] | 63 | // Knob to set custom sw image names for rom and sw. |
| 64 | if ($value$plusargs("sw_images=%0s", sw_images_plusarg)) begin |
| 65 | cfg.parse_sw_images_string(sw_images_plusarg); |
Srikrishna Iyer | 1bd0adf | 2020-10-14 11:55:30 -0700 | [diff] [blame] | 66 | end |
Srikrishna Iyer | d9881e4 | 2021-11-23 17:30:20 -0800 | [diff] [blame] | 67 | |
Srikrishna Iyer | 3fe9fdd | 2022-03-17 14:37:31 -0700 | [diff] [blame] | 68 | // Knob to perform the AST configuration. |
| 69 | void'($value$plusargs("do_creator_sw_cfg_ast_cfg=%0b", cfg.do_creator_sw_cfg_ast_cfg)); |
| 70 | |
Srikrishna Iyer | a6f0f3a | 2022-03-09 13:19:22 -0800 | [diff] [blame] | 71 | // Override the initial AST configuration data at runtime via plusarg. |
| 72 | foreach (cfg.creator_sw_cfg_ast_cfg_data[i]) begin |
| 73 | void'($value$plusargs({$sformatf("creator_sw_cfg_ast_cfg_data[%0d]", i), "=%0h"}, |
| 74 | cfg.creator_sw_cfg_ast_cfg_data[i])); |
| 75 | end |
| 76 | |
Srikrishna Iyer | d9881e4 | 2021-11-23 17:30:20 -0800 | [diff] [blame] | 77 | // Knob to select the OTP image based on LC state. |
Timothy Trippel | 0417911 | 2022-11-04 16:06:35 -0700 | [diff] [blame] | 78 | `DV_GET_ENUM_PLUSARG(otp_type_e, cfg.use_otp_image, use_otp_image) |
Srikrishna Iyer | d9881e4 | 2021-11-23 17:30:20 -0800 | [diff] [blame] | 79 | `DV_CHECK_FATAL(cfg.otp_images.exists(cfg.use_otp_image), |
| 80 | $sformatf({"Unsupported plusarg value: +use_otp_image=%0s. An image associated", |
| 81 | "with this LC state needs to be created first."}, cfg.use_otp_image)) |
Srikrishna Iyer | 5e40007 | 2022-04-05 16:12:27 -0700 | [diff] [blame] | 82 | |
| 83 | // Set the test timeout value to be sufficiently large. |
| 84 | test_timeout_ns = 50_000_000; |
| 85 | test_timeout_ns = `DV_MAX2(test_timeout_ns, 5 * cfg.sw_test_timeout_ns); |
Srikrishna Iyer | 305072a | 2022-07-22 15:42:41 -0700 | [diff] [blame] | 86 | `uvm_info(`gfn, $sformatf("test_timeout_ns = %0d", test_timeout_ns), UVM_LOW) |
Srikrishna Iyer | 97fe0d8 | 2020-03-06 13:24:16 -0800 | [diff] [blame] | 87 | endfunction : build_phase |
lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 88 | |
| 89 | endclass : chip_base_test |