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lowRISC Contributors802543a2019-08-31 12:12:56 +01001// Copyright lowRISC contributors.
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
Weicai Yang67689cd2020-04-21 14:51:14 -07005class chip_base_test extends cip_base_test #(
lowRISC Contributors802543a2019-08-31 12:12:56 +01006 .ENV_T(chip_env),
7 .CFG_T(chip_env_cfg)
8 );
lowRISC Contributors802543a2019-08-31 12:12:56 +01009 `uvm_component_new
Srikrishna Iyera6f0f3a2022-03-09 13:19:22 -080010 `uvm_component_utils(chip_base_test)
lowRISC Contributors802543a2019-08-31 12:12:56 +010011
Srikrishna Iyer9b340db2020-05-14 15:14:25 -070012 // The base class dv_base_test creates the following instances:
lowRISC Contributors802543a2019-08-31 12:12:56 +010013 // chip_env_cfg: cfg
14 // chip_env: env
15
Srikrishna Iyer9b340db2020-05-14 15:14:25 -070016 // The base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in
17 // the run_phase; as such, nothing more needs to be done.
lowRISC Contributors802543a2019-08-31 12:12:56 +010018
19 virtual function void build_phase(uvm_phase phase);
Michael Schaffner4c609f82021-03-04 18:20:43 -080020 string sw_images_plusarg;
Srikrishna Iyerd9881e42021-11-23 17:30:20 -080021 string use_otp_image_plusarg;
22
lowRISC Contributors802543a2019-08-31 12:12:56 +010023 super.build_phase(phase);
Michael Schaffner4c609f82021-03-04 18:20:43 -080024
Srikrishna Iyercb1c9d02021-11-15 17:18:25 -080025 // Set the number of RAM tiles (1 each).
26 cfg.num_ram_main_tiles = 1;
27 cfg.num_ram_ret_tiles = 1;
Michael Schaffnerf8144ad2022-08-22 15:21:56 -070028 cfg.num_otbn_dmem_tiles = 1;
Srikrishna Iyercb1c9d02021-11-15 17:18:25 -080029
Srikrishna Iyer64346b42022-09-13 16:25:10 -070030 // Knob to select the chip clock source.
31 `DV_GET_ENUM_PLUSARG(chip_clock_source_e, cfg.chip_clock_source, chip_clock_source)
32 if (cfg.chip_clock_source != ChipClockSourceInternal) begin
33 cfg.clk_freq_mhz = cfg.chip_clock_source;
34 end
35
Srikrishna Iyer9b340db2020-05-14 15:14:25 -070036 // Knob to set the UART baud rate (set to 2M by default).
37 void'($value$plusargs("uart_baud_rate=%0d", cfg.uart_baud_rate));
38
Michael Schaffner4c609f82021-03-04 18:20:43 -080039 // The following plusargs are only valid for SW based tests (i.e., no stubbed CPU).
40 // Knob to configure writing sw logs to a separate file (enabled by default).
41 void'($value$plusargs("write_sw_logs_to_file=%0b", cfg.write_sw_logs_to_file));
Srikrishna Iyer3cb7c162020-04-22 14:45:00 -070042
Michael Schaffner4c609f82021-03-04 18:20:43 -080043 // Knob to enable logging over UART (disabled by default).
44 void'($value$plusargs("en_uart_logger=%0b", cfg.en_uart_logger));
Weicai Yangad5907d2021-03-09 17:37:44 -080045 cfg.m_uart_agent_cfgs[0].en_logger = cfg.en_uart_logger;
46 cfg.m_uart_agent_cfgs[0].write_logs_to_file = cfg.write_sw_logs_to_file;
Weicai Yang67689cd2020-04-21 14:51:14 -070047
Timothy Chen2fb27672022-09-09 12:20:00 -070048 // all the spi_agents talking to the host interface should be configured into
49 // device mode
50 foreach (cfg.m_spi_device_agent_cfgs[i]) begin
51 cfg.m_spi_device_agent_cfgs[i].if_mode = dv_utils_pkg::Device;
52 end
53
Srikrishna Iyer5e400072022-04-05 16:12:27 -070054 // Knob to set the sw_test_timeout_ns (set to 12ms by default).
Michael Schaffner4c609f82021-03-04 18:20:43 -080055 void'($value$plusargs("sw_test_timeout_ns=%0d", cfg.sw_test_timeout_ns));
Weicai Yang50f2f522020-08-27 15:10:51 -070056
Michael Schaffner4c609f82021-03-04 18:20:43 -080057 // Knob to use SPI to load image via ROM bootstrap.
58 void'($value$plusargs("use_spi_load_bootstrap=%0b", cfg.use_spi_load_bootstrap));
Srikrishna Iyer1bd0adf2020-10-14 11:55:30 -070059
Michael Schaffner4c609f82021-03-04 18:20:43 -080060 // Knob to indicate what build device to use (DV, Verilator or FPGA).
61 void'($value$plusargs("sw_build_device=%0s", cfg.sw_build_device));
Srikrishna Iyer10763582020-11-20 23:36:50 -080062
Michael Schaffner4c609f82021-03-04 18:20:43 -080063 // Knob to set custom sw image names for rom and sw.
64 if ($value$plusargs("sw_images=%0s", sw_images_plusarg)) begin
65 cfg.parse_sw_images_string(sw_images_plusarg);
Srikrishna Iyer1bd0adf2020-10-14 11:55:30 -070066 end
Srikrishna Iyerd9881e42021-11-23 17:30:20 -080067
Srikrishna Iyer3fe9fdd2022-03-17 14:37:31 -070068 // Knob to perform the AST configuration.
69 void'($value$plusargs("do_creator_sw_cfg_ast_cfg=%0b", cfg.do_creator_sw_cfg_ast_cfg));
70
Srikrishna Iyera6f0f3a2022-03-09 13:19:22 -080071 // Override the initial AST configuration data at runtime via plusarg.
72 foreach (cfg.creator_sw_cfg_ast_cfg_data[i]) begin
73 void'($value$plusargs({$sformatf("creator_sw_cfg_ast_cfg_data[%0d]", i), "=%0h"},
74 cfg.creator_sw_cfg_ast_cfg_data[i]));
75 end
76
Srikrishna Iyerd9881e42021-11-23 17:30:20 -080077 // Knob to select the OTP image based on LC state.
Timothy Trippel04179112022-11-04 16:06:35 -070078 `DV_GET_ENUM_PLUSARG(otp_type_e, cfg.use_otp_image, use_otp_image)
Srikrishna Iyerd9881e42021-11-23 17:30:20 -080079 `DV_CHECK_FATAL(cfg.otp_images.exists(cfg.use_otp_image),
80 $sformatf({"Unsupported plusarg value: +use_otp_image=%0s. An image associated",
81 "with this LC state needs to be created first."}, cfg.use_otp_image))
Srikrishna Iyer5e400072022-04-05 16:12:27 -070082
83 // Set the test timeout value to be sufficiently large.
84 test_timeout_ns = 50_000_000;
85 test_timeout_ns = `DV_MAX2(test_timeout_ns, 5 * cfg.sw_test_timeout_ns);
Srikrishna Iyer305072a2022-07-22 15:42:41 -070086 `uvm_info(`gfn, $sformatf("test_timeout_ns = %0d", test_timeout_ns), UVM_LOW)
Srikrishna Iyer97fe0d82020-03-06 13:24:16 -080087 endfunction : build_phase
lowRISC Contributors802543a2019-08-31 12:12:56 +010088
89endclass : chip_base_test