| lowRISC Contributors | 802543a | 2019-08-31 12:12:56 +0100 | [diff] [blame] | 1 | # FPGA Splice flow |
| 2 | This is a FPGA utiity script which embedds the generated rom elf file into FPGA bitstream. |
| 3 | Script assumes there is pre-generated fpga bit file in the build directory.The boot rom mem file is auto generated. |
| 4 | |
| 5 | ## How to run the script |
| 6 | Utility script to load MEM contents into BRAM FPGA bitfile. |
| 7 | * Usage: |
| 8 | ```console |
| 9 | $ cd $REPO_TOP |
| 10 | $ ./util/fpga/splice_nexysvideo.sh |
| 11 | ``` |
| 12 | |
| 13 | Updated output bitfile located : at the same place as raw vivado bitfile @ |
| 14 | `build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.splice.bit` |
| 15 | |
| 16 | This directory contains following files |
| 17 | * splice_nexysvideo.sh - master script |
| 18 | * bram_load.mmi - format which vivado tool understands on which FPGA BRAM locations the SW contents should go |
| 19 | * addr4x.py - utility script used underneath to do address calculation to map with FPGA BRAM architecture |
