Start of public OpenTitan development history
Code contributors:
Alex Bradbury <asb@lowrisc.org>
Cindy Chen <chencindy@google.com>
Eunchan Kim <eunchan@google.com>
Gaurang Chitroda <gaurangg@google.com>
Mark Hayter <mark.hayter@gmail.com>
Michael Schaffner <msf@google.com>
Miguel Osorio <miguelosorio@google.com>
Nils Graf <nilsg@google.com>
Philipp Wagner <phw@lowrisc.org>
Pirmin Vogel <vogelpi@lowrisc.org>
Ram Babu Penugonda <rampenugonda@google.com>
Scott Johnson <scottdj@google.com>
Shail Kushwah <kushwahs@google.com>
Srikrishna Iyer <sriyer@google.com>
Steve Nelson <Steve.Nelson@wdc.com>
Tao Liu <taliu@google.com>
Timothy Chen <timothytim@google.com>
Tobias Wölfel <tobias.woelfel@mailbox.org>
Weicai Yang <weicai@google.com>
diff --git a/util/fpga/README.md b/util/fpga/README.md
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+++ b/util/fpga/README.md
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+# FPGA Splice flow
+This is a FPGA utiity script which embedds the generated rom elf file into FPGA bitstream.
+Script assumes there is pre-generated fpga bit file in the build directory.The boot rom mem file is auto generated.
+
+## How to run the script
+Utility script to load MEM contents into BRAM FPGA bitfile.
+* Usage:
+```console
+$ cd $REPO_TOP
+$ ./util/fpga/splice_nexysvideo.sh
+```
+
+Updated output bitfile located : at the same place as raw vivado bitfile @
+`build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.splice.bit`
+
+This directory contains following files
+* splice_nexysvideo.sh - master script
+* bram_load.mmi - format which vivado tool understands on which FPGA BRAM locations the SW contents should go
+* addr4x.py - utility script used underneath to do address calculation to map with FPGA BRAM architecture
