Start of public OpenTitan development history
Code contributors:
Alex Bradbury <asb@lowrisc.org>
Cindy Chen <chencindy@google.com>
Eunchan Kim <eunchan@google.com>
Gaurang Chitroda <gaurangg@google.com>
Mark Hayter <mark.hayter@gmail.com>
Michael Schaffner <msf@google.com>
Miguel Osorio <miguelosorio@google.com>
Nils Graf <nilsg@google.com>
Philipp Wagner <phw@lowrisc.org>
Pirmin Vogel <vogelpi@lowrisc.org>
Ram Babu Penugonda <rampenugonda@google.com>
Scott Johnson <scottdj@google.com>
Shail Kushwah <kushwahs@google.com>
Srikrishna Iyer <sriyer@google.com>
Steve Nelson <Steve.Nelson@wdc.com>
Tao Liu <taliu@google.com>
Timothy Chen <timothytim@google.com>
Tobias Wölfel <tobias.woelfel@mailbox.org>
Weicai Yang <weicai@google.com>
diff --git a/util/fpga/README.md b/util/fpga/README.md
new file mode 100644
index 0000000..969e2af
--- /dev/null
+++ b/util/fpga/README.md
@@ -0,0 +1,19 @@
+# FPGA Splice flow
+This is a FPGA utiity script which embedds the generated rom elf file into FPGA bitstream.
+Script assumes there is pre-generated fpga bit file in the build directory.The boot rom mem file is auto generated.
+
+## How to run the script
+Utility script to load MEM contents into BRAM FPGA bitfile.
+* Usage:
+```console
+$ cd $REPO_TOP
+$ ./util/fpga/splice_nexysvideo.sh
+```
+
+Updated output bitfile located : at the same place as raw vivado bitfile @
+`build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.splice.bit`
+
+This directory contains following files
+* splice_nexysvideo.sh - master script
+* bram_load.mmi - format which vivado tool understands on which FPGA BRAM locations the SW contents should go
+* addr4x.py - utility script used underneath to do address calculation to map with FPGA BRAM architecture
diff --git a/util/fpga/addr4x.py b/util/fpga/addr4x.py
new file mode 100755
index 0000000..4f1b14c
--- /dev/null
+++ b/util/fpga/addr4x.py
@@ -0,0 +1,56 @@
+#!/usr/bin/env python3
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+"""Utility script
+Handles linear addresses generated from srec_cat to suit with fpga BRAM
+architecture which need word addressing.. Example
+0x0 0x00000010
+0x1 0x000000FF
+0x2 0x00000088
+
+get converted to
+
+0x0 0x00000010
+0x4 0x000000FF
+0x8 0x00000088 """
+
+import argparse
+import imp
+import logging
+import os
+import sys
+from pathlib import Path
+
+DESC = """addr4x.py script handles the address generated in mem file from
+srec_cat to suit with BRAM memory architecture which need word addressing"""
+
+
+def main(argv):
+ parser = argparse.ArgumentParser(prog="addr4x.py", description=DESC)
+ parser.add_argument('--infile',
+ '-i',
+ dest='inputfile',
+ type=argparse.FileType('r', encoding='UTF-8'),
+ required=True,
+ help='Input Mem file')
+ parser.add_argument('--outfile',
+ '-o',
+ dest='outputfile',
+ type=argparse.FileType('w', encoding='UTF-8'),
+ required=True,
+ help='Output Mem file')
+ args = parser.parse_args()
+ in_file_path = Path(args.inputfile.name).resolve()
+ with open(in_file_path) as file:
+ for line in file:
+ if "sourceforge" not in line:
+ a = line.split("@")
+ b = a[1].split(" ")
+ mult = int(b[0], 16)
+ final = "@" + hex(mult * 4)[2:] + " " + b[1]
+ args.outputfile.write(final)
+
+
+if __name__ == "__main__":
+ main(sys.argv)
diff --git a/util/fpga/bram_load.mmi b/util/fpga/bram_load.mmi
new file mode 100644
index 0000000..3f31a1b
--- /dev/null
+++ b/util/fpga/bram_load.mmi
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<MemInfo Version="1" Minor="0">
+ <Processor Endianness="Little" InstPath="dummy">
+ <AddressSpace Name="axi_bram_ctrl_0_bram" Begin="0" End="8191">
+ <BusBlock>
+ <BitLane MemType="RAMB32" Placement="X4Y18">
+ <DataWidth MSB="15" LSB="0"/>
+ <AddressRange Begin="0" End="2047"/>
+ <Parity ON="false" NumBits="0"/>
+ </BitLane>
+ <BitLane MemType="RAMB32" Placement="X4Y19">
+ <DataWidth MSB="31" LSB="16"/>
+ <AddressRange Begin="0" End="2047"/>
+ <Parity ON="false" NumBits="0"/>
+ </BitLane>
+ </BusBlock>
+ </AddressSpace>
+ </Processor>
+<Config>
+ <Option Name="Part" Val="xc7a200tsbg484-1"/>
+</Config>
+</MemInfo>
diff --git a/util/fpga/splice_nexysvideo.sh b/util/fpga/splice_nexysvideo.sh
new file mode 100755
index 0000000..f66440f
--- /dev/null
+++ b/util/fpga/splice_nexysvideo.sh
@@ -0,0 +1,28 @@
+#!/bin/bash
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+
+# Utility script to load MEM contents into BRAM FPGA bitfile
+# Usage:
+# cd $REPO_TOP
+# ./util/fpga/splice_nexysvideo.sh
+
+# Updated bitfile located : at the same place as raw vivado bitfile @
+# $REPO_TOP/build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/
+# lowrisc_systems_top_earlgrey_nexysvideo_0.1.splice.bit
+
+
+PROGRAM=boot_rom
+
+cd sw/boot_rom
+make clean ; make
+srec_cat ${PROGRAM}.bin -binary -offset 0x0 -o ${PROGRAM}.brammem \
+ -vmem -Output_Block_Size 4;
+../../util/fpga/addr4x.py -i ${PROGRAM}.brammem -o ${PROGRAM}.mem
+updatemem -force --meminfo ../../util/fpga/bram_load.mmi --data ${PROGRAM}.mem \
+ --bit ../../build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/\
+lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit --proc dummy \
+ --out ../../build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/\
+lowrisc_systems_top_earlgrey_nexysvideo_0.1.splice.bit
